diff options
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1')
26 files changed, 263 insertions, 922 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 88c2e51ab166..9f2164782844 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -320,7 +320,7 @@ static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc, } static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, - struct dpu_plane_state *pstate, struct dpu_format *format) + struct dpu_plane_state *pstate, const struct msm_format *format) { struct dpu_hw_mixer *lm = mixer->hw_lm; uint32_t blend_op; @@ -363,7 +363,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, fg_alpha, bg_alpha, blend_op); DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n", - &format->base.pixel_format, format->alpha_enable, blend_op); + &format->pixel_format, format->alpha_enable, blend_op); } static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) @@ -395,7 +395,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, struct dpu_crtc_mixer *mixer, u32 num_mixers, enum dpu_stage stage, - struct dpu_format *format, + const struct msm_format *format, uint64_t modifier, struct dpu_sw_pipe *pipe, unsigned int stage_idx, @@ -412,7 +412,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), state, to_dpu_plane_state(state), stage_idx, - format->base.pixel_format, + format->pixel_format, modifier); DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n", @@ -440,7 +440,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, struct drm_plane_state *state; struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); struct dpu_plane_state *pstate = NULL; - struct dpu_format *format; + const struct msm_format *format; struct dpu_hw_ctl *ctl = mixer->lm_ctl; uint32_t lm_idx; @@ -459,7 +459,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, pstate = to_dpu_plane_state(state); fb = state->fb; - format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); + format = msm_framebuffer_format(pstate->base.fb); if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable = true; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 9a14d2232e4a..119f3ea50a7c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -675,7 +675,7 @@ static int dpu_encoder_virt_atomic_check( if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) { fb = conn_state->writeback_job->fb; - if (fb && DPU_FORMAT_IS_YUV(to_dpu_format(msm_framebuffer_format(fb)))) + if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb))) topology.needs_cdm = true; } else if (disp_info->intf_type == INTF_DP) { if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], adj_mode)) @@ -2184,7 +2184,7 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) } void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, - const struct dpu_format *dpu_fmt, + const struct msm_format *dpu_fmt, u32 output_type) { struct dpu_hw_cdm *hw_cdm; @@ -2202,9 +2202,9 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, if (!hw_cdm) return; - if (!DPU_FORMAT_IS_YUV(dpu_fmt)) { - DPU_DEBUG("[enc:%d] cdm_disable fmt:%x\n", DRMID(phys_enc->parent), - dpu_fmt->base.pixel_format); + if (!MSM_FORMAT_IS_YUV(dpu_fmt)) { + DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent), + &dpu_fmt->pixel_format); if (hw_cdm->ops.bind_pingpong_blk) hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE); @@ -2217,25 +2217,25 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, cdm_cfg->output_height = phys_enc->cached_mode.vdisplay; cdm_cfg->output_fmt = dpu_fmt; cdm_cfg->output_type = output_type; - cdm_cfg->output_bit_depth = DPU_FORMAT_IS_DX(dpu_fmt) ? + cdm_cfg->output_bit_depth = MSM_FORMAT_IS_DX(dpu_fmt) ? CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT; cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l; /* enable 10 bit logic */ switch (cdm_cfg->output_fmt->chroma_sample) { - case DPU_CHROMA_RGB: + case CHROMA_FULL: cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE; cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; break; - case DPU_CHROMA_H2V1: + case CHROMA_H2V1: cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE; cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; break; - case DPU_CHROMA_420: + case CHROMA_420: cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE; cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE; break; - case DPU_CHROMA_H1V2: + case CHROMA_H1V2: default: DPU_ERROR("[enc:%d] unsupported chroma sampling type\n", DRMID(phys_enc->parent)); @@ -2244,9 +2244,9 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, break; } - DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n", + DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%p4cc,%d,%d,%d,%d]\n", DRMID(phys_enc->parent), cdm_cfg->output_width, - cdm_cfg->output_height, cdm_cfg->output_fmt->base.pixel_format, + cdm_cfg->output_height, &cdm_cfg->output_fmt->pixel_format, cdm_cfg->output_type, cdm_cfg->output_bit_depth, cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index 98d1b64a43e8..002e89cc1705 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -393,7 +393,7 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc); * @output_type: HDMI/WB */ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, - const struct dpu_format *dpu_fmt, + const struct msm_format *dpu_fmt, u32 output_type); /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index fc1d5736d7fc..489be1c0c704 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -448,9 +448,6 @@ static void dpu_encoder_phys_cmd_enable_helper( _dpu_encoder_phys_cmd_pingpong_config(phys_enc); - if (!dpu_encoder_phys_cmd_is_master(phys_enc)) - return; - ctl = phys_enc->hw_ctl; ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index d9e7dbf0499c..ef69c2f408c3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -235,7 +235,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( { struct drm_display_mode mode; struct dpu_hw_intf_timing_params timing_params = { 0 }; - const struct dpu_format *fmt = NULL; + const struct msm_format *fmt = NULL; u32 fmt_fourcc; unsigned long lock_flags; struct dpu_hw_intf_cfg intf_cfg = { 0 }; @@ -274,7 +274,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params); - fmt = dpu_get_dpu_format(fmt_fourcc); + fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0); DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc); if (phys_enc->hw_cdm) @@ -409,12 +409,12 @@ end: static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) { struct dpu_hw_ctl *ctl; - const struct dpu_format *fmt; + const struct msm_format *fmt; u32 fmt_fourcc; ctl = phys_enc->hw_ctl; fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc); - fmt = dpu_get_dpu_format(fmt_fourcc); + fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0); DPU_DEBUG_VIDENC(phys_enc, "\n"); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 1924a2b28e53..d3ea91c1d7d2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -322,11 +322,11 @@ static void dpu_encoder_phys_wb_setup( struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc); struct drm_writeback_job *wb_job; const struct msm_format *format; - const struct dpu_format *dpu_fmt; + const struct msm_format *dpu_fmt; wb_job = wb_enc->wb_job; format = msm_framebuffer_format(wb_enc->wb_job->fb); - dpu_fmt = dpu_get_dpu_format_ext(format->pixel_format, wb_job->fb->modifier); + dpu_fmt = mdp_get_format(&phys_enc->dpu_kms->base, format->pixel_format, wb_job->fb->modifier); DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n", hw_wb->idx - WB_0, mode.name, @@ -576,11 +576,11 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc format = msm_framebuffer_format(job->fb); - wb_cfg->dest.format = dpu_get_dpu_format_ext( - format->pixel_format, job->fb->modifier); + wb_cfg->dest.format = mdp_get_format(&phys_enc->dpu_kms->base, + format->pixel_format, job->fb->modifier); if (!wb_cfg->dest.format) { /* this error should be detected during atomic_check */ - DPU_ERROR("failed to get format %x\n", format->pixel_format); + DPU_ERROR("failed to get format %p4cc\n", &format->pixel_format); return; } @@ -594,7 +594,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc wb_cfg->dest.height = job->fb->height; wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes; - if ((wb_cfg->dest.format->fetch_planes == DPU_PLANE_PLANAR) && + if ((wb_cfg->dest.format->fetch_type == MDP_PLANE_PLANAR) && (wb_cfg->dest.format->element[0] == C1_B_Cb)) swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c index e366ab134249..6b1e9a617da3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c @@ -11,179 +11,12 @@ #include "dpu_kms.h" #include "dpu_formats.h" -#define DPU_UBWC_META_MACRO_W_H 16 -#define DPU_UBWC_META_BLOCK_SIZE 256 #define DPU_UBWC_PLANE_SIZE_ALIGNMENT 4096 -#define DPU_TILE_HEIGHT_DEFAULT 1 -#define DPU_TILE_HEIGHT_TILED 4 -#define DPU_TILE_HEIGHT_UBWC 4 -#define DPU_TILE_HEIGHT_NV12 8 - #define DPU_MAX_IMG_WIDTH 0x3FFF #define DPU_MAX_IMG_HEIGHT 0x3FFF /* - * DPU supported format packing, bpp, and other format - * information. - * DPU currently only supports interleaved RGB formats - * UBWC support for a pixel format is indicated by the flag, - * there is additional meta data plane for such formats - */ - -#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \ -bp, flg, fm, np) \ -{ \ - .base.pixel_format = DRM_FORMAT_ ## fmt, \ - .fetch_planes = DPU_PLANE_INTERLEAVED, \ - .alpha_enable = alpha, \ - .element = { (e0), (e1), (e2), (e3) }, \ - .bits = { g, b, r, a }, \ - .chroma_sample = DPU_CHROMA_RGB, \ - .unpack_align_msb = 0, \ - .unpack_tight = 1, \ - .unpack_count = uc, \ - .bpp = bp, \ - .fetch_mode = fm, \ - .flag = {(flg)}, \ - .num_planes = np, \ - .tile_height = DPU_TILE_HEIGHT_DEFAULT \ -} - -#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \ -alpha, bp, flg, fm, np, th) \ -{ \ - .base.pixel_format = DRM_FORMAT_ ## fmt, \ - .fetch_planes = DPU_PLANE_INTERLEAVED, \ - .alpha_enable = alpha, \ - .element = { (e0), (e1), (e2), (e3) }, \ - .bits = { g, b, r, a }, \ - .chroma_sample = DPU_CHROMA_RGB, \ - .unpack_align_msb = 0, \ - .unpack_tight = 1, \ - .unpack_count = uc, \ - .bpp = bp, \ - .fetch_mode = fm, \ - .flag = {(flg)}, \ - .num_planes = np, \ - .tile_height = th \ -} - - -#define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3, \ -alpha, chroma, count, bp, flg, fm, np) \ -{ \ - .base.pixel_format = DRM_FORMAT_ ## fmt, \ - .fetch_planes = DPU_PLANE_INTERLEAVED, \ - .alpha_enable = alpha, \ - .element = { (e0), (e1), (e2), (e3)}, \ - .bits = { g, b, r, a }, \ - .chroma_sample = chroma, \ - .unpack_align_msb = 0, \ - .unpack_tight = 1, \ - .unpack_count = count, \ - .bpp = bp, \ - .fetch_mode = fm, \ - .flag = {(flg)}, \ - .num_planes = np, \ - .tile_height = DPU_TILE_HEIGHT_DEFAULT \ -} - -#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \ -{ \ - .base.pixel_format = DRM_FORMAT_ ## fmt, \ - .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \ - .alpha_enable = false, \ - .element = { (e0), (e1), 0, 0 }, \ - .bits = { g, b, r, a }, \ - .chroma_sample = chroma, \ - .unpack_align_msb = 0, \ - .unpack_tight = 1, \ - .unpack_count = 2, \ - .bpp = 2, \ - .fetch_mode = fm, \ - .flag = {(flg)}, \ - .num_planes = np, \ - .tile_height = DPU_TILE_HEIGHT_DEFAULT \ -} - -#define PSEUDO_YUV_FMT_TILED(fmt, a, r, g, b, e0, e1, chroma, \ -flg, fm, np, th) \ -{ \ - .base.pixel_format = DRM_FORMAT_ ## fmt, \ - .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \ - .alpha_enable = false, \ - .element = { (e0), (e1), 0, 0 }, \ - .bits = { g, b, r, a }, \ - .chroma_sample = chroma, \ - .unpack_align_msb = 0, \ - .unpack_tight = 1, \ - .unpack_count = 2, \ - .bpp = 2, \ - .fetch_mode = fm, \ - .flag = {(flg)}, \ - .num_planes = np, \ - .tile_height = th \ -} - -#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\ -{ \ - .base.pixel_format = DRM_FORMAT_ ## fmt, \ - .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \ - .alpha_enable = false, \ - .element = { (e0), (e1), 0, 0 }, \ - .bits = { g, b, r, a }, \ - .chroma_sample = chroma, \ - .unpack_align_msb = 1, \ - .unpack_tight = 0, \ - .unpack_count = 2, \ - .bpp = 2, \ - .fetch_mode = fm, \ - .flag = {(flg)}, \ - .num_planes = np, \ - .tile_height = DPU_TILE_HEIGHT_DEFAULT \ -} - -#define PSEUDO_YUV_FMT_LOOSE_TILED(fmt, a, r, g, b, e0, e1, chroma, \ -flg, fm, np, th) \ -{ \ - .base.pixel_format = DRM_FORMAT_ ## fmt, \ - .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \ - .alpha_enable = false, \ - .element = { (e0), (e1), 0, 0 }, \ - .bits = { g, b, r, a }, \ - .chroma_sample = chroma, \ - .unpack_align_msb = 1, \ - .unpack_tight = 0, \ - .unpack_count = 2, \ - .bpp = 2, \ - .fetch_mode = fm, \ - .flag = {(flg)}, \ - .num_planes = np, \ - .tile_height = th \ -} - - -#define PLANAR_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, alpha, chroma, bp, \ -flg, fm, np) \ -{ \ - .base.pixel_format = DRM_FORMAT_ ## fmt, \ - .fetch_planes = DPU_PLANE_PLANAR, \ - .alpha_enable = alpha, \ - .element = { (e0), (e1), (e2), 0 }, \ - .bits = { g, b, r, a }, \ - .chroma_sample = chroma, \ - .unpack_align_msb = 0, \ - .unpack_tight = 1, \ - .unpack_count = 1, \ - .bpp = bp, \ - .fetch_mode = fm, \ - .flag = {(flg)}, \ - .num_planes = np, \ - .tile_height = DPU_TILE_HEIGHT_DEFAULT \ -} - -/* * struct dpu_media_color_map - maps drm format to media format * @format: DRM base pixel format * @color: Media API color related to DRM format @@ -193,380 +26,11 @@ struct dpu_media_color_map { uint32_t color; }; -static const struct dpu_format dpu_format_map[] = { - INTERLEAVED_RGB_FMT(ARGB8888, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, - true, 4, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(ABGR8888, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 4, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(XBGR8888, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - false, 4, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(RGBA8888, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, - true, 4, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(BGRA8888, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, - true, 4, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(BGRX8888, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, - false, 4, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(XRGB8888, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, - false, 4, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(RGBX8888, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, - false, 4, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(RGB888, - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3, - false, 3, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(BGR888, - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3, - false, 3, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(RGB565, - 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3, - false, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(BGR565, - 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3, - false, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(ARGB1555, - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, - true, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(ABGR1555, - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(RGBA5551, - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, - true, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(BGRA5551, - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, - true, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(XRGB1555, - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, - false, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(XBGR1555, - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - false, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(RGBX5551, - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, - false, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(BGRX5551, - COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT, - C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, - false, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(ARGB4444, - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, - true, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(ABGR4444, - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(RGBA4444, - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, - true, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(BGRA4444, - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, - true, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(XRGB4444, - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, - false, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(XBGR4444, - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - false, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(RGBX4444, - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, - false, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(BGRX4444, - COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT, - C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, - false, 2, 0, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(BGRA1010102, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, - true, 4, DPU_FORMAT_FLAG_DX, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(RGBA1010102, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, - true, 4, DPU_FORMAT_FLAG_DX, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(ABGR2101010, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 4, DPU_FORMAT_FLAG_DX, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(ARGB2101010, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, - true, 4, DPU_FORMAT_FLAG_DX, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(XRGB2101010, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, - false, 4, DPU_FORMAT_FLAG_DX, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(BGRX1010102, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, - false, 4, DPU_FORMAT_FLAG_DX, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(XBGR2101010, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - false, 4, DPU_FORMAT_FLAG_DX, - DPU_FETCH_LINEAR, 1), - - INTERLEAVED_RGB_FMT(RGBX1010102, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, - false, 4, DPU_FORMAT_FLAG_DX, - DPU_FETCH_LINEAR, 1), - - PSEUDO_YUV_FMT(NV12, - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C1_B_Cb, C2_R_Cr, - DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV, - DPU_FETCH_LINEAR, 2), - - PSEUDO_YUV_FMT(NV21, - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C1_B_Cb, - DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV, - DPU_FETCH_LINEAR, 2), - - PSEUDO_YUV_FMT(NV16, - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C1_B_Cb, C2_R_Cr, - DPU_CHROMA_H2V1, DPU_FORMAT_FLAG_YUV, - DPU_FETCH_LINEAR, 2), - - PSEUDO_YUV_FMT(NV61, - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C1_B_Cb, - DPU_CHROMA_H2V1, DPU_FORMAT_FLAG_YUV, - DPU_FETCH_LINEAR, 2), - - PSEUDO_YUV_FMT_LOOSE(P010, - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C1_B_Cb, C2_R_Cr, - DPU_CHROMA_420, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_YUV, - DPU_FETCH_LINEAR, 2), - - INTERLEAVED_YUV_FMT(VYUY, - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y, - false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV, - DPU_FETCH_LINEAR, 2), - - INTERLEAVED_YUV_FMT(UYVY, - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y, - false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV, - DPU_FETCH_LINEAR, 2), - - INTERLEAVED_YUV_FMT(YUYV, - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr, - false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV, - DPU_FETCH_LINEAR, 2), - - INTERLEAVED_YUV_FMT(YVYU, - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb, - false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV, - DPU_FETCH_LINEAR, 2), - - PLANAR_YUV_FMT(YUV420, - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C1_B_Cb, C0_G_Y, - false, DPU_CHROMA_420, 1, DPU_FORMAT_FLAG_YUV, - DPU_FETCH_LINEAR, 3), - - PLANAR_YUV_FMT(YVU420, - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C1_B_Cb, C2_R_Cr, C0_G_Y, - false, DPU_CHROMA_420, 1, DPU_FORMAT_FLAG_YUV, - DPU_FETCH_LINEAR, 3), -}; - -/* - * UBWC formats table: - * This table holds the UBWC formats supported. - * If a compression ratio needs to be used for this or any other format, - * the data will be passed by user-space. - */ -static const struct dpu_format dpu_format_map_ubwc[] = { - INTERLEAVED_RGB_FMT_TILED(BGR565, - 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3, - false, 2, DPU_FORMAT_FLAG_COMPRESSED, - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), - - INTERLEAVED_RGB_FMT_TILED(ABGR8888, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 4, DPU_FORMAT_FLAG_COMPRESSED, - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), - - /* ARGB8888 and ABGR8888 purposely have the same color - * ordering. The hardware only supports ABGR8888 UBWC - * natively. - */ - INTERLEAVED_RGB_FMT_TILED(ARGB8888, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 4, DPU_FORMAT_FLAG_COMPRESSED, - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), - - INTERLEAVED_RGB_FMT_TILED(XBGR8888, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - false, 4, DPU_FORMAT_FLAG_COMPRESSED, - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), - - INTERLEAVED_RGB_FMT_TILED(XRGB8888, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - false, 4, DPU_FORMAT_FLAG_COMPRESSED, - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), - - INTERLEAVED_RGB_FMT_TILED(ABGR2101010, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED, - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), - - INTERLEAVED_RGB_FMT_TILED(XBGR2101010, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED, - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), - - INTERLEAVED_RGB_FMT_TILED(XRGB2101010, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED, - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), - - /* XRGB2101010 and ARGB2101010 purposely have the same color - * ordering. The hardware only supports ARGB2101010 UBWC - * natively. - */ - INTERLEAVED_RGB_FMT_TILED(ARGB2101010, - COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, - true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED, - DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), - - PSEUDO_YUV_FMT_TILED(NV12, - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C1_B_Cb, C2_R_Cr, - DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV | - DPU_FORMAT_FLAG_COMPRESSED, - DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12), - - PSEUDO_YUV_FMT_TILED(P010, - 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, - C1_B_Cb, C2_R_Cr, - DPU_CHROMA_420, DPU_FORMAT_FLAG_DX | - DPU_FORMAT_FLAG_YUV | - DPU_FORMAT_FLAG_COMPRESSED, - DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC), -}; - /* _dpu_get_v_h_subsample_rate - Get subsample rates for all formats we support * Note: Not using the drm_format_*_subsampling since we have formats */ static void _dpu_get_v_h_subsample_rate( - enum dpu_chroma_samp_type chroma_sample, + enum mdp_chroma_samp_type chroma_sample, uint32_t *v_sample, uint32_t *h_sample) { @@ -574,15 +38,15 @@ static void _dpu_get_v_h_subsample_rate( return; switch (chroma_sample) { - case DPU_CHROMA_H2V1: + case CHROMA_H2V1: *v_sample = 1; *h_sample = 2; break; - case DPU_CHROMA_H1V2: + case CHROMA_H1V2: *v_sample = 2; *h_sample = 1; break; - case DPU_CHROMA_420: + case CHROMA_420: *v_sample = 2; *h_sample = 2; break; @@ -593,7 +57,7 @@ static void _dpu_get_v_h_subsample_rate( } } -static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt) +static int _dpu_format_get_media_color_ubwc(const struct msm_format *fmt) { static const struct dpu_media_color_map dpu_media_ubwc_map[] = { {DRM_FORMAT_ABGR8888, COLOR_FMT_RGBA8888_UBWC}, @@ -609,10 +73,10 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt) int color_fmt = -1; int i; - if (fmt->base.pixel_format == DRM_FORMAT_NV12 || - fmt->base.pixel_format == DRM_FORMAT_P010) { - if (DPU_FORMAT_IS_DX(fmt)) { - if (fmt->unpack_tight) + if (fmt->pixel_format == DRM_FORMAT_NV12 || + fmt->pixel_format == DRM_FORMAT_P010) { + if (MSM_FORMAT_IS_DX(fmt)) { + if (fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT) color_fmt = COLOR_FMT_NV12_BPP10_UBWC; else color_fmt = COLOR_FMT_P010_UBWC; @@ -622,7 +86,7 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt) } for (i = 0; i < ARRAY_SIZE(dpu_media_ubwc_map); ++i) - if (fmt->base.pixel_format == dpu_media_ubwc_map[i].format) { + if (fmt->pixel_format == dpu_media_ubwc_map[i].format) { color_fmt = dpu_media_ubwc_map[i].color; break; } @@ -630,14 +94,14 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt) } static int _dpu_format_get_plane_sizes_ubwc( - const struct dpu_format *fmt, + const struct msm_format *fmt, const uint32_t width, const uint32_t height, struct dpu_hw_fmt_layout *layout) { int i; int color; - bool meta = DPU_FORMAT_IS_UBWC(fmt); + bool meta = MSM_FORMAT_IS_UBWC(fmt); memset(layout, 0, sizeof(struct dpu_hw_fmt_layout)); layout->format = fmt; @@ -647,12 +111,12 @@ static int _dpu_format_get_plane_sizes_ubwc( color = _dpu_format_get_media_color_ubwc(fmt); if (color < 0) { - DRM_ERROR("UBWC format not supported for fmt: %4.4s\n", - (char *)&fmt->base.pixel_format); + DRM_ERROR("UBWC format not supported for fmt: %p4cc\n", + &fmt->pixel_format); return -EINVAL; } - if (DPU_FORMAT_IS_YUV(layout->format)) { + if (MSM_FORMAT_IS_YUV(layout->format)) { uint32_t y_sclines, uv_sclines; uint32_t y_meta_scanlines = 0; uint32_t uv_meta_scanlines = 0; @@ -709,7 +173,7 @@ done: } static int _dpu_format_get_plane_sizes_linear( - const struct dpu_format *fmt, + const struct msm_format *fmt, const uint32_t width, const uint32_t height, struct dpu_hw_fmt_layout *layout, @@ -724,7 +188,7 @@ static int _dpu_format_get_plane_sizes_linear( layout->num_planes = fmt->num_planes; /* Due to memset above, only need to set planes of interest */ - if (fmt->fetch_planes == DPU_PLANE_INTERLEAVED) { + if (fmt->fetch_type == MDP_PLANE_INTERLEAVED) { layout->num_planes = 1; layout->plane_size[0] = width * height * layout->format->bpp; layout->plane_pitch[0] = width * layout->format->bpp; @@ -742,8 +206,8 @@ static int _dpu_format_get_plane_sizes_linear( return -EINVAL; } - if ((fmt->base.pixel_format == DRM_FORMAT_NV12) && - (DPU_FORMAT_IS_DX(fmt))) + if ((fmt->pixel_format == DRM_FORMAT_NV12) && + (MSM_FORMAT_IS_DX(fmt))) bpp = 2; layout->plane_pitch[0] = width * bpp; layout->plane_pitch[1] = layout->plane_pitch[0] / h_subsample; @@ -751,7 +215,7 @@ static int _dpu_format_get_plane_sizes_linear( layout->plane_size[1] = layout->plane_pitch[1] * (height / v_subsample); - if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) { + if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) { layout->num_planes = 2; layout->plane_size[1] *= 2; layout->plane_pitch[1] *= 2; @@ -781,7 +245,7 @@ static int _dpu_format_get_plane_sizes_linear( } static int dpu_format_get_plane_sizes( - const struct dpu_format *fmt, + const struct msm_format *fmt, const uint32_t w, const uint32_t h, struct dpu_hw_fmt_layout *layout, @@ -797,7 +261,7 @@ static int dpu_format_get_plane_sizes( return -ERANGE; } - if (DPU_FORMAT_IS_UBWC(fmt) || DPU_FORMAT_IS_TILE(fmt)) + if (MSM_FORMAT_IS_UBWC(fmt) || MSM_FORMAT_IS_TILE(fmt)) return _dpu_format_get_plane_sizes_ubwc(fmt, w, h, layout); return _dpu_format_get_plane_sizes_linear(fmt, w, h, layout, pitches); @@ -823,10 +287,10 @@ static int _dpu_format_populate_addrs_ubwc( return -EFAULT; } - meta = DPU_FORMAT_IS_UBWC(layout->format); + meta = MSM_FORMAT_IS_UBWC(layout->format); /* Per-format logic for verifying active planes */ - if (DPU_FORMAT_IS_YUV(layout->format)) { + if (MSM_FORMAT_IS_YUV(layout->format)) { /************************************************/ /* UBWC ** */ /* buffer ** DPU PLANE */ @@ -942,7 +406,7 @@ int dpu_format_populate_layout( return -ERANGE; } - layout->format = to_dpu_format(msm_framebuffer_format(fb)); + layout->format = msm_framebuffer_format(fb); /* Populate the plane sizes etc via get_format */ ret = dpu_format_get_plane_sizes(layout->format, fb->width, fb->height, @@ -951,8 +415,8 @@ int dpu_format_populate_layout( return ret; /* Populate the addresses given the fb */ - if (DPU_FORMAT_IS_UBWC(layout->format) || - DPU_FORMAT_IS_TILE(layout->format)) + if (MSM_FORMAT_IS_UBWC(layout->format) || + MSM_FORMAT_IS_TILE(layout->format)) ret = _dpu_format_populate_addrs_ubwc(aspace, fb, layout); else ret = _dpu_format_populate_addrs_linear(aspace, fb, layout); @@ -962,23 +426,21 @@ int dpu_format_populate_layout( int dpu_format_check_modified_format( const struct msm_kms *kms, - const struct msm_format *msm_fmt, + const struct msm_format *fmt, const struct drm_mode_fb_cmd2 *cmd, struct drm_gem_object **bos) { const struct drm_format_info *info; - const struct dpu_format *fmt; struct dpu_hw_fmt_layout layout; uint32_t bos_total_size = 0; int ret, i; - if (!msm_fmt || !cmd || !bos) { + if (!fmt || !cmd || !bos) { DRM_ERROR("invalid arguments\n"); return -EINVAL; } - fmt = to_dpu_format(msm_fmt); - info = drm_format_info(fmt->base.pixel_format); + info = drm_format_info(fmt->pixel_format); if (!info) return -EINVAL; @@ -1004,65 +466,3 @@ int dpu_format_check_modified_format( return 0; } - -const struct dpu_format *dpu_get_dpu_format_ext( - const uint32_t format, - const uint64_t modifier) -{ - uint32_t i = 0; - const struct dpu_format *fmt = NULL; - const struct dpu_format *map = NULL; - ssize_t map_size = 0; - - /* - * Currently only support exactly zero or one modifier. - * All planes use the same modifier. - */ - DRM_DEBUG_ATOMIC("plane format modifier 0x%llX\n", modifier); - - switch (modifier) { - case 0: - map = dpu_format_map; - map_size = ARRAY_SIZE(dpu_format_map); - break; - case DRM_FORMAT_MOD_QCOM_COMPRESSED: - map = dpu_format_map_ubwc; - map_size = ARRAY_SIZE(dpu_format_map_ubwc); - DRM_DEBUG_ATOMIC("found fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED\n", - (char *)&format); - break; - default: - DPU_ERROR("unsupported format modifier %llX\n", modifier); - return NULL; - } - - for (i = 0; i < map_size; i++) { - if (format == map[i].base.pixel_format) { - fmt = &map[i]; - break; - } - } - - if (fmt == NULL) - DPU_ERROR("unsupported fmt: %4.4s modifier 0x%llX\n", - (char *)&format, modifier); - else - DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %d\n", - (char *)&format, modifier, - DPU_FORMAT_IS_UBWC(fmt), - DPU_FORMAT_IS_YUV(fmt)); - - return fmt; -} - -const struct msm_format *dpu_get_msm_format( - struct msm_kms *kms, - const uint32_t format, - const uint64_t modifiers) -{ - const struct dpu_format *fmt = dpu_get_dpu_format_ext(format, - modifiers); - if (fmt) - return &fmt->base; - return NULL; -} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h index 84b8b3289f18..210d0ed5f0af 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h @@ -10,17 +10,6 @@ #include "dpu_hw_mdss.h" /** - * dpu_get_dpu_format_ext() - Returns dpu format structure pointer. - * @format: DRM FourCC Code - * @modifiers: format modifier array from client, one per plane - */ -const struct dpu_format *dpu_get_dpu_format_ext( - const uint32_t format, - const uint64_t modifier); - -#define dpu_get_dpu_format(f) dpu_get_dpu_format_ext(f, 0) - -/** * dpu_find_format - validate if the pixel format is supported * @format: dpu format * @supported_formats: supported formats by dpu HW @@ -43,22 +32,10 @@ static inline bool dpu_find_format(u32 format, const u32 *supported_formats, } /** - * dpu_get_msm_format - get an dpu_format by its msm_format base - * callback function registers with the msm_kms layer - * @kms: kms driver - * @format: DRM FourCC Code - * @modifiers: data layout modifier - */ -const struct msm_format *dpu_get_msm_format( - struct msm_kms *kms, - const uint32_t format, - const uint64_t modifiers); - -/** * dpu_format_check_modified_format - validate format and buffers for * dpu non-standard, i.e. modified format * @kms: kms driver - * @msm_fmt: pointer to the msm_fmt base pointer of an dpu_format + * @msm_fmt: pointer to the msm_fmt base pointer of an msm_format * @cmd: fb_cmd2 structure user request * @bos: gem buffer object list * diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c index 9016b3ade6bc..55d2768a6d4d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c @@ -170,7 +170,7 @@ static int dpu_hw_cdm_setup_cdwn(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg * static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cdm) { struct dpu_hw_blk_reg_map *c = &ctx->hw; - const struct dpu_format *fmt; + const struct msm_format *fmt; u32 opmode = 0; u32 csc = 0; @@ -179,14 +179,14 @@ static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cdm) fmt = cdm->output_fmt; - if (!DPU_FORMAT_IS_YUV(fmt)) + if (!MSM_FORMAT_IS_YUV(fmt)) return -EINVAL; dpu_hw_csc_setup(&ctx->hw, CDM_CSC_10_MATRIX_COEFF_0, cdm->csc_cfg, true); dpu_hw_cdm_setup_cdwn(ctx, cdm); if (cdm->output_type == CDM_CDWN_OUTPUT_HDMI) { - if (fmt->chroma_sample == DPU_CHROMA_H1V2) + if (fmt->chroma_sample == CHROMA_H1V2) return -EINVAL; /*unsupported format */ opmode = CDM_HDMI_PACK_OP_MODE_EN; opmode |= (fmt->chroma_sample << 1); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h index 348424df87c6..ec71c9886d75 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h @@ -19,7 +19,7 @@ struct dpu_hw_cdm; * @output_bit_depth: output bit-depth of CDM block * @h_cdwn_type: downsample type used for horizontal pixels * @v_cdwn_type: downsample type used for vertical pixels - * @output_fmt: handle to dpu_format of CDM block + * @output_fmt: handle to msm_format of CDM block * @csc_cfg: handle to CSC matrix programmed for CDM block * @output_type: interface to which CDM is paired (HDMI/WB) * @pp_id: ping-pong block to which CDM is bound to @@ -30,7 +30,7 @@ struct dpu_hw_cdm_cfg { u32 output_bit_depth; u32 h_cdwn_type; u32 v_cdwn_type; - const struct dpu_format *output_fmt; + const struct msm_format *output_fmt; const struct dpu_csc_cfg *csc_cfg; u32 output_type; int pp_id; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index a06f69d0b257..2e50049f2f85 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -545,6 +545,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, { struct dpu_hw_blk_reg_map *c = &ctx->hw; u32 intf_active = 0; + u32 dsc_active = 0; u32 wb_active = 0; u32 mode_sel = 0; @@ -560,6 +561,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE); wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE); + dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE); if (cfg->intf) intf_active |= BIT(cfg->intf - INTF_0); @@ -567,17 +569,18 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, if (cfg->wb) wb_active |= BIT(cfg->wb - WB_0); + if (cfg->dsc) + dsc_active |= cfg->dsc; + DPU_REG_WRITE(c, CTL_TOP, mode_sel); DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active); DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active); + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active); if (cfg->merge_3d) DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, BIT(cfg->merge_3d - MERGE_3D_0)); - if (cfg->dsc) - DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc); - if (cfg->cdm) DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 6a0a74832fb6..b85881aab047 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -223,9 +223,11 @@ static void dpu_core_irq_callback_handler(struct dpu_kms *dpu_kms, unsigned int VERB("IRQ=[%d, %d]\n", DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx)); - if (!irq_entry->cb) + if (!irq_entry->cb) { DRM_ERROR("no registered cb, IRQ=[%d, %d]\n", DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx)); + return; + } atomic_inc(&irq_entry->count); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 965692ef7892..225c1c7768ff 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -96,11 +96,11 @@ #define INTF_CFG2_DCE_DATA_COMPRESS BIT(12) -static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, +static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, const struct dpu_hw_intf_timing_params *p, - const struct dpu_format *fmt) + const struct msm_format *fmt) { - struct dpu_hw_blk_reg_map *c = &ctx->hw; + struct dpu_hw_blk_reg_map *c = &intf->hw; u32 hsync_period, vsync_period; u32 display_v_start, display_v_end; u32 hsync_start_x, hsync_end_x; @@ -118,7 +118,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, /* read interface_cfg */ intf_cfg = DPU_REG_READ(c, INTF_CONFIG); - if (ctx->cap->type == INTF_DP) + if (intf->cap->type == INTF_DP) dp_intf = true; hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width + @@ -194,16 +194,16 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, (p->vsync_polarity << 1) | /* VSYNC Polarity */ (p->hsync_polarity << 0); /* HSYNC Polarity */ - if (!DPU_FORMAT_IS_YUV(fmt)) - panel_format = (fmt->bits[C0_G_Y] | - (fmt->bits[C1_B_Cb] << 2) | - (fmt->bits[C2_R_Cr] << 4) | + if (!MSM_FORMAT_IS_YUV(fmt)) + panel_format = (fmt->bpc_g_y | + (fmt->bpc_b_cb << 2) | + (fmt->bpc_r_cr << 4) | (0x21 << 8)); else /* Interface treats all the pixel data in RGB888 format */ - panel_format = (COLOR_8BIT | - (COLOR_8BIT << 2) | - (COLOR_8BIT << 4) | + panel_format = (BPC8 | + (BPC8 << 2) | + (BPC8 << 4) | (0x21 << 8)); DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl); @@ -223,7 +223,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3); DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); - if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) { + if (intf->cap->features & BIT(DPU_DATA_HCTL_EN)) { /* * DATA_HCTL_EN controls data timing which can be different from * video timing. It is recommended to enable it for all cases, except @@ -518,10 +518,10 @@ static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf, } -static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx, +static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *intf, struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg) { - u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2); + u32 intf_cfg2 = DPU_REG_READ(&intf->hw, INTF_CONFIG2); if (cmd_mode_cfg->data_compress) intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; @@ -529,7 +529,7 @@ static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx, if (cmd_mode_cfg->wide_bus_en) intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN; - DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2); + DPU_REG_WRITE(&intf->hw, INTF_CONFIG2, intf_cfg2); } struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index 6f4c87244f94..f9015c67a574 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -81,7 +81,7 @@ struct dpu_hw_intf_cmd_mode_cfg { struct dpu_hw_intf_ops { void (*setup_timing_gen)(struct dpu_hw_intf *intf, const struct dpu_hw_intf_timing_params *p, - const struct dpu_format *fmt); + const struct msm_format *fmt); void (*setup_prg_fetch)(struct dpu_hw_intf *intf, const struct dpu_hw_intf_prog_fetch *fetch); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index 5df545904057..66759623fc42 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -10,6 +10,8 @@ #include "msm_drv.h" +#include "disp/mdp_format.h" + #define DPU_DBG_NAME "dpu" #define DPU_NONE 0 @@ -35,28 +37,6 @@ #define DPU_MAX_DE_CURVES 3 #endif -enum dpu_format_flags { - DPU_FORMAT_FLAG_YUV_BIT, - DPU_FORMAT_FLAG_DX_BIT, - DPU_FORMAT_FLAG_COMPRESSED_BIT, - DPU_FORMAT_FLAG_BIT_MAX, -}; - -#define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT) -#define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT) -#define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT) -#define DPU_FORMAT_IS_YUV(X) \ - (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag)) -#define DPU_FORMAT_IS_DX(X) \ - (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag)) -#define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR) -#define DPU_FORMAT_IS_TILE(X) \ - (((X)->fetch_mode == DPU_FETCH_UBWC) && \ - !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) -#define DPU_FORMAT_IS_UBWC(X) \ - (((X)->fetch_mode == DPU_FETCH_UBWC) && \ - test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag)) - #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0) #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0) #define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0) @@ -291,67 +271,6 @@ enum dpu_vbif { }; /** - * DPU HW,Component order color map - */ -enum { - C0_G_Y = 0, - C1_B_Cb = 1, - C2_R_Cr = 2, - C3_ALPHA = 3 -}; - -/** - * enum dpu_plane_type - defines how the color component pixel packing - * @DPU_PLANE_INTERLEAVED : Color components in single plane - * @DPU_PLANE_PLANAR : Color component in separate planes - * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane - */ -enum dpu_plane_type { - DPU_PLANE_INTERLEAVED, - DPU_PLANE_PLANAR, - DPU_PLANE_PSEUDO_PLANAR, -}; - -/** - * enum dpu_chroma_samp_type - chroma sub-samplng type - * @DPU_CHROMA_RGB : No chroma subsampling - * @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled - * @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled - * @DPU_CHROMA_420 : 420 subsampling - */ -enum dpu_chroma_samp_type { - DPU_CHROMA_RGB, - DPU_CHROMA_H2V1, - DPU_CHROMA_H1V2, - DPU_CHROMA_420 -}; - -/** - * dpu_fetch_type - Defines How DPU HW fetches data - * @DPU_FETCH_LINEAR : fetch is line by line - * @DPU_FETCH_TILE : fetches data in Z order from a tile - * @DPU_FETCH_UBWC : fetch and decompress data - */ -enum dpu_fetch_type { - DPU_FETCH_LINEAR, - DPU_FETCH_TILE, - DPU_FETCH_UBWC -}; - -/** - * Value of enum chosen to fit the number of bits - * expected by the HW programming. - */ -enum { - COLOR_ALPHA_1BIT = 0, - COLOR_ALPHA_4BIT = 1, - COLOR_4BIT = 0, - COLOR_5BIT = 1, /* No 5-bit Alpha */ - COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */ - COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */ -}; - -/** * enum dpu_3d_blend_mode * Desribes how the 3d data is blended * @BLEND_3D_NONE : 3d blending not enabled @@ -370,43 +289,6 @@ enum dpu_3d_blend_mode { BLEND_3D_MAX }; -/** struct dpu_format - defines the format configuration which - * allows DPU HW to correctly fetch and decode the format - * @base: base msm_format structure containing fourcc code - * @fetch_planes: how the color components are packed in pixel format - * @element: element color ordering - * @bits: element bit widths - * @chroma_sample: chroma sub-samplng type - * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB - * @unpack_tight: 0 for loose, 1 for tight - * @unpack_count: 0 = 1 component, 1 = 2 component - * @bpp: bytes per pixel - * @alpha_enable: whether the format has an alpha channel - * @num_planes: number of planes (including meta data planes) - * @fetch_mode: linear, tiled, or ubwc hw fetch behavior - * @flag: usage bit flags - * @tile_width: format tile width - * @tile_height: format tile height - */ -struct dpu_format { - struct msm_format base; - enum dpu_plane_type fetch_planes; - u8 element[DPU_MAX_PLANES]; - u8 bits[DPU_MAX_PLANES]; - enum dpu_chroma_samp_type chroma_sample; - u8 unpack_align_msb; - u8 unpack_tight; - u8 unpack_count; - u8 bpp; - u8 alpha_enable; - u8 num_planes; - enum dpu_fetch_type fetch_mode; - DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX); - u16 tile_width; - u16 tile_height; -}; -#define to_dpu_format(x) container_of(x, struct dpu_format, base) - /** * struct dpu_hw_fmt_layout - format information of the source pixel data * @format: pixel format parameters @@ -419,7 +301,7 @@ struct dpu_format { * @plane_pitch: pitch of each plane */ struct dpu_hw_fmt_layout { - const struct dpu_format *format; + const struct msm_format *format; uint32_t num_planes; uint32_t width; uint32_t height; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 0bf8a83e8df3..2c720f1fc1b2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -2,6 +2,8 @@ /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. */ +#include <linux/debugfs.h> + #include "dpu_hwio.h" #include "dpu_hw_catalog.h" #include "dpu_hw_lm.h" @@ -206,7 +208,7 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, * Setup source pixel format, flip, */ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, - const struct dpu_format *fmt, u32 flags) + const struct msm_format *fmt, u32 flags) { struct dpu_hw_sspp *ctx = pipe->sspp; struct dpu_hw_blk_reg_map *c; @@ -241,20 +243,20 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, chroma_samp = fmt->chroma_sample; if (flags & DPU_SSPP_SOURCE_ROTATED_90) { - if (chroma_samp == DPU_CHROMA_H2V1) - chroma_samp = DPU_CHROMA_H1V2; - else if (chroma_samp == DPU_CHROMA_H1V2) - chroma_samp = DPU_CHROMA_H2V1; + if (chroma_samp == CHROMA_H2V1) + chroma_samp = CHROMA_H1V2; + else if (chroma_samp == CHROMA_H1V2) + chroma_samp = CHROMA_H2V1; } - src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) | - (fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) | - (fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0); + src_format = (chroma_samp << 23) | (fmt->fetch_type << 19) | + (fmt->bpc_a << 6) | (fmt->bpc_r_cr << 4) | + (fmt->bpc_b_cb << 2) | (fmt->bpc_g_y << 0); if (flags & DPU_SSPP_ROT_90) src_format |= BIT(11); /* ROT90 */ - if (fmt->alpha_enable && fmt->fetch_planes == DPU_PLANE_INTERLEAVED) + if (fmt->alpha_enable && fmt->fetch_type == MDP_PLANE_INTERLEAVED) src_format |= BIT(8); /* SRCC3_EN */ if (flags & DPU_SSPP_SOLID_FILL) @@ -263,12 +265,12 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) | (fmt->element[1] << 8) | (fmt->element[0] << 0); src_format |= ((fmt->unpack_count - 1) << 12) | - (fmt->unpack_tight << 17) | - (fmt->unpack_align_msb << 18) | + ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) | + ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB ? 1 : 0) << 18) | ((fmt->bpp - 1) << 9); - if (fmt->fetch_mode != DPU_FETCH_LINEAR) { - if (DPU_FORMAT_IS_UBWC(fmt)) + if (fmt->fetch_mode != MDP_FETCH_LINEAR) { + if (MSM_FORMAT_IS_UBWC(fmt)) opmode |= MDSS_MDP_OP_BWC_EN; src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */ DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, @@ -295,7 +297,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, break; case UBWC_4_0: DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, - DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); + MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); break; } } @@ -303,20 +305,20 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, opmode |= MDSS_MDP_OP_PE_OVERRIDE; /* if this is YUV pixel format, enable CSC */ - if (DPU_FORMAT_IS_YUV(fmt)) + if (MSM_FORMAT_IS_YUV(fmt)) src_format |= BIT(15); - if (DPU_FORMAT_IS_DX(fmt)) + if (MSM_FORMAT_IS_DX(fmt)) src_format |= BIT(14); /* update scaler opmode, if appropriate */ if (test_bit(DPU_SSPP_CSC, &ctx->cap->features)) _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, - DPU_FORMAT_IS_YUV(fmt)); + MSM_FORMAT_IS_YUV(fmt)); else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) _sspp_setup_csc10_opmode(ctx, VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, - DPU_FORMAT_IS_YUV(fmt)); + MSM_FORMAT_IS_YUV(fmt)); DPU_REG_WRITE(c, format_off, src_format); DPU_REG_WRITE(c, unpack_pat_off, unpack); @@ -385,7 +387,7 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, struct dpu_hw_scaler3_cfg *scaler3_cfg, - const struct dpu_format *format) + const struct msm_format *format) { if (!ctx || !scaler3_cfg) return; @@ -556,7 +558,7 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx, } static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe, - const struct dpu_format *fmt, + const struct msm_format *fmt, bool enable) { struct dpu_hw_sspp *ctx = pipe->sspp; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index b7dc52312c39..4a910b808687 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -183,7 +183,7 @@ struct dpu_hw_sspp_ops { * @flags: Extra flags for format config */ void (*setup_format)(struct dpu_sw_pipe *pipe, - const struct dpu_format *fmt, u32 flags); + const struct msm_format *fmt, u32 flags); /** * setup_rects - setup pipe ROI rectangles @@ -279,7 +279,7 @@ struct dpu_hw_sspp_ops { */ void (*setup_scaler)(struct dpu_hw_sspp *ctx, struct dpu_hw_scaler3_cfg *scaler3_cfg, - const struct dpu_format *format); + const struct msm_format *format); /** * setup_cdp - setup client driven prefetch @@ -288,7 +288,7 @@ struct dpu_hw_sspp_ops { * @enable: whether the CDP should be enabled for this pipe */ void (*setup_cdp)(struct dpu_sw_pipe *pipe, - const struct dpu_format *fmt, + const struct msm_format *fmt, bool enable); }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c index dd475827314e..486be346d40d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c @@ -282,7 +282,7 @@ static void _dpu_hw_setup_scaler3_de(struct dpu_hw_blk_reg_map *c, void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c, struct dpu_hw_scaler3_cfg *scaler3_cfg, u32 scaler_offset, u32 scaler_version, - const struct dpu_format *format) + const struct msm_format *format) { u32 op_mode = 0; u32 phase_init, preload, src_y_rgb, src_uv, dst; @@ -293,7 +293,7 @@ void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c, op_mode |= BIT(0); op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16; - if (format && DPU_FORMAT_IS_YUV(format)) { + if (format && MSM_FORMAT_IS_YUV(format)) { op_mode |= BIT(12); op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24; } @@ -367,7 +367,7 @@ void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c, DPU_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst); end: - if (format && !DPU_FORMAT_IS_DX(format)) + if (format && !MSM_FORMAT_IS_DX(format)) op_mode |= BIT(14); if (format && format->alpha_enable) { @@ -522,16 +522,16 @@ int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c, #define CDP_PRELOAD_AHEAD_64 BIT(3) void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset, - const struct dpu_format *fmt, bool enable) + const struct msm_format *fmt, bool enable) { u32 cdp_cntl = CDP_PRELOAD_AHEAD_64; if (enable) cdp_cntl |= CDP_ENABLE; - if (DPU_FORMAT_IS_UBWC(fmt)) + if (MSM_FORMAT_IS_UBWC(fmt)) cdp_cntl |= CDP_UBWC_META_ENABLE; - if (DPU_FORMAT_IS_UBWC(fmt) || - DPU_FORMAT_IS_TILE(fmt)) + if (MSM_FORMAT_IS_UBWC(fmt) || + MSM_FORMAT_IS_TILE(fmt)) cdp_cntl |= CDP_TILE_AMORTIZE_ENABLE; DPU_REG_WRITE(c, offset, cdp_cntl); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h index 64ded69fa903..67b08e99335d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h @@ -344,14 +344,14 @@ void *dpu_hw_util_get_dir(void); void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c, struct dpu_hw_scaler3_cfg *scaler3_cfg, u32 scaler_offset, u32 scaler_version, - const struct dpu_format *format); + const struct msm_format *format); void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, u32 csc_reg_off, const struct dpu_csc_cfg *data, bool csc10); void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset, - const struct dpu_format *fmt, bool enable); + const struct msm_format *fmt, bool enable); u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, u32 total_fl); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c index e75995f7fcea..93ff01c889b5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c @@ -67,7 +67,7 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx, struct dpu_hw_wb_cfg *data) { struct dpu_hw_blk_reg_map *c = &ctx->hw; - const struct dpu_format *fmt = data->dest.format; + const struct msm_format *fmt = data->dest.format; u32 dst_format, pattern, ystride0, ystride1, outsize, chroma_samp; u32 write_config = 0; u32 opmode = 0; @@ -76,20 +76,20 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx, chroma_samp = fmt->chroma_sample; dst_format = (chroma_samp << 23) | - (fmt->fetch_planes << 19) | - (fmt->bits[C3_ALPHA] << 6) | - (fmt->bits[C2_R_Cr] << 4) | - (fmt->bits[C1_B_Cb] << 2) | - (fmt->bits[C0_G_Y] << 0); + (fmt->fetch_type << 19) | + (fmt->bpc_a << 6) | + (fmt->bpc_r_cr << 4) | + (fmt->bpc_b_cb << 2) | + (fmt->bpc_g_y << 0); - if (fmt->bits[C3_ALPHA] || fmt->alpha_enable) { + if (fmt->bpc_a || fmt->alpha_enable) { dst_format |= BIT(8); /* DSTC3_EN */ if (!fmt->alpha_enable || !(ctx->caps->features & BIT(DPU_WB_PIPE_ALPHA))) dst_format |= BIT(14); /* DST_ALPHA_X */ } - if (DPU_FORMAT_IS_YUV(fmt)) + if (MSM_FORMAT_IS_YUV(fmt)) dst_format |= BIT(15); pattern = (fmt->element[3] << 24) | @@ -97,8 +97,8 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx, (fmt->element[1] << 8) | (fmt->element[0] << 0); - dst_format |= (fmt->unpack_align_msb << 18) | - (fmt->unpack_tight << 17) | + dst_format |= ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB ? 1 : 0) << 18) | + ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) | ((fmt->unpack_count - 1) << 12) | ((fmt->bpp - 1) << 9); @@ -149,7 +149,7 @@ static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx, } static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx, - const struct dpu_format *fmt, + const struct msm_format *fmt, bool enable) { if (!ctx) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h index e671796ea379..37497473e16c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h @@ -46,7 +46,7 @@ struct dpu_hw_wb_ops { struct dpu_hw_qos_cfg *cfg); void (*setup_cdp)(struct dpu_hw_wb *ctx, - const struct dpu_format *fmt, + const struct msm_format *fmt, bool enable); bool (*setup_clk_force_ctrl)(struct dpu_hw_wb *ctx, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index a1f5d7c4ab91..1955848b1b78 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -348,9 +348,18 @@ static void dpu_kms_global_destroy_state(struct drm_private_obj *obj, kfree(dpu_state); } +static void dpu_kms_global_print_state(struct drm_printer *p, + const struct drm_private_state *state) +{ + const struct dpu_global_state *global_state = to_dpu_global_state(state); + + dpu_rm_print_state(p, global_state); +} + static const struct drm_private_state_funcs dpu_kms_global_state_funcs = { .atomic_duplicate_state = dpu_kms_global_duplicate_state, .atomic_destroy_state = dpu_kms_global_destroy_state, + .atomic_print_state = dpu_kms_global_print_state, }; static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms) @@ -364,6 +373,9 @@ static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms) drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state, &state->base, &dpu_kms_global_state_funcs); + + state->rm = &dpu_kms->rm; + return 0; } @@ -970,7 +982,6 @@ static const struct msm_kms_funcs kms_funcs = { .enable_vblank = dpu_kms_enable_vblank, .disable_vblank = dpu_kms_disable_vblank, .check_modified_format = dpu_format_check_modified_format, - .get_format = dpu_get_msm_format, .destroy = dpu_kms_destroy, .snapshot = dpu_kms_mdp_snapshot, #ifdef CONFIG_DEBUG_FS diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index b5db3fc76ca6..e2adc937ea63 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -130,6 +130,8 @@ struct vsync_info { struct dpu_global_state { struct drm_private_state base; + struct dpu_rm *rm; + uint32_t pingpong_to_enc_id[PINGPONG_MAX - PINGPONG_0]; uint32_t mixer_to_enc_id[LM_MAX - LM_0]; uint32_t ctl_to_enc_id[CTL_MAX - CTL_0]; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index ff975ad51145..1c3a2657450c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -113,7 +113,7 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) * Prefill BW Equation: line src bytes * line_time */ static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog, - const struct dpu_format *fmt, + const struct msm_format *fmt, const struct drm_display_mode *mode, struct dpu_sw_pipe_cfg *pipe_cfg) { @@ -195,7 +195,7 @@ static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode, static int _dpu_plane_calc_fill_level(struct drm_plane *plane, struct dpu_sw_pipe *pipe, enum dpu_qos_lut_usage lut_usage, - const struct dpu_format *fmt, u32 src_width) + const struct msm_format *fmt, u32 src_width) { struct dpu_plane *pdpu; u32 fixed_buff_size; @@ -214,8 +214,8 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, /* FIXME: in multirect case account for the src_width of all the planes */ - if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) { - if (fmt->chroma_sample == DPU_CHROMA_420) { + if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) { + if (fmt->chroma_sample == CHROMA_420) { /* NV12 */ total_fl = (fixed_buff_size / 2) / ((src_width + 32) * fmt->bpp); @@ -234,9 +234,9 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, } } - DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n", + DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc w:%u fl:%u\n", pipe->sspp->idx - SSPP_VIG0, - (char *)&fmt->base.pixel_format, + &fmt->pixel_format, src_width, total_fl); return total_fl; @@ -251,7 +251,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, */ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, struct dpu_sw_pipe *pipe, - const struct dpu_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg) + const struct msm_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_hw_qos_cfg cfg; @@ -260,7 +260,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, if (!pdpu->is_rt_pipe) { lut_usage = DPU_QOS_LUT_USAGE_NRT; } else { - if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) + if (fmt && MSM_FORMAT_IS_LINEAR(fmt)) lut_usage = DPU_QOS_LUT_USAGE_LINEAR; else lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; @@ -284,26 +284,26 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, pdpu->is_rt_pipe); trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0, - (fmt) ? fmt->base.pixel_format : 0, + (fmt) ? fmt->pixel_format : 0, pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage); - DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", + DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc rt:%d fl:%u lut:0x%llx\n", pdpu->pipe - SSPP_VIG0, - fmt ? (char *)&fmt->base.pixel_format : NULL, + fmt ? &fmt->pixel_format : NULL, pdpu->is_rt_pipe, total_fl, cfg.creq_lut); trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, - (fmt) ? fmt->base.pixel_format : 0, + (fmt) ? fmt->pixel_format : 0, (fmt) ? fmt->fetch_mode : 0, cfg.danger_lut, cfg.safe_lut); - DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", - pdpu->pipe - SSPP_VIG0, - fmt ? (char *)&fmt->base.pixel_format : NULL, - fmt ? fmt->fetch_mode : -1, - cfg.danger_lut, - cfg.safe_lut); + DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc mode:%d luts[0x%x, 0x%x]\n", + pdpu->pipe - SSPP_VIG0, + fmt ? &fmt->pixel_format : NULL, + fmt ? fmt->fetch_mode : -1, + cfg.danger_lut, + cfg.safe_lut); pipe->sspp->ops.setup_qos_lut(pipe->sspp, &cfg); } @@ -425,7 +425,7 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane, static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw, uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h, struct dpu_hw_scaler3_cfg *scale_cfg, - const struct dpu_format *fmt, + const struct msm_format *fmt, uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v, unsigned int rotation) { @@ -477,7 +477,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw, scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V; } } - if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) + if (!(MSM_FORMAT_IS_YUV(fmt)) && (src_h == dst_h) && (src_w == dst_w)) return; @@ -510,11 +510,11 @@ static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg, } static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, - const struct dpu_format *fmt) + const struct msm_format *fmt) { const struct dpu_csc_cfg *csc_ptr; - if (!DPU_FORMAT_IS_YUV(fmt)) + if (!MSM_FORMAT_IS_YUV(fmt)) return NULL; if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features) @@ -526,12 +526,12 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, } static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, - const struct dpu_format *fmt, bool color_fill, + const struct msm_format *fmt, bool color_fill, struct dpu_sw_pipe_cfg *pipe_cfg, unsigned int rotation) { struct dpu_hw_sspp *pipe_hw = pipe->sspp; - const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); + const struct drm_format_info *info = drm_format_info(fmt->pixel_format); struct dpu_hw_scaler3_cfg scaler3_cfg; struct dpu_hw_pixel_ext pixel_ext; u32 src_width = drm_rect_width(&pipe_cfg->src_rect); @@ -577,7 +577,7 @@ static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate, struct dpu_sw_pipe *pipe, struct drm_rect *dst_rect, u32 fill_color, - const struct dpu_format *fmt) + const struct msm_format *fmt) { struct dpu_sw_pipe_cfg pipe_cfg; @@ -615,8 +615,9 @@ static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate, static void _dpu_plane_color_fill(struct dpu_plane *pdpu, uint32_t color, uint32_t alpha) { - const struct dpu_format *fmt; + const struct msm_format *fmt; const struct drm_plane *plane = &pdpu->base; + struct msm_drm_private *priv = plane->dev->dev_private; struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state); u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); @@ -626,7 +627,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu, * select fill format to match user property expectation, * h/w only supports RGB variants */ - fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888); + fmt = mdp_get_format(priv->kms, DRM_FORMAT_ABGR8888, 0); /* should not happen ever */ if (!fmt) return; @@ -704,7 +705,7 @@ static void dpu_plane_cleanup_fb(struct drm_plane *plane, static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, const struct dpu_sspp_sub_blks *sblk, - struct drm_rect src, const struct dpu_format *fmt) + struct drm_rect src, const struct msm_format *fmt) { size_t num_formats; const u32 *supported_formats; @@ -723,8 +724,8 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, supported_formats = sblk->rotation_cfg->rot_format_list; num_formats = sblk->rotation_cfg->rot_num_formats; - if (!DPU_FORMAT_IS_UBWC(fmt) || - !dpu_find_format(fmt->base.pixel_format, supported_formats, num_formats)) + if (!MSM_FORMAT_IS_UBWC(fmt) || + !dpu_find_format(fmt->pixel_format, supported_formats, num_formats)) return -EINVAL; return 0; @@ -733,15 +734,15 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *pipe_cfg, - const struct dpu_format *fmt, + const struct msm_format *fmt, const struct drm_display_mode *mode) { uint32_t min_src_size; struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); - min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; + min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1; - if (DPU_FORMAT_IS_YUV(fmt) && + if (MSM_FORMAT_IS_YUV(fmt) && (!pipe->sspp->cap->sblk->scaler_blk.len || !pipe->sspp->cap->sblk->csc_blk.len)) { DPU_DEBUG_PLANE(pdpu, @@ -758,7 +759,7 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, } /* valid yuv image */ - if (DPU_FORMAT_IS_YUV(fmt) && + if (MSM_FORMAT_IS_YUV(fmt) && (pipe_cfg->src_rect.x1 & 0x1 || pipe_cfg->src_rect.y1 & 0x1 || drm_rect_width(&pipe_cfg->src_rect) & 0x1 || @@ -798,7 +799,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, struct dpu_sw_pipe *pipe = &pstate->pipe; struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; const struct drm_crtc_state *crtc_state = NULL; - const struct dpu_format *fmt; + const struct msm_format *fmt; struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; struct drm_rect fb_rect = { 0 }; @@ -858,7 +859,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return -E2BIG; } - fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); + fmt = msm_framebuffer_format(new_plane_state->fb); max_linewidth = pdpu->catalog->caps->max_linewidth; @@ -870,7 +871,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, * full width is more than max_linewidth, thus each rect is * wider than allowed. */ - if (DPU_FORMAT_IS_UBWC(fmt) && + if (MSM_FORMAT_IS_UBWC(fmt) && drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n", DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); @@ -887,7 +888,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) || (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || - DPU_FORMAT_IS_YUV(fmt)) { + MSM_FORMAT_IS_YUV(fmt)) { DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n", DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); return -E2BIG; @@ -945,8 +946,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) { - const struct dpu_format *format = - to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb)); + const struct msm_format *format = + msm_framebuffer_format(pdpu->base.state->fb); const struct dpu_csc_cfg *csc_ptr; if (!pipe->sspp || !pipe->sspp->ops.setup_csc) @@ -1017,7 +1018,7 @@ void dpu_plane_set_error(struct drm_plane *plane, bool error) static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *pipe_cfg, - const struct dpu_format *fmt, + const struct msm_format *fmt, int frame_rate, struct dpu_hw_fmt_layout *layout) { @@ -1095,8 +1096,8 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) struct drm_crtc *crtc = state->crtc; struct drm_framebuffer *fb = state->fb; bool is_rt_pipe; - const struct dpu_format *fmt = - to_dpu_format(msm_framebuffer_format(fb)); + const struct msm_format *fmt = + msm_framebuffer_format(fb); struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); @@ -1118,9 +1119,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane) pdpu->is_rt_pipe = is_rt_pipe; DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT - ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), + ", %p4cc ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src), crtc->base.id, DRM_RECT_ARG(&state->dst), - (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt)); + &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, drm_mode_vrefresh(&crtc->mode), diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index cb5ce3c62a22..44938ba7a2b7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -758,3 +758,59 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, return num_blks; } + +static void dpu_rm_print_state_helper(struct drm_printer *p, + struct dpu_hw_blk *blk, + uint32_t mapping) +{ + if (!blk) + drm_puts(p, "- "); + else if (!mapping) + drm_puts(p, "# "); + else + drm_printf(p, "%d ", mapping); +} + + +void dpu_rm_print_state(struct drm_printer *p, + const struct dpu_global_state *global_state) +{ + const struct dpu_rm *rm = global_state->rm; + int i; + + drm_puts(p, "resource mapping:\n"); + drm_puts(p, "\tpingpong="); + for (i = 0; i < ARRAY_SIZE(global_state->pingpong_to_enc_id); i++) + dpu_rm_print_state_helper(p, rm->pingpong_blks[i], + global_state->pingpong_to_enc_id[i]); + drm_puts(p, "\n"); + + drm_puts(p, "\tmixer="); + for (i = 0; i < ARRAY_SIZE(global_state->mixer_to_enc_id); i++) + dpu_rm_print_state_helper(p, rm->mixer_blks[i], + global_state->mixer_to_enc_id[i]); + drm_puts(p, "\n"); + + drm_puts(p, "\tctl="); + for (i = 0; i < ARRAY_SIZE(global_state->ctl_to_enc_id); i++) + dpu_rm_print_state_helper(p, rm->ctl_blks[i], + global_state->ctl_to_enc_id[i]); + drm_puts(p, "\n"); + + drm_puts(p, "\tdspp="); + for (i = 0; i < ARRAY_SIZE(global_state->dspp_to_enc_id); i++) + dpu_rm_print_state_helper(p, rm->dspp_blks[i], + global_state->dspp_to_enc_id[i]); + drm_puts(p, "\n"); + + drm_puts(p, "\tdsc="); + for (i = 0; i < ARRAY_SIZE(global_state->dsc_to_enc_id); i++) + dpu_rm_print_state_helper(p, rm->dsc_blks[i], + global_state->dsc_to_enc_id[i]); + drm_puts(p, "\n"); + + drm_puts(p, "\tcdm="); + dpu_rm_print_state_helper(p, rm->cdm_blk, + global_state->cdm_to_enc_id); + drm_puts(p, "\n"); +} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index e3f83ebc656b..e63db8ace6b9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -90,6 +90,14 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); /** + * dpu_rm_print_state - output the RM private state + * @p: DRM printer + * @global_state: global state + */ +void dpu_rm_print_state(struct drm_printer *p, + const struct dpu_global_state *global_state); + +/** * dpu_rm_get_intf - Return a struct dpu_hw_intf instance given it's index. * @rm: DPU Resource Manager handle * @intf_idx: INTF's index |