diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c | 614 |
1 files changed, 370 insertions, 244 deletions
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c index bc86cfd084f6..3257c522a021 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c @@ -25,7 +25,6 @@ #include <subdev/gpio.h> #include <subdev/bios.h> -#include <subdev/bios/bit.h> #include <subdev/bios/pll.h> #include <subdev/bios/init.h> #include <subdev/bios/rammap.h> @@ -42,6 +41,14 @@ #include "ramfuc.h" +/* binary driver only executes this path if the condition (a) is true + * for any configuration (combination of rammap+ramcfg+timing) that + * can be reached on a given card. for now, we will execute the branch + * unconditionally in the hope that a "false everywhere" in the bios + * tables doesn't actually mean "don't touch this". + */ +#define NOTE00(a) 1 + struct nve0_ramfuc { struct ramfuc base; @@ -104,7 +111,9 @@ struct nve0_ramfuc { struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */ struct ramfuc_reg r_0x62c000; + struct ramfuc_reg r_0x10f200; + struct ramfuc_reg r_0x10f210; struct ramfuc_reg r_0x10f310; struct ramfuc_reg r_0x10f314; @@ -118,12 +127,17 @@ struct nve0_ramfuc { struct ramfuc_reg r_0x10f65c; struct ramfuc_reg r_0x10f6bc; struct ramfuc_reg r_0x100710; - struct ramfuc_reg r_0x10f750; + struct ramfuc_reg r_0x100750; }; struct nve0_ram { struct nouveau_ram base; struct nve0_ramfuc fuc; + + u32 parts; + u32 pmask; + u32 pnuts; + int from; int mode; int N1, fN1, M1, P1; @@ -134,17 +148,17 @@ struct nve0_ram { * GDDR5 ******************************************************************************/ static void -train(struct nve0_ramfuc *fuc, u32 magic) +nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data) { struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); - struct nouveau_fb *pfb = nouveau_fb(ram); - const int mc = nv_rd32(pfb, 0x02243c); - int i; - - ram_mask(fuc, 0x10f910, 0xbc0e0000, magic); - ram_mask(fuc, 0x10f914, 0xbc0e0000, magic); - for (i = 0; i < mc; i++) { - const u32 addr = 0x110974 + (i * 0x1000); + u32 addr = 0x110974, i; + + ram_mask(fuc, 0x10f910, mask, data); + ram_mask(fuc, 0x10f914, mask, data); + + for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) { + if (ram->pmask & (1 << i)) + continue; ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000); } } @@ -199,12 +213,12 @@ r1373f4_init(struct nve0_ramfuc *fuc) } static void -r1373f4_fini(struct nve0_ramfuc *fuc, u32 ramcfg) +r1373f4_fini(struct nve0_ramfuc *fuc) { struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); - struct nouveau_bios *bios = nouveau_bios(ram); - u8 v0 = (nv_ro08(bios, ramcfg + 0x03) & 0xc0) >> 6; - u8 v1 = (nv_ro08(bios, ramcfg + 0x03) & 0x30) >> 4; + struct nouveau_ram_data *next = ram->base.next; + u8 v0 = next->bios.ramcfg_11_03_c0; + u8 v1 = next->bios.ramcfg_11_03_30; u32 tmp; tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000; @@ -220,25 +234,46 @@ r1373f4_fini(struct nve0_ramfuc *fuc, u32 ramcfg) ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4); } +static void +nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg, + u32 _mask, u32 _data, u32 _copy) +{ + struct nve0_fb_priv *priv = (void *)nouveau_fb(ram); + struct ramfuc *fuc = &ram->fuc.base; + u32 addr = 0x110000 + (reg->addr[0] & 0xfff); + u32 mask = _mask | _copy; + u32 data = (_data & _mask) | (reg->data & _copy); + u32 i; + + for (i = 0; i < 16; i++, addr += 0x1000) { + if (ram->pnuts & (1 << i)) { + u32 prev = nv_rd32(priv, addr); + u32 next = (prev & ~mask) | data; + nouveau_memx_wr32(fuc->memx, addr, next); + } + } +} +#define ram_nuts(s,r,m,d,c) \ + nve0_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c)) + static int nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) { - struct nouveau_bios *bios = nouveau_bios(pfb); struct nve0_ram *ram = (void *)pfb->ram; struct nve0_ramfuc *fuc = &ram->fuc; - const u32 rammap = ram->base.rammap.data; - const u32 ramcfg = ram->base.ramcfg.data; - const u32 timing = ram->base.timing.data; - int vc = !(nv_ro08(bios, ramcfg + 0x02) & 0x08); - int mv = 1; /*XXX*/ + struct nouveau_ram_data *next = ram->base.next; + int vc = !(next->bios.ramcfg_11_02_08); + int mv = !(next->bios.ramcfg_11_02_04); u32 mask, data; ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); ram_wr32(fuc, 0x62c000, 0x0f0f0000); /* MR1: turn termination on early, for some reason.. */ - if ((ram->base.mr[1] & 0x03c) != 0x030) + if ((ram->base.mr[1] & 0x03c) != 0x030) { ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c); + ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000); + } if (vc == 1 && ram_have(fuc, gpio2E)) { u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]); @@ -250,8 +285,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); - ram_mask(fuc, 0x10f914, 0x01020000, 0x000c0000); - ram_mask(fuc, 0x10f910, 0x01020000, 0x000c0000); + nve0_ram_train(fuc, 0x01020000, 0x000c0000); ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ ram_nsec(fuc, 1000); @@ -280,28 +314,28 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) if (1) { data |= 0x800807e0; - switch (nv_ro08(bios, ramcfg + 0x03) & 0xc0) { - case 0xc0: data &= ~0x00000040; break; - case 0x80: data &= ~0x00000100; break; - case 0x40: data &= ~0x80000000; break; - case 0x00: data &= ~0x00000400; break; + switch (next->bios.ramcfg_11_03_c0) { + case 3: data &= ~0x00000040; break; + case 2: data &= ~0x00000100; break; + case 1: data &= ~0x80000000; break; + case 0: data &= ~0x00000400; break; } - switch (nv_ro08(bios, ramcfg + 0x03) & 0x30) { - case 0x30: data &= ~0x00000020; break; - case 0x20: data &= ~0x00000080; break; - case 0x10: data &= ~0x00080000; break; - case 0x00: data &= ~0x00000200; break; + switch (next->bios.ramcfg_11_03_30) { + case 3: data &= ~0x00000020; break; + case 2: data &= ~0x00000080; break; + case 1: data &= ~0x00080000; break; + case 0: data &= ~0x00000200; break; } } - if (nv_ro08(bios, ramcfg + 0x02) & 0x80) + if (next->bios.ramcfg_11_02_80) mask |= 0x03000000; - if (nv_ro08(bios, ramcfg + 0x02) & 0x40) + if (next->bios.ramcfg_11_02_40) mask |= 0x00002000; - if (nv_ro08(bios, ramcfg + 0x07) & 0x10) + if (next->bios.ramcfg_11_07_10) mask |= 0x00004000; - if (nv_ro08(bios, ramcfg + 0x07) & 0x08) + if (next->bios.ramcfg_11_07_08) mask |= 0x00000003; else { mask |= 0x34000000; @@ -314,18 +348,18 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) if (ram->from == 2 && ram->mode != 2) { ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000); - ram_mask(fuc, 0x10f200, 0x00008000, 0x00008000); + ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000); ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004); ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010); ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); r1373f4_init(fuc); ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001); - r1373f4_fini(fuc, ramcfg); + r1373f4_fini(fuc); ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001); } else if (ram->from != 2 && ram->mode != 2) { r1373f4_init(fuc); - r1373f4_fini(fuc, ramcfg); + r1373f4_fini(fuc); } if (ram_have(fuc, gpioMV)) { @@ -336,49 +370,54 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) } } - if ( (nv_ro08(bios, ramcfg + 0x02) & 0x40) || - (nv_ro08(bios, ramcfg + 0x07) & 0x10)) { + if ( (next->bios.ramcfg_11_02_40) || + (next->bios.ramcfg_11_07_10)) { ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); ram_nsec(fuc, 20000); } if (ram->from != 2 && ram->mode == 2) { + if (0 /*XXX: Titan */) + ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000); ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002); ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010); r1373f4_init(fuc); - r1373f4_fini(fuc, ramcfg); + r1373f4_fini(fuc); ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000); ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000); } else if (ram->from == 2 && ram->mode == 2) { ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); r1373f4_init(fuc); - r1373f4_fini(fuc, ramcfg); + r1373f4_fini(fuc); } if (ram->mode != 2) /*XXX*/ { - if (nv_ro08(bios, ramcfg + 0x07) & 0x40) + if (next->bios.ramcfg_11_07_40) ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); } - data = (nv_ro08(bios, rammap + 0x11) & 0x0c) >> 2; - ram_wr32(fuc, 0x10f65c, 0x00000011 * data); - ram_wr32(fuc, 0x10f6b8, 0x01010101 * nv_ro08(bios, ramcfg + 0x09)); - ram_wr32(fuc, 0x10f6bc, 0x01010101 * nv_ro08(bios, ramcfg + 0x09)); + ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c); + ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09); + ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09); - data = nv_ro08(bios, ramcfg + 0x04); - if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) { - ram_wr32(fuc, 0x10f698, 0x01010101 * data); - ram_wr32(fuc, 0x10f69c, 0x01010101 * data); + if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) { + ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04); + ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04); + } else + if (!next->bios.ramcfg_11_07_08) { + ram_wr32(fuc, 0x10f698, 0x00000000); + ram_wr32(fuc, 0x10f69c, 0x00000000); } if (ram->mode != 2) { - u32 temp = ram_rd32(fuc, 0x10f694) & ~0xff00ff00; - ram_wr32(fuc, 0x10f694, temp | (0x01000100 * data)); + u32 data = 0x01000100 * next->bios.ramcfg_11_04; + ram_nuke(fuc, 0x10f694); + ram_mask(fuc, 0x10f694, 0xff00ff00, data); } - if (ram->mode == 2 && (nv_ro08(bios, ramcfg + 0x08) & 0x10)) + if (ram->mode == 2 && (next->bios.ramcfg_11_08_10)) data = 0x00000080; else data = 0x00000000; @@ -386,19 +425,19 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) mask = 0x00070000; data = 0x00000000; - if (!(nv_ro08(bios, ramcfg + 0x02) & 0x80)) + if (!(next->bios.ramcfg_11_02_80)) data |= 0x03000000; - if (!(nv_ro08(bios, ramcfg + 0x02) & 0x40)) + if (!(next->bios.ramcfg_11_02_40)) data |= 0x00002000; - if (!(nv_ro08(bios, ramcfg + 0x07) & 0x10)) + if (!(next->bios.ramcfg_11_07_10)) data |= 0x00004000; - if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) + if (!(next->bios.ramcfg_11_07_08)) data |= 0x00000003; else data |= 0x74000000; ram_mask(fuc, 0x10f824, mask, data); - if (nv_ro08(bios, ramcfg + 0x01) & 0x08) + if (next->bios.ramcfg_11_01_08) data = 0x00000000; else data = 0x00001000; @@ -409,61 +448,90 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000); } - if (nv_ro08(bios, ramcfg + 0x08) & 0x01) + if (next->bios.ramcfg_11_08_01) data = 0x00100000; else data = 0x00000000; ram_mask(fuc, 0x10f82c, 0x00100000, data); data = 0x00000000; - if (nv_ro08(bios, ramcfg + 0x08) & 0x08) + if (next->bios.ramcfg_11_08_08) data |= 0x00002000; - if (nv_ro08(bios, ramcfg + 0x08) & 0x04) + if (next->bios.ramcfg_11_08_04) data |= 0x00001000; - if (nv_ro08(bios, ramcfg + 0x08) & 0x02) + if (next->bios.ramcfg_11_08_02) data |= 0x00004000; ram_mask(fuc, 0x10f830, 0x00007000, data); /* PFB timing */ - ram_mask(fuc, 0x10f248, 0xffffffff, nv_ro32(bios, timing + 0x28)); - ram_mask(fuc, 0x10f290, 0xffffffff, nv_ro32(bios, timing + 0x00)); - ram_mask(fuc, 0x10f294, 0xffffffff, nv_ro32(bios, timing + 0x04)); - ram_mask(fuc, 0x10f298, 0xffffffff, nv_ro32(bios, timing + 0x08)); - ram_mask(fuc, 0x10f29c, 0xffffffff, nv_ro32(bios, timing + 0x0c)); - ram_mask(fuc, 0x10f2a0, 0xffffffff, nv_ro32(bios, timing + 0x10)); - ram_mask(fuc, 0x10f2a4, 0xffffffff, nv_ro32(bios, timing + 0x14)); - ram_mask(fuc, 0x10f2a8, 0xffffffff, nv_ro32(bios, timing + 0x18)); - ram_mask(fuc, 0x10f2ac, 0xffffffff, nv_ro32(bios, timing + 0x1c)); - ram_mask(fuc, 0x10f2cc, 0xffffffff, nv_ro32(bios, timing + 0x20)); - ram_mask(fuc, 0x10f2e8, 0xffffffff, nv_ro32(bios, timing + 0x24)); - - data = (nv_ro08(bios, ramcfg + 0x02) & 0x03) << 8; - if (nv_ro08(bios, ramcfg + 0x01) & 0x10) - data |= 0x70000000; - ram_mask(fuc, 0x10f604, 0x70000300, data); - - data = (nv_ro08(bios, timing + 0x30) & 0x07) << 28; - if (nv_ro08(bios, ramcfg + 0x01) & 0x01) - data |= 0x00000100; - ram_mask(fuc, 0x10f614, 0x70000000, data); - - data = (nv_ro08(bios, timing + 0x30) & 0x07) << 28; - if (nv_ro08(bios, ramcfg + 0x01) & 0x02) - data |= 0x00000100; - ram_mask(fuc, 0x10f610, 0x70000000, data); + ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); + ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); + ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); + ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); + ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); + ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); + ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); + ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); + ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); + ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); + ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); + + data = mask = 0x00000000; + if (NOTE00(ramcfg_08_20)) { + if (next->bios.ramcfg_11_08_20) + data |= 0x01000000; + mask |= 0x01000000; + } + ram_mask(fuc, 0x10f200, mask, data); + + data = mask = 0x00000000; + if (NOTE00(ramcfg_02_03 != 0)) { + data |= (next->bios.ramcfg_11_02_03) << 8; + mask |= 0x00000300; + } + if (NOTE00(ramcfg_01_10)) { + if (next->bios.ramcfg_11_01_10) + data |= 0x70000000; + mask |= 0x70000000; + } + ram_mask(fuc, 0x10f604, mask, data); + + data = mask = 0x00000000; + if (NOTE00(timing_30_07 != 0)) { + data |= (next->bios.timing_20_30_07) << 28; + mask |= 0x70000000; + } + if (NOTE00(ramcfg_01_01)) { + if (next->bios.ramcfg_11_01_01) + data |= 0x00000100; + mask |= 0x00000100; + } + ram_mask(fuc, 0x10f614, mask, data); + + data = mask = 0x00000000; + if (NOTE00(timing_30_07 != 0)) { + data |= (next->bios.timing_20_30_07) << 28; + mask |= 0x70000000; + } + if (NOTE00(ramcfg_01_02)) { + if (next->bios.ramcfg_11_01_02) + data |= 0x00000100; + mask |= 0x00000100; + } + ram_mask(fuc, 0x10f610, mask, data); mask = 0x33f00000; data = 0x00000000; - if (!(nv_ro08(bios, ramcfg + 0x01) & 0x04)) + if (!(next->bios.ramcfg_11_01_04)) data |= 0x20200000; - if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80)) + if (!(next->bios.ramcfg_11_07_80)) data |= 0x12800000; /*XXX: see note above about there probably being some condition * for the 10f824 stuff that uses ramcfg 3... */ - if ( (nv_ro08(bios, ramcfg + 0x03) & 0xf0)) { - if (nv_ro08(bios, rammap + 0x08) & 0x0c) { - if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80)) + if ( (next->bios.ramcfg_11_03_f0)) { + if (next->bios.rammap_11_08_0c) { + if (!(next->bios.ramcfg_11_07_80)) mask |= 0x00000020; else data |= 0x00000020; @@ -476,49 +544,53 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x10f808, mask, data); - data = nv_ro08(bios, ramcfg + 0x03) & 0x0f; - ram_wr32(fuc, 0x10f870, 0x11111111 * data); + ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f); - data = nv_ro08(bios, ramcfg + 0x02) & 0x03; - if (nv_ro08(bios, ramcfg + 0x01) & 0x10) - data |= 0x00000004; - if ((nv_rd32(bios, 0x100770) & 0x00000004) != (data & 0x00000004)) { - ram_wr32(fuc, 0x10f750, 0x04000009); + data = mask = 0x00000000; + if (NOTE00(ramcfg_02_03 != 0)) { + data |= next->bios.ramcfg_11_02_03; + mask |= 0x00000003; + } + if (NOTE00(ramcfg_01_10)) { + if (next->bios.ramcfg_11_01_10) + data |= 0x00000004; + mask |= 0x00000004; + } + + if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) { + ram_mask(fuc, 0x100750, 0x00000008, 0x00000008); ram_wr32(fuc, 0x100710, 0x00000000); ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000); } - ram_mask(fuc, 0x100770, 0x00000007, data); - data = (nv_ro08(bios, timing + 0x30) & 0x07) << 8; - if (nv_ro08(bios, ramcfg + 0x01) & 0x01) + data = (next->bios.timing_20_30_07) << 8; + if (next->bios.ramcfg_11_01_01) data |= 0x80000000; ram_mask(fuc, 0x100778, 0x00000700, data); - data = nv_ro16(bios, timing + 0x2c); - ram_mask(fuc, 0x10f250, 0x000003f0, (data & 0x003f) << 4); - ram_mask(fuc, 0x10f24c, 0x7f000000, (data & 0x1fc0) << 18); - - data = nv_ro08(bios, timing + 0x30); - ram_mask(fuc, 0x10f224, 0x001f0000, (data & 0xf8) << 13); + ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4); + data = (next->bios.timing[10] & 0x7f000000) >> 24; + if (data < next->bios.timing_20_2c_1fc0) + data = next->bios.timing_20_2c_1fc0; + ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); + ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16); - data = nv_ro16(bios, timing + 0x31); - ram_mask(fuc, 0x10fec4, 0x041e0f07, (data & 0x0800) << 15 | - (data & 0x0780) << 10 | - (data & 0x0078) << 5 | - (data & 0x0007)); - ram_mask(fuc, 0x10fec8, 0x00000027, (data & 0x8000) >> 10 | - (data & 0x7000) >> 12); + ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 | + next->bios.timing_20_31_0780 << 17 | + next->bios.timing_20_31_0078 << 8 | + next->bios.timing_20_31_0007); + ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 | + next->bios.timing_20_31_7000); ram_wr32(fuc, 0x10f090, 0x4000007e); - ram_nsec(fuc, 1000); + ram_nsec(fuc, 2000); ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ - ram_nsec(fuc, 2000); ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ - if ((nv_ro08(bios, ramcfg + 0x08) & 0x10) && (ram->mode == 2) /*XXX*/) { + if ((next->bios.ramcfg_11_08_10) && (ram->mode == 2) /*XXX*/) { u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); - train(fuc, 0xa4010000); /*XXX*/ + nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ ram_nsec(fuc, 1000); ram_wr32(fuc, 0x10f294, temp); } @@ -528,7 +600,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]); ram_nsec(fuc, 1000); ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]); - ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5]); + ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */ ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]); ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]); @@ -544,12 +616,13 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */ ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); ram_nsec(fuc, 1000); + ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800); data = ram_rd32(fuc, 0x10f978); data &= ~0x00046144; data |= 0x0000000b; - if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) { - if (!(nv_ro08(bios, ramcfg + 0x07) & 0x04)) + if (!(next->bios.ramcfg_11_07_08)) { + if (!(next->bios.ramcfg_11_07_04)) data |= 0x0000200c; else data |= 0x00000000; @@ -563,44 +636,43 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ram_wr32(fuc, 0x10f830, data); } - if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) { + if (!(next->bios.ramcfg_11_07_08)) { data = 0x88020000; - if ( (nv_ro08(bios, ramcfg + 0x07) & 0x04)) + if ( (next->bios.ramcfg_11_07_04)) data |= 0x10000000; - if (!(nv_ro08(bios, rammap + 0x08) & 0x10)) + if (!(next->bios.rammap_11_08_10)) data |= 0x00080000; } else { data = 0xa40e0000; } - train(fuc, data); - ram_nsec(fuc, 1000); + nve0_ram_train(fuc, 0xbc0f0000, data); + if (1) /* XXX: not always? */ + ram_nsec(fuc, 1000); if (ram->mode == 2) { /*XXX*/ ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004); } - /* MR5: (re)enable LP3 if necessary - * XXX: need to find the switch, keeping off for now - */ - ram_mask(fuc, mr[5], 0x00000004, 0x00000000); + /* LP3 */ + if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5]) + ram_nsec(fuc, 1000); if (ram->mode != 2) { ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000); ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); } - if (nv_ro08(bios, ramcfg + 0x07) & 0x02) { - ram_mask(fuc, 0x10f910, 0x80020000, 0x01000000); - ram_mask(fuc, 0x10f914, 0x80020000, 0x01000000); - } + if (next->bios.ramcfg_11_07_02) + nve0_ram_train(fuc, 0x80020000, 0x01000000); ram_wr32(fuc, 0x62c000, 0x0f0f0f00); - if (nv_ro08(bios, rammap + 0x08) & 0x01) + if (next->bios.rammap_11_08_01) data = 0x00000800; else data = 0x00000000; ram_mask(fuc, 0x10f200, 0x00000800, data); + ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800); return 0; } @@ -611,17 +683,14 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) static int nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) { - struct nouveau_bios *bios = nouveau_bios(pfb); struct nve0_ram *ram = (void *)pfb->ram; struct nve0_ramfuc *fuc = &ram->fuc; const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); const u32 runk0 = ram->fN1 << 16; const u32 runk1 = ram->fN1; - const u32 rammap = ram->base.rammap.data; - const u32 ramcfg = ram->base.ramcfg.data; - const u32 timing = ram->base.timing.data; - int vc = !(nv_ro08(bios, ramcfg + 0x02) & 0x08); - int mv = 1; /*XXX*/ + struct nouveau_ram_data *next = ram->base.next; + int vc = !(next->bios.ramcfg_11_02_08); + int mv = !(next->bios.ramcfg_11_02_04); u32 mask, data; ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); @@ -636,7 +705,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) } ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); - if ((nv_ro08(bios, ramcfg + 0x03) & 0xf0)) + if ((next->bios.ramcfg_11_03_f0)) ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000); ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ @@ -661,28 +730,28 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) if (1) { mask |= 0x800807e0; data |= 0x800807e0; - switch (nv_ro08(bios, ramcfg + 0x03) & 0xc0) { - case 0xc0: data &= ~0x00000040; break; - case 0x80: data &= ~0x00000100; break; - case 0x40: data &= ~0x80000000; break; - case 0x00: data &= ~0x00000400; break; + switch (next->bios.ramcfg_11_03_c0) { + case 3: data &= ~0x00000040; break; + case 2: data &= ~0x00000100; break; + case 1: data &= ~0x80000000; break; + case 0: data &= ~0x00000400; break; } - switch (nv_ro08(bios, ramcfg + 0x03) & 0x30) { - case 0x30: data &= ~0x00000020; break; - case 0x20: data &= ~0x00000080; break; - case 0x10: data &= ~0x00080000; break; - case 0x00: data &= ~0x00000200; break; + switch (next->bios.ramcfg_11_03_30) { + case 3: data &= ~0x00000020; break; + case 2: data &= ~0x00000080; break; + case 1: data &= ~0x00080000; break; + case 0: data &= ~0x00000200; break; } } - if (nv_ro08(bios, ramcfg + 0x02) & 0x80) + if (next->bios.ramcfg_11_02_80) mask |= 0x03000000; - if (nv_ro08(bios, ramcfg + 0x02) & 0x40) + if (next->bios.ramcfg_11_02_40) mask |= 0x00002000; - if (nv_ro08(bios, ramcfg + 0x07) & 0x10) + if (next->bios.ramcfg_11_07_10) mask |= 0x00004000; - if (nv_ro08(bios, ramcfg + 0x07) & 0x08) + if (next->bios.ramcfg_11_07_08) mask |= 0x00000003; else mask |= 0x14000000; @@ -692,7 +761,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); data = ram_rd32(fuc, 0x1373ec) & ~0x00030000; - data |= (nv_ro08(bios, ramcfg + 0x03) & 0x30) << 12; + data |= (next->bios.ramcfg_11_03_30) << 12; ram_wr32(fuc, 0x1373ec, data); ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); @@ -724,68 +793,67 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) } } - if ( (nv_ro08(bios, ramcfg + 0x02) & 0x40) || - (nv_ro08(bios, ramcfg + 0x07) & 0x10)) { + if ( (next->bios.ramcfg_11_02_40) || + (next->bios.ramcfg_11_07_10)) { ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); ram_nsec(fuc, 20000); } if (ram->mode != 2) /*XXX*/ { - if (nv_ro08(bios, ramcfg + 0x07) & 0x40) + if (next->bios.ramcfg_11_07_40) ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); } - data = (nv_ro08(bios, rammap + 0x11) & 0x0c) >> 2; - ram_wr32(fuc, 0x10f65c, 0x00000011 * data); - ram_wr32(fuc, 0x10f6b8, 0x01010101 * nv_ro08(bios, ramcfg + 0x09)); - ram_wr32(fuc, 0x10f6bc, 0x01010101 * nv_ro08(bios, ramcfg + 0x09)); + ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c); + ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09); + ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09); mask = 0x00010000; data = 0x00000000; - if (!(nv_ro08(bios, ramcfg + 0x02) & 0x80)) + if (!(next->bios.ramcfg_11_02_80)) data |= 0x03000000; - if (!(nv_ro08(bios, ramcfg + 0x02) & 0x40)) + if (!(next->bios.ramcfg_11_02_40)) data |= 0x00002000; - if (!(nv_ro08(bios, ramcfg + 0x07) & 0x10)) + if (!(next->bios.ramcfg_11_07_10)) data |= 0x00004000; - if (!(nv_ro08(bios, ramcfg + 0x07) & 0x08)) + if (!(next->bios.ramcfg_11_07_08)) data |= 0x00000003; else data |= 0x14000000; ram_mask(fuc, 0x10f824, mask, data); ram_nsec(fuc, 1000); - if (nv_ro08(bios, ramcfg + 0x08) & 0x01) + if (next->bios.ramcfg_11_08_01) data = 0x00100000; else data = 0x00000000; ram_mask(fuc, 0x10f82c, 0x00100000, data); /* PFB timing */ - ram_mask(fuc, 0x10f248, 0xffffffff, nv_ro32(bios, timing + 0x28)); - ram_mask(fuc, 0x10f290, 0xffffffff, nv_ro32(bios, timing + 0x00)); - ram_mask(fuc, 0x10f294, 0xffffffff, nv_ro32(bios, timing + 0x04)); - ram_mask(fuc, 0x10f298, 0xffffffff, nv_ro32(bios, timing + 0x08)); - ram_mask(fuc, 0x10f29c, 0xffffffff, nv_ro32(bios, timing + 0x0c)); - ram_mask(fuc, 0x10f2a0, 0xffffffff, nv_ro32(bios, timing + 0x10)); - ram_mask(fuc, 0x10f2a4, 0xffffffff, nv_ro32(bios, timing + 0x14)); - ram_mask(fuc, 0x10f2a8, 0xffffffff, nv_ro32(bios, timing + 0x18)); - ram_mask(fuc, 0x10f2ac, 0xffffffff, nv_ro32(bios, timing + 0x1c)); - ram_mask(fuc, 0x10f2cc, 0xffffffff, nv_ro32(bios, timing + 0x20)); - ram_mask(fuc, 0x10f2e8, 0xffffffff, nv_ro32(bios, timing + 0x24)); + ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); + ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); + ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); + ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); + ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); + ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); + ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); + ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); + ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); + ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); + ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); mask = 0x33f00000; data = 0x00000000; - if (!(nv_ro08(bios, ramcfg + 0x01) & 0x04)) + if (!(next->bios.ramcfg_11_01_04)) data |= 0x20200000; - if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80)) + if (!(next->bios.ramcfg_11_07_80)) data |= 0x12800000; /*XXX: see note above about there probably being some condition * for the 10f824 stuff that uses ramcfg 3... */ - if ( (nv_ro08(bios, ramcfg + 0x03) & 0xf0)) { - if (nv_ro08(bios, rammap + 0x08) & 0x0c) { - if (!(nv_ro08(bios, ramcfg + 0x07) & 0x80)) + if ( (next->bios.ramcfg_11_03_f0)) { + if (next->bios.rammap_11_08_0c) { + if (!(next->bios.ramcfg_11_07_80)) mask |= 0x00000020; else data |= 0x00000020; @@ -799,21 +867,16 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x10f808, mask, data); - data = nv_ro08(bios, ramcfg + 0x03) & 0x0f; - ram_wr32(fuc, 0x10f870, 0x11111111 * data); + ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f); - data = nv_ro16(bios, timing + 0x2c); - ram_mask(fuc, 0x10f250, 0x000003f0, (data & 0x003f) << 4); + ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4); - if (((nv_ro32(bios, timing + 0x2c) & 0x00001fc0) >> 6) > - ((nv_ro32(bios, timing + 0x28) & 0x7f000000) >> 24)) - data = (nv_ro32(bios, timing + 0x2c) & 0x00001fc0) >> 6; - else - data = (nv_ro32(bios, timing + 0x28) & 0x1f000000) >> 24; + data = (next->bios.timing[10] & 0x7f000000) >> 24; + if (data < next->bios.timing_20_2c_1fc0) + data = next->bios.timing_20_2c_1fc0; ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); - data = nv_ro08(bios, timing + 0x30); - ram_mask(fuc, 0x10f224, 0x001f0000, (data & 0xf8) << 13); + ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8); ram_wr32(fuc, 0x10f090, 0x4000007f); ram_nsec(fuc, 1000); @@ -855,7 +918,7 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) ram_wr32(fuc, 0x62c000, 0x0f0f0f00); - if (nv_ro08(bios, rammap + 0x08) & 0x01) + if (next->bios.rammap_11_08_01) data = 0x00000800; else data = 0x00000000; @@ -868,21 +931,18 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) ******************************************************************************/ static int -nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) +nve0_ram_calc_data(struct nouveau_fb *pfb, u32 freq, + struct nouveau_ram_data *data) { struct nouveau_bios *bios = nouveau_bios(pfb); struct nve0_ram *ram = (void *)pfb->ram; - struct nve0_ramfuc *fuc = &ram->fuc; - struct bit_entry M; - int ret, refclk, strap, i; - u32 data; - u8 cnt; + u8 strap, cnt, len; /* lookup memory config data relevant to the target frequency */ - ram->base.rammap.data = nvbios_rammap_match(bios, freq / 1000, - &ram->base.rammap.version, - &ram->base.rammap.size, &cnt, - &ram->base.ramcfg.size); + ram->base.rammap.data = nvbios_rammapEp(bios, freq / 1000, + &ram->base.rammap.version, + &ram->base.rammap.size, + &cnt, &len, &data->bios); if (!ram->base.rammap.data || ram->base.rammap.version != 0x11 || ram->base.rammap.size < 0x09) { nv_error(pfb, "invalid/missing rammap entry\n"); @@ -890,24 +950,13 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) } /* locate specific data set for the attached memory */ - if (bit_entry(bios, 'M', &M) || M.version != 2 || M.length < 3) { - nv_error(pfb, "invalid/missing memory table\n"); - return -EINVAL; - } - - strap = (nv_rd32(pfb, 0x101000) & 0x0000003c) >> 2; - data = nv_ro16(bios, M.offset + 1); - if (data) - strap = nv_ro08(bios, data + strap); - - if (strap >= cnt) { - nv_error(pfb, "invalid ramcfg strap\n"); - return -EINVAL; - } - - ram->base.ramcfg.version = ram->base.rammap.version; - ram->base.ramcfg.data = ram->base.rammap.data + ram->base.rammap.size + - (ram->base.ramcfg.size * strap); + ram->base.ramcfg.data = nvbios_rammapSp(bios, ram->base.rammap.data, + ram->base.rammap.version, + ram->base.rammap.size, cnt, len, + nvbios_ramcfg_index(bios), + &ram->base.ramcfg.version, + &ram->base.ramcfg.size, + &data->bios); if (!ram->base.ramcfg.data || ram->base.ramcfg.version != 0x11 || ram->base.ramcfg.size < 0x08) { nv_error(pfb, "invalid/missing ramcfg entry\n"); @@ -918,9 +967,9 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) strap = nv_ro08(bios, ram->base.ramcfg.data + 0x00); if (strap != 0xff) { ram->base.timing.data = - nvbios_timing_entry(bios, strap, - &ram->base.timing.version, - &ram->base.timing.size); + nvbios_timingEp(bios, strap, &ram->base.timing.version, + &ram->base.timing.size, &cnt, &len, + &data->bios); if (!ram->base.timing.data || ram->base.timing.version != 0x20 || ram->base.timing.size < 0x33) { @@ -931,11 +980,23 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) ram->base.timing.data = 0; } + data->freq = freq; + return 0; +} + +static int +nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) +{ + struct nve0_ram *ram = (void *)pfb->ram; + struct nve0_ramfuc *fuc = &ram->fuc; + int refclk, i; + int ret; + ret = ram_init(fuc, pfb); if (ret) return ret; - ram->mode = (freq > fuc->refpll.vco1.max_freq) ? 2 : 1; + ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1; ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f; /* XXX: this is *not* what nvidia do. on fermi nvidia generally @@ -946,7 +1007,7 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) * so far, i've seen very weird values being chosen by nvidia on * kepler boards, no idea how/why they're chosen. */ - refclk = freq; + refclk = next->freq; if (ram->mode == 2) refclk = fuc->mempll.refclk; @@ -968,7 +1029,7 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) fuc->mempll.min_p = 1; fuc->mempll.max_p = 2; - ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, freq, + ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq, &ram->N2, NULL, &ram->M2, &ram->P2); if (ret <= 0) { nv_error(pfb, "unable to calc mempll\n"); @@ -980,17 +1041,18 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) if (ram_have(fuc, mr[i])) ram->base.mr[i] = ram_rd32(fuc, mr[i]); } + ram->base.freq = next->freq; switch (ram->base.type) { case NV_MEM_TYPE_DDR3: ret = nouveau_sddr3_calc(&ram->base); if (ret == 0) - ret = nve0_ram_calc_sddr3(pfb, freq); + ret = nve0_ram_calc_sddr3(pfb, next->freq); break; case NV_MEM_TYPE_GDDR5: - ret = nouveau_gddr5_calc(&ram->base); + ret = nouveau_gddr5_calc(&ram->base, ram->pnuts != 0); if (ret == 0) - ret = nve0_ram_calc_gddr5(pfb, freq); + ret = nve0_ram_calc_gddr5(pfb, next->freq); break; default: ret = -ENOSYS; @@ -1001,13 +1063,55 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) } static int +nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) +{ + struct nouveau_clock *clk = nouveau_clock(pfb); + struct nve0_ram *ram = (void *)pfb->ram; + struct nouveau_ram_data *xits = &ram->base.xition; + struct nouveau_ram_data *copy; + int ret; + + if (ram->base.next == NULL) { + ret = nve0_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem), + &ram->base.former); + if (ret) + return ret; + + ret = nve0_ram_calc_data(pfb, freq, &ram->base.target); + if (ret) + return ret; + + if (ram->base.target.freq < ram->base.former.freq) { + *xits = ram->base.target; + copy = &ram->base.former; + } else { + *xits = ram->base.former; + copy = &ram->base.target; + } + + xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04; + xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03; + xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07; + + ram->base.next = &ram->base.target; + if (memcmp(xits, &ram->base.former, sizeof(xits->bios))) + ram->base.next = &ram->base.xition; + } else { + BUG_ON(ram->base.next != &ram->base.xition); + ram->base.next = &ram->base.target; + } + + return nve0_ram_calc_xits(pfb, ram->base.next); +} + +static int nve0_ram_prog(struct nouveau_fb *pfb) { struct nouveau_device *device = nv_device(pfb); struct nve0_ram *ram = (void *)pfb->ram; struct nve0_ramfuc *fuc = &ram->fuc; ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", false)); - return 0; + return (ram->base.next == &ram->base.xition); } static void @@ -1015,6 +1119,7 @@ nve0_ram_tidy(struct nouveau_fb *pfb) { struct nve0_ram *ram = (void *)pfb->ram; struct nve0_ramfuc *fuc = &ram->fuc; + ram->base.next = NULL; ram_exec(fuc, false); } @@ -1055,7 +1160,7 @@ nve0_ram_init(struct nouveau_object *object) * binary driver skips the one that's already been setup by * the init tables. */ - data = nvbios_rammap_table(bios, &ver, &hdr, &cnt, &len, &snr, &ssz); + data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz); if (!data || hdr < 0x15) return -EINVAL; @@ -1073,6 +1178,7 @@ nve0_ram_init(struct nouveau_object *object) data += 4; } nv_wr32(pfb, 0x10f65c, save); + nv_mask(pfb, 0x10f584, 0x11000000, 0x00000000); switch (ram->base.type) { case NV_MEM_TYPE_GDDR5: @@ -1117,7 +1223,8 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_gpio *gpio = nouveau_gpio(pfb); struct dcb_gpio_func func; struct nve0_ram *ram; - int ret; + int ret, i; + u32 tmp; ret = nvc0_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); @@ -1136,6 +1243,25 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, break; } + /* calculate a mask of differently configured memory partitions, + * because, of course reclocking wasn't complicated enough + * already without having to treat some of them differently to + * the others.... + */ + ram->parts = nv_rd32(pfb, 0x022438); + ram->pmask = nv_rd32(pfb, 0x022554); + ram->pnuts = 0; + for (i = 0, tmp = 0; i < ram->parts; i++) { + if (!(ram->pmask & (1 << i))) { + u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000)); + if (tmp && tmp != cfg1) { + ram->pnuts |= (1 << i); + continue; + } + tmp = cfg1; + } + } + // parse bios data for both pll's ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll); if (ret) { @@ -1248,7 +1374,7 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c); ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc); ram->fuc.r_0x100710 = ramfuc_reg(0x100710); - ram->fuc.r_0x10f750 = ramfuc_reg(0x10f750); + ram->fuc.r_0x100750 = ramfuc_reg(0x100750); return 0; } |