diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/include')
19 files changed, 227 insertions, 167 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl5070.h b/drivers/gpu/drm/nouveau/include/nvif/cl5070.h index 53800fb46582..56affb606adf 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/cl5070.h +++ b/drivers/gpu/drm/nouveau/include/nvif/cl5070.h @@ -30,7 +30,6 @@ struct nv50_disp_mthd_v1 { __u8 version; #define NV50_DISP_MTHD_V1_ACQUIRE 0x01 #define NV50_DISP_MTHD_V1_RELEASE 0x02 -#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 @@ -50,13 +49,6 @@ struct nv50_disp_acquire_v0 { __u8 pad04[4]; }; -struct nv50_disp_dac_load_v0 { - __u8 version; - __u8 load; - __u8 pad02[2]; - __u32 data; -}; - struct nv50_disp_sor_hda_eld_v0 { __u8 version; __u8 pad01[7]; diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507a.h b/drivers/gpu/drm/nouveau/include/nvif/cl507a.h deleted file mode 100644 index 3b2a9809b8ce..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvif/cl507a.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef __NVIF_CL507A_H__ -#define __NVIF_CL507A_H__ - -struct nv50_disp_cursor_v0 { - __u8 version; - __u8 head; - __u8 pad02[6]; -}; - -#define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00 -#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507b.h b/drivers/gpu/drm/nouveau/include/nvif/cl507b.h deleted file mode 100644 index 0f3d05581ea5..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvif/cl507b.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef __NVIF_CL507B_H__ -#define __NVIF_CL507B_H__ - -struct nv50_disp_overlay_v0 { - __u8 version; - __u8 head; - __u8 pad02[6]; -}; - -#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 -#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507c.h b/drivers/gpu/drm/nouveau/include/nvif/cl507c.h deleted file mode 100644 index 7da8813f4f5c..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvif/cl507c.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef __NVIF_CL507C_H__ -#define __NVIF_CL507C_H__ - -struct nv50_disp_base_channel_dma_v0 { - __u8 version; - __u8 head; - __u8 pad02[6]; - __u64 pushbuf; -}; - -#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 -#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507d.h b/drivers/gpu/drm/nouveau/include/nvif/cl507d.h deleted file mode 100644 index 4a56e42d8bc9..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvif/cl507d.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef __NVIF_CL507D_H__ -#define __NVIF_CL507D_H__ - -struct nv50_disp_core_channel_dma_v0 { - __u8 version; - __u8 pad01[7]; - __u64 pushbuf; -}; - -#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 -#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl507e.h b/drivers/gpu/drm/nouveau/include/nvif/cl507e.h deleted file mode 100644 index 633936cb6313..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvif/cl507e.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef __NVIF_CL507E_H__ -#define __NVIF_CL507E_H__ - -struct nv50_disp_overlay_channel_dma_v0 { - __u8 version; - __u8 head; - __u8 pad02[6]; - __u64 pushbuf; -}; - -#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 -#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index a582c0cb0cb0..8641db649f48 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -32,6 +32,11 @@ #define NVIF_CLASS_VMM_GM200 /* ifb00d.h */ 0x8000b00d #define NVIF_CLASS_VMM_GP100 /* ifc00d.h */ 0x8000c00d +#define NVIF_CLASS_DISP /* if0010.h */ 0x80000010 +#define NVIF_CLASS_CONN /* if0011.h */ 0x80000011 +#define NVIF_CLASS_OUTP /* if0012.h */ 0x80000012 +#define NVIF_CLASS_DISP_CHAN /* if0014.h */ 0x80000014 + /* the below match nvidia-assigned (either in hw, or sw) class numbers */ #define NV_NULL_CLASS 0x00000030 @@ -73,21 +78,21 @@ #define TURING_CHANNEL_GPFIFO_A /* clc36f.h */ 0x0000c46f #define AMPERE_CHANNEL_GPFIFO_B /* clc36f.h */ 0x0000c76f -#define NV50_DISP /* cl5070.h */ 0x00005070 -#define G82_DISP /* cl5070.h */ 0x00008270 -#define GT200_DISP /* cl5070.h */ 0x00008370 -#define GT214_DISP /* cl5070.h */ 0x00008570 -#define GT206_DISP /* cl5070.h */ 0x00008870 -#define GF110_DISP /* cl5070.h */ 0x00009070 -#define GK104_DISP /* cl5070.h */ 0x00009170 -#define GK110_DISP /* cl5070.h */ 0x00009270 -#define GM107_DISP /* cl5070.h */ 0x00009470 -#define GM200_DISP /* cl5070.h */ 0x00009570 -#define GP100_DISP /* cl5070.h */ 0x00009770 -#define GP102_DISP /* cl5070.h */ 0x00009870 -#define GV100_DISP /* cl5070.h */ 0x0000c370 -#define TU102_DISP /* cl5070.h */ 0x0000c570 -#define GA102_DISP /* cl5070.h */ 0x0000c670 +#define NV50_DISP /* if0010.h */ 0x00005070 +#define G82_DISP /* if0010.h */ 0x00008270 +#define GT200_DISP /* if0010.h */ 0x00008370 +#define GT214_DISP /* if0010.h */ 0x00008570 +#define GT206_DISP /* if0010.h */ 0x00008870 +#define GF110_DISP /* if0010.h */ 0x00009070 +#define GK104_DISP /* if0010.h */ 0x00009170 +#define GK110_DISP /* if0010.h */ 0x00009270 +#define GM107_DISP /* if0010.h */ 0x00009470 +#define GM200_DISP /* if0010.h */ 0x00009570 +#define GP100_DISP /* if0010.h */ 0x00009770 +#define GP102_DISP /* if0010.h */ 0x00009870 +#define GV100_DISP /* if0010.h */ 0x0000c370 +#define TU102_DISP /* if0010.h */ 0x0000c570 +#define GA102_DISP /* if0010.h */ 0x0000c670 #define GV100_DISP_CAPS 0x0000c373 @@ -96,59 +101,59 @@ #define NV74_VP2 0x00007476 -#define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a -#define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a -#define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a -#define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a -#define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a -#define GV100_DISP_CURSOR /* cl507a.h */ 0x0000c37a -#define TU102_DISP_CURSOR /* cl507a.h */ 0x0000c57a -#define GA102_DISP_CURSOR /* cl507a.h */ 0x0000c67a - -#define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b -#define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b -#define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b -#define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b -#define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b - -#define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c37b -#define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c57b -#define GA102_DISP_WINDOW_IMM_CHANNEL_DMA /* clc37b.h */ 0x0000c67b - -#define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c -#define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c -#define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c -#define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c -#define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c -#define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c -#define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c - -#define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d -#define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d -#define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d -#define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d -#define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d -#define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d -#define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d -#define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d -#define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d -#define GM200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d -#define GP100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000977d -#define GP102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000987d -#define GV100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c37d -#define TU102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c57d -#define GA102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000c67d - -#define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e -#define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e -#define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e -#define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e -#define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e -#define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e - -#define GV100_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c37e -#define TU102_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c57e -#define GA102_DISP_WINDOW_CHANNEL_DMA /* clc37e.h */ 0x0000c67e +#define NV50_DISP_CURSOR /* if0014.h */ 0x0000507a +#define G82_DISP_CURSOR /* if0014.h */ 0x0000827a +#define GT214_DISP_CURSOR /* if0014.h */ 0x0000857a +#define GF110_DISP_CURSOR /* if0014.h */ 0x0000907a +#define GK104_DISP_CURSOR /* if0014.h */ 0x0000917a +#define GV100_DISP_CURSOR /* if0014.h */ 0x0000c37a +#define TU102_DISP_CURSOR /* if0014.h */ 0x0000c57a +#define GA102_DISP_CURSOR /* if0014.h */ 0x0000c67a + +#define NV50_DISP_OVERLAY /* if0014.h */ 0x0000507b +#define G82_DISP_OVERLAY /* if0014.h */ 0x0000827b +#define GT214_DISP_OVERLAY /* if0014.h */ 0x0000857b +#define GF110_DISP_OVERLAY /* if0014.h */ 0x0000907b +#define GK104_DISP_OVERLAY /* if0014.h */ 0x0000917b + +#define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c37b +#define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c57b +#define GA102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c67b + +#define NV50_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000507c +#define G82_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000827c +#define GT200_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000837c +#define GT214_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000857c +#define GF110_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000907c +#define GK104_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000917c +#define GK110_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000927c + +#define NV50_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000507d +#define G82_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000827d +#define GT200_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000837d +#define GT214_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000857d +#define GT206_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000887d +#define GF110_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000907d +#define GK104_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000917d +#define GK110_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000927d +#define GM107_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000947d +#define GM200_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000957d +#define GP100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000977d +#define GP102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000987d +#define GV100_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c37d +#define TU102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c57d +#define GA102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c67d + +#define NV50_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000507e +#define G82_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000827e +#define GT200_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000837e +#define GT214_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000857e +#define GF110_DISP_OVERLAY_CONTROL_DMA /* if0014.h */ 0x0000907e +#define GK104_DISP_OVERLAY_CONTROL_DMA /* if0014.h */ 0x0000917e + +#define GV100_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c37e +#define TU102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c57e +#define GA102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c67e #define NV50_TESLA 0x00005097 #define G82_TESLA 0x00008297 diff --git a/drivers/gpu/drm/nouveau/include/nvif/clc37b.h b/drivers/gpu/drm/nouveau/include/nvif/clc37b.h deleted file mode 100644 index 970a5ac4cb95..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvif/clc37b.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef __NVIF_CLC37B_H__ -#define __NVIF_CLC37B_H__ - -struct nvc37b_window_imm_channel_dma_v0 { - __u8 version; - __u8 index; - __u8 pad02[6]; - __u64 pushbuf; -}; -#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/clc37e.h b/drivers/gpu/drm/nouveau/include/nvif/clc37e.h deleted file mode 100644 index 7ea23695e7e1..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvif/clc37e.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef __NVIF_CLC37E_H__ -#define __NVIF_CLC37E_H__ - -struct nvc37e_window_channel_dma_v0 { - __u8 version; - __u8 index; - __u8 pad02[6]; - __u64 pushbuf; -}; - -#define NVC37E_WINDOW_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 -#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/conn.h b/drivers/gpu/drm/nouveau/include/nvif/conn.h new file mode 100644 index 000000000000..f72a8f138f47 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/conn.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef __NVIF_CONN_H__ +#define __NVIF_CONN_H__ +#include <nvif/object.h> +struct nvif_disp; + +struct nvif_conn { + struct nvif_object object; +}; + +int nvif_conn_ctor(struct nvif_disp *, const char *name, int id, struct nvif_conn *); +void nvif_conn_dtor(struct nvif_conn *); + +#define NVIF_CONN_HPD_STATUS_UNSUPPORTED 0 /* negative if query fails */ +#define NVIF_CONN_HPD_STATUS_NOT_PRESENT 1 +#define NVIF_CONN_HPD_STATUS_PRESENT 2 +int nvif_conn_hpd_status(struct nvif_conn *); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/disp.h b/drivers/gpu/drm/nouveau/include/nvif/disp.h index 07ac544f282f..742632ad3bea 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/disp.h +++ b/drivers/gpu/drm/nouveau/include/nvif/disp.h @@ -5,6 +5,8 @@ struct nvif_device; struct nvif_disp { struct nvif_object object; + unsigned long conn_mask; + unsigned long outp_mask; }; int nvif_disp_ctor(struct nvif_device *, const char *name, s32 oclass, diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0010.h b/drivers/gpu/drm/nouveau/include/nvif/if0010.h new file mode 100644 index 000000000000..fc236ef28965 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/if0010.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef __NVIF_IF0010_H__ +#define __NVIF_IF0010_H__ + +union nvif_disp_args { + struct nvif_disp_v0 { + __u8 version; + __u8 pad01[3]; + __u32 conn_mask; + __u32 outp_mask; + } v0; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0011.h b/drivers/gpu/drm/nouveau/include/nvif/if0011.h new file mode 100644 index 000000000000..04ba6581f840 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/if0011.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef __NVIF_IF0011_H__ +#define __NVIF_IF0011_H__ + +union nvif_conn_args { + struct nvif_conn_v0 { + __u8 version; + __u8 id; /* DCB connector table index. */ + __u8 pad02[6]; + } v0; +}; + +#define NVIF_CONN_V0_HPD_STATUS 0x00000000 + +union nvif_conn_hpd_status_args { + struct nvif_conn_hpd_status_v0 { + __u8 version; + __u8 support; + __u8 present; + __u8 pad03[5]; + } v0; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0012.h b/drivers/gpu/drm/nouveau/include/nvif/if0012.h new file mode 100644 index 000000000000..243bd35d942f --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/if0012.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef __NVIF_IF0012_H__ +#define __NVIF_IF0012_H__ + +union nvif_outp_args { + struct nvif_outp_v0 { + __u8 version; + __u8 id; /* DCB device index. */ + __u8 pad02[6]; + } v0; +}; + +#define NVIF_OUTP_V0_LOAD_DETECT 0x00 + +union nvif_outp_load_detect_args { + struct nvif_outp_load_detect_v0 { + __u8 version; + __u8 load; + __u8 pad02[2]; + __u32 data; /*TODO: move vbios loadval parsing into nvkm */ + } v0; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0014.h b/drivers/gpu/drm/nouveau/include/nvif/if0014.h new file mode 100644 index 000000000000..be0362805106 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/if0014.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef __NVIF_IF0014_H__ +#define __NVIF_IF0014_H__ + +union nvif_disp_chan_args { + struct nvif_disp_chan_v0 { + __u8 version; + __u8 id; + __u8 pad02[6]; + __u64 pushbuf; + } v0; +}; +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/outp.h b/drivers/gpu/drm/nouveau/include/nvif/outp.h new file mode 100644 index 000000000000..0d6aa07a9184 --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvif/outp.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef __NVIF_OUTP_H__ +#define __NVIF_OUTP_H__ +#include <nvif/object.h> +struct nvif_disp; + +struct nvif_outp { + struct nvif_object object; +}; + +int nvif_outp_ctor(struct nvif_disp *, const char *name, int id, struct nvif_outp *); +void nvif_outp_dtor(struct nvif_outp *); +int nvif_outp_load_detect(struct nvif_outp *, u32 loadval); +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvif/printf.h b/drivers/gpu/drm/nouveau/include/nvif/printf.h index 6c299ec6be21..ec524b2faeae 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/printf.h +++ b/drivers/gpu/drm/nouveau/include/nvif/printf.h @@ -17,4 +17,13 @@ #endif #define NVIF_ERROR(o,f,a...) NVIF_PRINT(errorf, (o), f, ##a) +#define NVIF_ERRON(c,o,f,a...) do { \ + struct nvif_object *_object = (o); \ + int _cond = (c); \ + if (_cond) { \ + NVIF_ERROR(_object, f" (ret:%d)", ##a, _cond); \ + } else { \ + NVIF_DEBUG(_object, f, ##a); \ + } \ +} while(0) #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h index d08d3337ba0d..8b5d8a434be8 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h @@ -3,23 +3,56 @@ #define __NVKM_DISP_H__ #define nvkm_disp(p) container_of((p), struct nvkm_disp, engine) #include <core/engine.h> +#include <core/object.h> #include <core/event.h> struct nvkm_disp { const struct nvkm_disp_func *func; struct nvkm_engine engine; - struct list_head head; - struct list_head ior; - struct list_head outp; - struct list_head conn; + struct list_head heads; + struct list_head iors; + struct list_head outps; + struct list_head conns; struct nvkm_event hpd; struct nvkm_event vblank; struct { + struct workqueue_struct *wq; + struct work_struct work; + u32 pending; + struct mutex mutex; + } super; + +#define NVKM_DISP_EVENT_CHAN_AWAKEN BIT(0) + struct nvkm_event uevent; + + struct { + unsigned long mask; + int nr; + } wndw, head, dac; + + struct { + unsigned long mask; + int nr; + u32 lvdsconf; + } sor; + + struct { + unsigned long mask; + int nr; + u8 type[3]; + } pior; + + struct nvkm_gpuobj *inst; + struct nvkm_ramht *ramht; + + struct nvkm_disp_chan *chan[81]; + + struct { spinlock_t lock; - struct nvkm_oproxy *object; + struct nvkm_object object; } client; }; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h index a27a0f3fe7aa..73f9d9947e7e 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/dcb.h @@ -54,6 +54,7 @@ struct dcb_output { } tmdsconf; }; bool i2c_upper_default; + int id; }; u16 dcb_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *ent, u8 *len); |