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Diffstat (limited to 'drivers/gpu/drm/vmwgfx')
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.c224
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_drv.h3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_kms.c10
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c5
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c4
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c5
8 files changed, 151 insertions, 106 deletions
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c b/drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c
index 30a837b5baa6..67db472d3493 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cmd.c
@@ -140,7 +140,8 @@ struct vmw_fifo_state *vmw_fifo_create(struct vmw_private *dev_priv)
min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN);
fifo->capabilities = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_CAPABILITIES);
- DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
+ drm_info(&dev_priv->drm,
+ "Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
(unsigned int) max,
(unsigned int) min,
(unsigned int) fifo->capabilities);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c
index 9656d4a2abff..81b84570da0a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c
@@ -1272,7 +1272,8 @@ int vmw_cmdbuf_set_pool_size(struct vmw_cmdbuf_man *man, size_t size)
* submissions to be able to free up space.
*/
man->default_size = VMW_CMDBUF_INLINE_SIZE;
- DRM_INFO("Using command buffers with %s pool.\n",
+ drm_info(&dev_priv->drm,
+ "Using command buffers with %s pool.\n",
(man->using_mob) ? "MOB" : "DMA");
return 0;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 05d6705aa46a..049ea3b8229b 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -286,62 +286,92 @@ MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
-static void vmw_print_capabilities2(uint32_t capabilities2)
+struct bitmap_name {
+ uint32 value;
+ const char *name;
+};
+
+static const struct bitmap_name cap1_names[] = {
+ { SVGA_CAP_RECT_COPY, "rect copy" },
+ { SVGA_CAP_CURSOR, "cursor" },
+ { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" },
+ { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" },
+ { SVGA_CAP_8BIT_EMULATION, "8bit emulation" },
+ { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" },
+ { SVGA_CAP_3D, "3D" },
+ { SVGA_CAP_EXTENDED_FIFO, "extended fifo" },
+ { SVGA_CAP_MULTIMON, "multimon" },
+ { SVGA_CAP_PITCHLOCK, "pitchlock" },
+ { SVGA_CAP_IRQMASK, "irq mask" },
+ { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" },
+ { SVGA_CAP_GMR, "gmr" },
+ { SVGA_CAP_TRACES, "traces" },
+ { SVGA_CAP_GMR2, "gmr2" },
+ { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" },
+ { SVGA_CAP_COMMAND_BUFFERS, "command buffers" },
+ { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" },
+ { SVGA_CAP_GBOBJECTS, "gbobject" },
+ { SVGA_CAP_DX, "dx" },
+ { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" },
+ { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" },
+ { SVGA_CAP_CAP2_REGISTER, "cap2 register" },
+};
+
+
+static const struct bitmap_name cap2_names[] = {
+ { SVGA_CAP2_GROW_OTABLE, "grow otable" },
+ { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" },
+ { SVGA_CAP2_DX2, "dx2" },
+ { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" },
+ { SVGA_CAP2_SCREENDMA_REG, "screendma reg" },
+ { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" },
+ { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" },
+ { SVGA_CAP2_CURSOR_MOB, "cursor mob" },
+ { SVGA_CAP2_MSHINT, "mshint" },
+ { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" },
+ { SVGA_CAP2_DX3, "dx3" },
+ { SVGA_CAP2_FRAME_TYPE, "frame type" },
+ { SVGA_CAP2_COTABLE_COPY, "cotable copy" },
+ { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" },
+ { SVGA_CAP2_EXTRA_REGS, "extra regs" },
+ { SVGA_CAP2_LO_STAGING, "lo staging" },
+};
+
+static void vmw_print_bitmap(struct drm_device *drm,
+ const char *prefix, uint32_t bitmap,
+ const struct bitmap_name *bnames,
+ uint32_t num_names)
{
- DRM_INFO("Capabilities2:\n");
- if (capabilities2 & SVGA_CAP2_GROW_OTABLE)
- DRM_INFO(" Grow oTable.\n");
- if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY)
- DRM_INFO(" IntraSurface copy.\n");
- if (capabilities2 & SVGA_CAP2_DX3)
- DRM_INFO(" DX3.\n");
+ char buf[512];
+ uint32_t i;
+ uint32_t offset = 0;
+ for (i = 0; i < num_names; ++i) {
+ if ((bitmap & bnames[i].value) != 0) {
+ offset += snprintf(buf + offset,
+ ARRAY_SIZE(buf) - offset,
+ "%s, ", bnames[i].name);
+ bitmap &= ~bnames[i].value;
+ }
+ }
+
+ drm_info(drm, "%s: %s\n", prefix, buf);
+ if (bitmap != 0)
+ drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap);
}
-static void vmw_print_capabilities(uint32_t capabilities)
+
+static void vmw_print_sm_type(struct vmw_private *dev_priv)
{
- DRM_INFO("Capabilities:\n");
- if (capabilities & SVGA_CAP_RECT_COPY)
- DRM_INFO(" Rect copy.\n");
- if (capabilities & SVGA_CAP_CURSOR)
- DRM_INFO(" Cursor.\n");
- if (capabilities & SVGA_CAP_CURSOR_BYPASS)
- DRM_INFO(" Cursor bypass.\n");
- if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
- DRM_INFO(" Cursor bypass 2.\n");
- if (capabilities & SVGA_CAP_8BIT_EMULATION)
- DRM_INFO(" 8bit emulation.\n");
- if (capabilities & SVGA_CAP_ALPHA_CURSOR)
- DRM_INFO(" Alpha cursor.\n");
- if (capabilities & SVGA_CAP_3D)
- DRM_INFO(" 3D.\n");
- if (capabilities & SVGA_CAP_EXTENDED_FIFO)
- DRM_INFO(" Extended Fifo.\n");
- if (capabilities & SVGA_CAP_MULTIMON)
- DRM_INFO(" Multimon.\n");
- if (capabilities & SVGA_CAP_PITCHLOCK)
- DRM_INFO(" Pitchlock.\n");
- if (capabilities & SVGA_CAP_IRQMASK)
- DRM_INFO(" Irq mask.\n");
- if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
- DRM_INFO(" Display Topology.\n");
- if (capabilities & SVGA_CAP_GMR)
- DRM_INFO(" GMR.\n");
- if (capabilities & SVGA_CAP_TRACES)
- DRM_INFO(" Traces.\n");
- if (capabilities & SVGA_CAP_GMR2)
- DRM_INFO(" GMR2.\n");
- if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
- DRM_INFO(" Screen Object 2.\n");
- if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
- DRM_INFO(" Command Buffers.\n");
- if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
- DRM_INFO(" Command Buffers 2.\n");
- if (capabilities & SVGA_CAP_GBOBJECTS)
- DRM_INFO(" Guest Backed Resources.\n");
- if (capabilities & SVGA_CAP_DX)
- DRM_INFO(" DX Features.\n");
- if (capabilities & SVGA_CAP_HP_CMD_QUEUE)
- DRM_INFO(" HP Command Queue.\n");
+ static const char *names[] = {
+ [VMW_SM_LEGACY] = "Legacy",
+ [VMW_SM_4] = "SM4",
+ [VMW_SM_4_1] = "SM4_1",
+ [VMW_SM_5] = "SM_5",
+ [VMW_SM_MAX] = "Invalid"
+ };
+ BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1));
+ drm_info(&dev_priv->drm, "Available shader model: %s.\n",
+ names[dev_priv->sm_type]);
}
/**
@@ -408,10 +438,6 @@ static int vmw_device_init(struct vmw_private *dev_priv)
{
bool uses_fb_traces = false;
- DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
- DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
- DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
-
dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
@@ -650,7 +676,8 @@ static int vmw_dma_select_mode(struct vmw_private *dev_priv)
else
dev_priv->map_mode = vmw_dma_map_populate;
- DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
+ drm_info(&dev_priv->drm,
+ "DMA map mode: %s\n", names[dev_priv->map_mode]);
return 0;
}
@@ -669,7 +696,8 @@ static int vmw_dma_masks(struct vmw_private *dev_priv)
ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64));
if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) {
- DRM_INFO("Restricting DMA addresses to 44 bits.\n");
+ drm_info(&dev_priv->drm,
+ "Restricting DMA addresses to 44 bits.\n");
return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44));
}
@@ -721,13 +749,15 @@ static int vmw_setup_pci_resources(struct vmw_private *dev,
dev->vram_start = pci_resource_start(pdev, 2);
dev->vram_size = pci_resource_len(pdev, 2);
- DRM_INFO("Register MMIO at 0x%pa size is %llu kiB\n",
+ drm_info(&dev->drm,
+ "Register MMIO at 0x%pa size is %llu kiB\n",
&rmmio_start, (uint64_t)rmmio_size / 1024);
dev->rmmio = devm_ioremap(dev->drm.dev,
rmmio_start,
rmmio_size);
if (!dev->rmmio) {
- DRM_ERROR("Failed mapping registers mmio memory.\n");
+ drm_err(&dev->drm,
+ "Failed mapping registers mmio memory.\n");
pci_release_regions(pdev);
return -ENOMEM;
}
@@ -738,7 +768,8 @@ static int vmw_setup_pci_resources(struct vmw_private *dev,
fifo_start = pci_resource_start(pdev, 2);
fifo_size = pci_resource_len(pdev, 2);
- DRM_INFO("FIFO at %pa size is %llu kiB\n",
+ drm_info(&dev->drm,
+ "FIFO at %pa size is %llu kiB\n",
&fifo_start, (uint64_t)fifo_size / 1024);
dev->fifo_mem = devm_memremap(dev->drm.dev,
fifo_start,
@@ -746,7 +777,8 @@ static int vmw_setup_pci_resources(struct vmw_private *dev,
MEMREMAP_WB);
if (IS_ERR(dev->fifo_mem)) {
- DRM_ERROR("Failed mapping FIFO memory.\n");
+ drm_err(&dev->drm,
+ "Failed mapping FIFO memory.\n");
pci_release_regions(pdev);
return PTR_ERR(dev->fifo_mem);
}
@@ -761,7 +793,8 @@ static int vmw_setup_pci_resources(struct vmw_private *dev,
* size will be equal to or bigger than the size reported by
* SVGA_REG_VRAM_SIZE.
*/
- DRM_INFO("VRAM at %pa size is %llu kiB\n",
+ drm_info(&dev->drm,
+ "VRAM at %pa size is %llu kiB\n",
&dev->vram_start, (uint64_t)dev->vram_size / 1024);
return 0;
@@ -775,12 +808,14 @@ static int vmw_detect_version(struct vmw_private *dev)
SVGA_ID_3 : SVGA_ID_2);
svga_id = vmw_read(dev, SVGA_REG_ID);
if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) {
- DRM_ERROR("Unsupported SVGA ID 0x%x on chipset 0x%x\n",
- svga_id, dev->pci_id);
+ drm_err(&dev->drm,
+ "Unsupported SVGA ID 0x%x on chipset 0x%x\n",
+ svga_id, dev->pci_id);
return -ENOSYS;
}
BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3));
- DRM_INFO("Running on SVGA version %d.\n", (svga_id & 0xff));
+ drm_info(&dev->drm,
+ "Running on SVGA version %d.\n", (svga_id & 0xff));
return 0;
}
@@ -834,10 +869,12 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
ret = vmw_dma_select_mode(dev_priv);
if (unlikely(ret != 0)) {
- DRM_INFO("Restricting capabilities since DMA not available.\n");
+ drm_info(&dev_priv->drm,
+ "Restricting capabilities since DMA not available.\n");
refuse_dma = true;
if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS)
- DRM_INFO("Disabling 3D acceleration.\n");
+ drm_info(&dev_priv->drm,
+ "Disabling 3D acceleration.\n");
}
dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
@@ -906,11 +943,13 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
dev_priv->max_primary_mem = dev_priv->vram_size;
}
- vmw_print_capabilities(dev_priv->capabilities);
+ vmw_print_bitmap(&dev_priv->drm, "Capabilities",
+ dev_priv->capabilities,
+ cap1_names, ARRAY_SIZE(cap1_names));
if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER)
- vmw_print_capabilities2(dev_priv->capabilities2);
- DRM_INFO("Supports command queues = %d\n",
- vmw_cmd_supported((dev_priv)));
+ vmw_print_bitmap(&dev_priv->drm, "Capabilities2",
+ dev_priv->capabilities2,
+ cap2_names, ARRAY_SIZE(cap2_names));
ret = vmw_dma_masks(dev_priv);
if (unlikely(ret != 0))
@@ -919,14 +958,15 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX);
if (dev_priv->capabilities & SVGA_CAP_GMR2) {
- DRM_INFO("Max GMR ids is %u\n",
+ drm_info(&dev_priv->drm,
+ "Max GMR ids is %u\n",
(unsigned)dev_priv->max_gmr_ids);
- DRM_INFO("Max number of GMR pages is %u\n",
+ drm_info(&dev_priv->drm,
+ "Max number of GMR pages is %u\n",
(unsigned)dev_priv->max_gmr_pages);
- DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
- (unsigned)dev_priv->memory_size / 1024);
}
- DRM_INFO("Maximum display memory size is %llu kiB\n",
+ drm_info(&dev_priv->drm,
+ "Maximum display memory size is %llu kiB\n",
(uint64_t)dev_priv->max_primary_mem / 1024);
/* Need mmio memory to check for fifo pitchlock cap. */
@@ -942,7 +982,8 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
&vmw_prime_dmabuf_ops);
if (unlikely(dev_priv->tdev == NULL)) {
- DRM_ERROR("Unable to initialize TTM object management.\n");
+ drm_err(&dev_priv->drm,
+ "Unable to initialize TTM object management.\n");
ret = -ENOMEM;
goto out_err0;
}
@@ -950,7 +991,8 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
ret = vmw_irq_install(&dev_priv->drm, pdev->irq);
if (ret != 0) {
- DRM_ERROR("Failed installing irq: %d\n", ret);
+ drm_err(&dev_priv->drm,
+ "Failed installing irq: %d\n", ret);
goto out_no_irq;
}
}
@@ -971,7 +1013,8 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
dev_priv->map_mode == vmw_dma_alloc_coherent,
false);
if (unlikely(ret != 0)) {
- DRM_ERROR("Failed initializing TTM buffer object driver.\n");
+ drm_err(&dev_priv->drm,
+ "Failed initializing TTM buffer object driver.\n");
goto out_no_bdev;
}
@@ -982,13 +1025,15 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
ret = vmw_vram_manager_init(dev_priv);
if (unlikely(ret != 0)) {
- DRM_ERROR("Failed initializing memory manager for VRAM.\n");
+ drm_err(&dev_priv->drm,
+ "Failed initializing memory manager for VRAM.\n");
goto out_no_vram;
}
ret = vmw_devcaps_create(dev_priv);
if (unlikely(ret != 0)) {
- DRM_ERROR("Failed initializing device caps.\n");
+ drm_err(&dev_priv->drm,
+ "Failed initializing device caps.\n");
goto out_no_vram;
}
@@ -1002,7 +1047,8 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
refuse_dma ||
vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) {
- DRM_INFO("No GMR memory available. "
+ drm_info(&dev_priv->drm,
+ "No GMR memory available. "
"Graphics memory resources are very limited.\n");
dev_priv->has_gmr = false;
}
@@ -1011,7 +1057,8 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
dev_priv->has_mob = true;
if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) {
- DRM_INFO("No MOB memory available. "
+ drm_info(&dev_priv->drm,
+ "No MOB memory available. "
"3D will be disabled.\n");
dev_priv->has_mob = false;
}
@@ -1045,14 +1092,7 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
if (ret)
goto out_no_fifo;
- if (dev_priv->sm_type == VMW_SM_5)
- DRM_INFO("SM5 support available.\n");
- if (dev_priv->sm_type == VMW_SM_4_1)
- DRM_INFO("SM4_1 support available.\n");
- if (dev_priv->sm_type == VMW_SM_4)
- DRM_INFO("SM4 support available.\n");
- DRM_INFO("Running without reservation semaphore\n");
-
+ vmw_print_sm_type(dev_priv);
vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)",
VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
index 356f82c26f59..375b01cccd1a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
@@ -367,7 +367,8 @@ enum vmw_display_unit_type {
vmw_du_invalid = 0,
vmw_du_legacy,
vmw_du_screen_object,
- vmw_du_screen_target
+ vmw_du_screen_target,
+ vmw_du_max
};
struct vmw_validation_context;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 2ddf4932d62c..338c6e2613ea 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -1793,6 +1793,13 @@ int vmw_kms_init(struct vmw_private *dev_priv)
{
struct drm_device *dev = &dev_priv->drm;
int ret;
+ static const char *display_unit_names[] = {
+ "Invalid",
+ "Legacy",
+ "Screen Object",
+ "Screen Target",
+ "Invalid (max)"
+ };
drm_mode_config_init(dev);
dev->mode_config.funcs = &vmw_kms_funcs;
@@ -1810,6 +1817,9 @@ int vmw_kms_init(struct vmw_private *dev_priv)
if (ret) /* Fallback */
ret = vmw_kms_ldu_init_display(dev_priv);
}
+ BUILD_BUG_ON(ARRAY_SIZE(display_unit_names) != (vmw_du_max + 1));
+ drm_info(&dev_priv->drm, "%s display unit initialized\n",
+ display_unit_names[dev_priv->active_display_unit]);
return ret;
}
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
index d85c7eab9469..fb58a71c458f 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
@@ -493,8 +493,7 @@ int vmw_kms_ldu_init_display(struct vmw_private *dev_priv)
struct drm_device *dev = &dev_priv->drm;
int i, ret;
- if (dev_priv->ldu_priv) {
- DRM_INFO("ldu system already on\n");
+ if (unlikely(dev_priv->ldu_priv)) {
return -EINVAL;
}
@@ -527,8 +526,6 @@ int vmw_kms_ldu_init_display(struct vmw_private *dev_priv)
drm_mode_config_reset(dev);
- DRM_INFO("Legacy Display Unit initialized\n");
-
return 0;
err_free:
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
index 145430d14219..bd157fb21b45 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c
@@ -954,8 +954,6 @@ int vmw_kms_sou_init_display(struct vmw_private *dev_priv)
int i, ret;
if (!(dev_priv->capabilities & SVGA_CAP_SCREEN_OBJECT_2)) {
- DRM_INFO("Not using screen objects,"
- " missing cap SCREEN_OBJECT_2\n");
return -ENOSYS;
}
@@ -972,8 +970,6 @@ int vmw_kms_sou_init_display(struct vmw_private *dev_priv)
drm_mode_config_reset(dev);
- DRM_INFO("Screen Objects Display Unit initialized\n");
-
return 0;
}
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
index 365ed93dd3e8..d85310b2608d 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
@@ -1889,14 +1889,13 @@ int vmw_kms_stdu_init_display(struct vmw_private *dev_priv)
ret = vmw_stdu_init(dev_priv, i);
if (unlikely(ret != 0)) {
- DRM_ERROR("Failed to initialize STDU %d", i);
+ drm_err(&dev_priv->drm,
+ "Failed to initialize STDU %d", i);
return ret;
}
}
drm_mode_config_reset(dev);
- DRM_INFO("Screen Target Display device initialized\n");
-
return 0;
}
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-10 13:09:32 +0300