diff options
Diffstat (limited to 'drivers/gpu')
202 files changed, 6744 insertions, 723 deletions
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index ab9ef1c20349..3caa020391c7 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -136,7 +136,7 @@ config DRM_FBDEV_EMULATION bool "Enable legacy fbdev support for your modesetting driver" depends on DRM select FRAMEBUFFER_CONSOLE_DETECT_PRIMARY if FRAMEBUFFER_CONSOLE - default y + default FB help Choose this option if you have a need for the legacy fbdev support. Note that this support also provides the linux console diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index dc2d53081e80..a79d53bdbe13 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1293,7 +1293,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); int amdgpu_device_pci_reset(struct amdgpu_device *adev); bool amdgpu_device_need_post(struct amdgpu_device *adev); -bool amdgpu_sg_display_supported(struct amdgpu_device *adev); bool amdgpu_device_pcie_dynamic_switching_supported(void); bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); bool amdgpu_device_aspm_support_quirk(void); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index df633e9ce920..25d5fda5b243 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -442,9 +442,7 @@ void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, mem_info->local_mem_size_public, mem_info->local_mem_size_private); - if (amdgpu_sriov_vf(adev)) - mem_info->mem_clk_max = adev->clock.default_mclk / 100; - else if (adev->pm.dpm_enabled) { + if (adev->pm.dpm_enabled) { if (amdgpu_emu_mode == 1) mem_info->mem_clk_max = 0; else @@ -463,9 +461,7 @@ uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev) uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev) { /* the sclk is in quantas of 10kHz */ - if (amdgpu_sriov_vf(adev)) - return adev->clock.default_sclk / 100; - else if (adev->pm.dpm_enabled) + if (adev->pm.dpm_enabled) return amdgpu_dpm_get_sclk(adev, false) / 100; else return 100; @@ -482,7 +478,7 @@ void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev, struct kfd_cu_info *c cu_info->cu_active_number = acu_info.number; cu_info->cu_ao_mask = acu_info.ao_cu_mask; memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0], - sizeof(acu_info.bitmap)); + sizeof(cu_info->cu_bitmap)); cu_info->num_shader_engines = adev->gfx.config.max_shader_engines; cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c index f1f2c24de081..69810b3f1c63 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c @@ -980,8 +980,7 @@ void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev, uint32_t wait_times, uint32_t grace_period, uint32_t *reg_offset, - uint32_t *reg_data, - uint32_t inst) + uint32_t *reg_data) { *reg_data = wait_times; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h index ecaead24e8c9..67bcaa3d4226 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.h @@ -55,5 +55,4 @@ void kgd_gfx_v10_build_grace_period_packet_info(struct amdgpu_device *adev, uint32_t wait_times, uint32_t grace_period, uint32_t *reg_offset, - uint32_t *reg_data, - uint32_t inst); + uint32_t *reg_data); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index fa5ee96f8845..3c45a188b701 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1103,8 +1103,7 @@ void kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev, uint32_t wait_times, uint32_t grace_period, uint32_t *reg_offset, - uint32_t *reg_data, - uint32_t inst) + uint32_t *reg_data) { *reg_data = wait_times; @@ -1120,8 +1119,7 @@ void kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev, SCH_WAVE, grace_period); - *reg_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), - mmCP_IQ_WAIT_TIME2); + *reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2); } void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h index 936e501908ce..ce424615f59b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h @@ -100,5 +100,4 @@ void kgd_gfx_v9_build_grace_period_packet_info(struct amdgpu_device *adev, uint32_t wait_times, uint32_t grace_period, uint32_t *reg_offset, - uint32_t *reg_data, - uint32_t inst); + uint32_t *reg_data); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 73ee14f7a9a4..dce9e7d5e4ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1776,7 +1776,7 @@ static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev, struct amdgpu_device *adev = drm_to_adev(ddev); struct atom_context *ctx = adev->mode_info.atom_context; - return sysfs_emit(buf, "%s\n", ctx->vbios_ver_str); + return sysfs_emit(buf, "%s\n", ctx->vbios_pn); } static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c index 835980e94b9e..fb2681dd6b33 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c @@ -217,6 +217,7 @@ union umc_info { struct atom_umc_info_v3_1 v31; struct atom_umc_info_v3_2 v32; struct atom_umc_info_v3_3 v33; + struct atom_umc_info_v4_0 v40; }; union vram_info { @@ -508,9 +509,8 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev) if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, &frev, &crev, &data_offset)) { + umc_info = (union umc_info *)(mode_info->atom_context->bios + data_offset); if (frev == 3) { - umc_info = (union umc_info *) - (mode_info->atom_context->bios + data_offset); switch (crev) { case 1: umc_config = le32_to_cpu(umc_info->v31.umc_config); @@ -533,6 +533,20 @@ bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev) /* unsupported crev */ return false; } + } else if (frev == 4) { + switch (crev) { + case 0: + umc_config1 = le32_to_cpu(umc_info->v40.umc_config1); + ecc_default_enabled = + (umc_config1 & UMC_CONFIG1__ENABLE_ECC_CAPABLE) ? true : false; + break; + default: + /* unsupported crev */ + return false; + } + } else { + /* unsupported frev */ + return false; } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 49dd9aa8da70..efdb1c48f431 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -127,7 +127,6 @@ static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p, { struct drm_gem_object *gobj; unsigned long size; - int r; gobj = drm_gem_object_lookup(p->filp, data->handle); if (gobj == NULL) @@ -137,23 +136,14 @@ static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p, drm_gem_object_put(gobj); size = amdgpu_bo_size(p->uf_bo); - if (size != PAGE_SIZE || (data->offset + 8) > size) { - r = -EINVAL; - goto error_unref; - } + if (size != PAGE_SIZE || data->offset > (size - 8)) + return -EINVAL; - if (amdgpu_ttm_tt_get_usermm(p->uf_bo->tbo.ttm)) { - r = -EINVAL; - goto error_unref; - } + if (amdgpu_ttm_tt_get_usermm(p->uf_bo->tbo.ttm)) + return -EINVAL; *offset = data->offset; - return 0; - -error_unref: - amdgpu_bo_unref(&p->uf_bo); - return r; } static int amdgpu_cs_p1_bo_handles(struct amdgpu_cs_parser *p, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index e77f048c99d8..2b8356699f23 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -885,13 +885,20 @@ static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev, */ static int amdgpu_device_asic_init(struct amdgpu_device *adev) { + int ret; + amdgpu_asic_pre_asic_init(adev); if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) || - adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) - return amdgpu_atomfirmware_asic_init(adev, true); - else + adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) { + amdgpu_psp_wait_for_bootloader(adev); + ret = amdgpu_atomfirmware_asic_init(adev, true); + return ret; + } else { return amdgpu_atom_asic_init(adev->mode_info.atom_context); + } + + return 0; } /** @@ -1238,32 +1245,6 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev) } /* - * On APUs with >= 64GB white flickering has been observed w/ SG enabled. - * Disable S/G on such systems until we have a proper fix. - * https://gitlab.freedesktop.org/drm/amd/-/issues/2354 - * https://gitlab.freedesktop.org/drm/amd/-/issues/2735 - */ -bool amdgpu_sg_display_supported(struct amdgpu_device *adev) -{ - switch (amdgpu_sg_display) { - case -1: - break; - case 0: - return false; - case 1: - return true; - default: - return false; - } - if ((totalram_pages() << (PAGE_SHIFT - 10)) + - (adev->gmc.real_vram_size / 1024) >= 64000000) { - DRM_WARN("Disabling S/G due to >=64GB RAM\n"); - return false; - } - return true; -} - -/* * Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic * speed switching. Until we have confirmation from Intel that a specific host * supports it, it's safer that we keep it disabled for all. @@ -2112,7 +2093,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) adev->flags |= AMD_IS_PX; if (!(adev->flags & AMD_IS_APU)) { - parent = pci_upstream_bridge(adev->pdev); + parent = pcie_find_root_port(adev->pdev); adev->has_pr3 = parent ? pci_pr3_present(parent) : false; } @@ -4694,9 +4675,12 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev) } if (ret) - dev_err(adev->dev, "GPU mode1 reset failed\n"); + goto mode1_reset_failed; amdgpu_device_load_pci_state(adev->pdev); + ret = amdgpu_psp_wait_for_bootloader(adev); + if (ret) + goto mode1_reset_failed; /* wait for asic to come out of reset */ for (i = 0; i < adev->usec_timeout; i++) { @@ -4707,7 +4691,17 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev) udelay(1); } + if (i >= adev->usec_timeout) { + ret = -ETIMEDOUT; + goto mode1_reset_failed; + } + amdgpu_atombios_scratch_regs_engine_hung(adev, false); + + return 0; + +mode1_reset_failed: + dev_err(adev->dev, "GPU mode1 reset failed\n"); return ret; } @@ -4849,7 +4843,7 @@ static void amdgpu_reset_capture_coredumpm(struct amdgpu_device *adev) struct drm_device *dev = adev_to_drm(adev); ktime_get_ts64(&adev->reset_time); - dev_coredumpm(dev->dev, THIS_MODULE, adev, 0, GFP_KERNEL, + dev_coredumpm(dev->dev, THIS_MODULE, adev, 0, GFP_NOWAIT, amdgpu_devcoredump_read, amdgpu_devcoredump_free); } #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 74ffe6581c85..7d5e7ad28ba8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1390,6 +1390,7 @@ union gc_info { struct gc_info_v1_1 v1_1; struct gc_info_v1_2 v1_2; struct gc_info_v2_0 v2; + struct gc_info_v2_1 v2_1; }; static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) @@ -1465,6 +1466,15 @@ static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / le32_to_cpu(gc_info->v2.gc_num_sh_per_se); adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); + if (gc_info->v2.header.version_minor == 1) { + adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); + adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); + adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ + adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); + adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); + adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); + adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ + } break; default: dev_err(adev->dev, @@ -1478,6 +1488,7 @@ static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) union mall_info { struct mall_info_v1_0 v1; + struct mall_info_v2_0 v2; }; static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) @@ -1518,6 +1529,10 @@ static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) adev->gmc.mall_size = mall_size; adev->gmc.m_half_use = half_use; break; + case 2: + mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); + adev->gmc.mall_size = mall_size_per_umc * adev->gmc.num_umc; + break; default: dev_err(adev->dev, "Unhandled MALL info table %d.%d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index d20dd3f852fc..363e6a2cad8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -38,6 +38,8 @@ #include <linux/pci.h> #include <linux/pm_runtime.h> #include <drm/drm_crtc_helper.h> +#include <drm/drm_damage_helper.h> +#include <drm/drm_drv.h> #include <drm/drm_edid.h> #include <drm/drm_fb_helper.h> #include <drm/drm_gem_framebuffer_helper.h> @@ -532,11 +534,29 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, return true; } +static int amdgpu_dirtyfb(struct drm_framebuffer *fb, struct drm_file *file, + unsigned int flags, unsigned int color, + struct drm_clip_rect *clips, unsigned int num_clips) +{ + + if (file) + return -ENOSYS; + + return drm_atomic_helper_dirtyfb(fb, file, flags, color, clips, + num_clips); +} + static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { .destroy = drm_gem_fb_destroy, .create_handle = drm_gem_fb_create_handle, }; +static const struct drm_framebuffer_funcs amdgpu_fb_funcs_atomic = { + .destroy = drm_gem_fb_destroy, + .create_handle = drm_gem_fb_create_handle, + .dirty = amdgpu_dirtyfb +}; + uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, uint64_t bo_flags) { @@ -1139,7 +1159,11 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, if (ret) goto err; - ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); + if (drm_drv_uses_atomic_modeset(dev)) + ret = drm_framebuffer_init(dev, &rfb->base, + &amdgpu_fb_funcs_atomic); + else + ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); if (ret) goto err; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c index 9c66d98af6d8..7cd0dfaeee20 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c @@ -170,6 +170,7 @@ int amdgpu_fru_get_product_info(struct amdgpu_device *adev) csum += pia[size - 1]; if (csum) { DRM_ERROR("Bad Product Info Area checksum: 0x%02x", csum); + kfree(pia); return -EIO; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index a4ff515ce896..0ca95c4d4bfb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -43,6 +43,7 @@ #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L #define AMDGPU_MAX_GC_INSTANCES 8 +#define KGD_MAX_QUEUES 128 #define AMDGPU_MAX_GFX_QUEUES KGD_MAX_QUEUES #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES @@ -241,6 +242,9 @@ struct amdgpu_gfx_config { uint32_t gc_gl1c_per_sa; uint32_t gc_gl1c_size_per_instance; uint32_t gc_gl2c_per_gpu; + uint32_t gc_tcp_size_per_cu; + uint32_t gc_num_cu_per_sqc; + uint32_t gc_tcc_size; }; struct amdgpu_cu_info { @@ -254,7 +258,7 @@ struct amdgpu_cu_info { uint32_t number; uint32_t ao_cu_mask; uint32_t ao_cu_bitmap[4][4]; - uint32_t bitmap[4][4]; + uint32_t bitmap[AMDGPU_MAX_GC_INSTANCES][4][4]; }; struct amdgpu_gfx_ras { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 99f4df133ed3..d30dc0b718c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -839,7 +839,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], sizeof(adev->gfx.cu_info.ao_cu_bitmap)); memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], - sizeof(adev->gfx.cu_info.bitmap)); + sizeof(dev_info->cu_bitmap)); dev_info->vram_type = adev->gmc.vram_type; dev_info->vram_bit_width = adev->gmc.vram_width; dev_info->vce_harvest_config = adev->vce.harvest_config; @@ -940,12 +940,17 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) struct atom_context *atom_context; atom_context = adev->mode_info.atom_context; - memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name)); - memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn)); - vbios_info.version = atom_context->version; - memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, - sizeof(atom_context->vbios_ver_str)); - memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date)); + if (atom_context) { + memcpy(vbios_info.name, atom_context->name, + sizeof(atom_context->name)); + memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, + sizeof(atom_context->vbios_pn)); + vbios_info.version = atom_context->version; + memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, + sizeof(atom_context->vbios_ver_str)); + memcpy(vbios_info.date, atom_context->date, + sizeof(atom_context->date)); + } return copy_to_user(out, &vbios_info, min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 8fdca54bb8a1..429ef212c1f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -2078,6 +2078,17 @@ int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) } /* SECUREDISPLAY end */ +int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev) +{ + struct psp_context *psp = &adev->psp; + int ret = 0; + + if (!amdgpu_sriov_vf(adev) && psp->funcs && psp->funcs->wait_for_bootloader != NULL) + ret = psp->funcs->wait_for_bootloader(psp); + + return ret; +} + static int psp_hw_start(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 3384eb94fde0..3e67ed63e638 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -109,6 +109,7 @@ enum psp_reg_prog_id { struct psp_funcs { int (*init_microcode)(struct psp_context *psp); + int (*wait_for_bootloader)(struct psp_context *psp); int (*bootloader_load_kdb)(struct psp_context *psp); int (*bootloader_load_spl)(struct psp_context *psp); int (*bootloader_load_sysdrv)(struct psp_context *psp); @@ -533,4 +534,6 @@ int psp_spatial_partition(struct psp_context *psp, int mode); int is_psp_fw_valid(struct psp_bin_desc bin); +int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 7689395e44fd..163445baa4fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -764,7 +764,7 @@ int amdgpu_ras_feature_enable(struct amdgpu_device *adev, { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); union ta_ras_cmd_input *info; - int ret = 0; + int ret; if (!con) return -EINVAL; @@ -773,7 +773,7 @@ int amdgpu_ras_feature_enable(struct amdgpu_device *adev, if (enable && head->block != AMDGPU_RAS_BLOCK__GFX && !amdgpu_ras_is_feature_allowed(adev, head)) - goto out; + return 0; /* Only enable gfx ras feature from host side */ if (head->block == AMDGPU_RAS_BLOCK__GFX && @@ -801,16 +801,17 @@ int amdgpu_ras_feature_enable(struct amdgpu_device *adev, enable ? "enable":"disable", get_ras_block_str(head), amdgpu_ras_is_poison_mode_supported(adev), ret); - goto out; + kfree(info); + return ret; } + + kfree(info); } /* setup the obj */ __amdgpu_ras_feature_enable(adev, head, enable); -out: - if (head->block == AMDGPU_RAS_BLOCK__GFX) - kfree(info); - return ret; + + return 0; } /* Only used in device probe stage and called only once. */ @@ -1052,7 +1053,8 @@ int amdgpu_ras_query_error_status(struct amdgpu_device *adev, info->ce_count = obj->err_data.ce_count; if (err_data.ce_count) { - if (adev->smuio.funcs && + if (!adev->aid_mask && + adev->smuio.funcs && adev->smuio.funcs->get_socket_id && adev->smuio.funcs->get_die_id) { dev_info(adev->dev, "socket: %d, die: %d " @@ -1072,7 +1074,8 @@ int amdgpu_ras_query_error_status(struct amdgpu_device *adev, } } if (err_data.ue_count) { - if (adev->smuio.funcs && + if (!adev->aid_mask && + adev->smuio.funcs && adev->smuio.funcs->get_socket_id && adev->smuio.funcs->get_die_id) { dev_info(adev->dev, "socket: %d, die: %d " @@ -2399,6 +2402,7 @@ static bool amdgpu_ras_asic_supported(struct amdgpu_device *adev) if (amdgpu_sriov_vf(adev)) { switch (adev->ip_versions[MP0_HWIP][0]) { case IP_VERSION(13, 0, 2): + case IP_VERSION(13, 0, 6): return true; default: return false; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index 4764d2171f92..595d5e535aca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -158,9 +158,10 @@ static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) case IP_VERSION(11, 0, 7): /* Sienna cichlid */ case IP_VERSION(13, 0, 0): case IP_VERSION(13, 0, 2): /* Aldebaran */ - case IP_VERSION(13, 0, 6): case IP_VERSION(13, 0, 10): return true; + case IP_VERSION(13, 0, 6): + return (adev->gmc.is_app_apu) ? false : true; default: return false; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c index c6b4337eb20c..10df731998b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c @@ -81,7 +81,7 @@ int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, unsigned int size) { struct drm_suballoc *sa = drm_suballoc_new(&sa_manager->base, size, - GFP_KERNEL, true, 0); + GFP_KERNEL, false, 0); if (IS_ERR(sa)) { *sa_bo = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 0aee9c8288a2..9032d7a24d7c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -9449,7 +9449,7 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( adev, disable_masks[i * 2 + j]); bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); - cu_info->bitmap[i][j] = bitmap; + cu_info->bitmap[0][i][j] = bitmap; for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { if (bitmap & mask) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 5c3db694afa8..762d7a19f1be 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6368,7 +6368,7 @@ static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev, * SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]} * SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]} */ - cu_info->bitmap[i % 4][j + (i / 4) * 2] = bitmap; + cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap; for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { if (bitmap & mask) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index da6caff78c22..34f9211b2679 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3577,7 +3577,7 @@ static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev) gfx_v6_0_set_user_cu_inactive_bitmap( adev, disable_masks[i * 2 + j]); bitmap = gfx_v6_0_get_cu_enabled(adev); - cu_info->bitmap[i][j] = bitmap; + cu_info->bitmap[0][i][j] = bitmap; for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { if (bitmap & mask) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 90b034b173c1..c2faf6b4c2fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -5119,7 +5119,7 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev) gfx_v7_0_set_user_cu_inactive_bitmap( adev, disable_masks[i * 2 + j]); bitmap = gfx_v7_0_get_cu_active_bitmap(adev); - cu_info->bitmap[i][j] = bitmap; + cu_info->bitmap[0][i][j] = bitmap; for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { if (bitmap & mask) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 51c1745c8369..885ebd703260 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -7121,7 +7121,7 @@ static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev) gfx_v8_0_set_user_cu_inactive_bitmap( adev, disable_masks[i * 2 + j]); bitmap = gfx_v8_0_get_cu_active_bitmap(adev); - cu_info->bitmap[i][j] = bitmap; + cu_info->bitmap[0][i][j] = bitmap; for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { if (bitmap & mask) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 458faf657042..fd61574a737c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1499,7 +1499,7 @@ static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { - if (cu_info->bitmap[i][j] & mask) { + if (cu_info->bitmap[0][i][j] & mask) { if (counter == pg_always_on_cu_num) WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap); if (counter < always_on_cu_num) @@ -7233,7 +7233,7 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, * SE6,SH0 --> bitmap[2][1] * SE7,SH0 --> bitmap[3][1] */ - cu_info->bitmap[i % 4][j + i / 4] = bitmap; + cu_info->bitmap[0][i % 4][j + i / 4] = bitmap; for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { if (bitmap & mask) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 57ed4e5c294c..18ce5fe45f6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -203,6 +203,9 @@ static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev) if (adev->rev_id == 0) { WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1, REDUCE_FIFO_DEPTH_BY_2, 2); + } else { + WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2, + SPARE, 0x1); } } } @@ -860,11 +863,15 @@ static int gfx_v9_4_3_sw_init(void *handle) if (r) return r; - r = amdgpu_gfx_sysfs_init(adev); + r = amdgpu_gfx_ras_sw_init(adev); if (r) return r; - return amdgpu_gfx_ras_sw_init(adev); + + if (!amdgpu_sriov_vf(adev)) + r = amdgpu_gfx_sysfs_init(adev); + + return r; } static int gfx_v9_4_3_sw_fini(void *handle) @@ -885,7 +892,8 @@ static int gfx_v9_4_3_sw_fini(void *handle) gfx_v9_4_3_mec_fini(adev); amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); gfx_v9_4_3_free_microcode(adev); - amdgpu_gfx_sysfs_fini(adev); + if (!amdgpu_sriov_vf(adev)) + amdgpu_gfx_sysfs_fini(adev); return 0; } @@ -2219,15 +2227,6 @@ static void gfx_v9_4_3_xcc_update_sram_fgcg(struct amdgpu_device *adev, WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); - def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL); - - if (enable) - data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; - else - data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; - - if (def != data) - WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CLK_CNTL, data); } static void gfx_v9_4_3_xcc_update_repeater_fgcg(struct amdgpu_device *adev, @@ -4048,7 +4047,8 @@ static void gfx_v9_4_3_inst_enable_watchdog_timer(struct amdgpu_device *adev, uint32_t i; uint32_t data; - data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, + data = RREG32_SOC15(GC, GET_INST(GC, 0), regSQ_TIMEOUT_CONFIG); + data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE, amdgpu_watchdog_timer.timeout_fatal_disable ? 1 : 0); if (amdgpu_watchdog_timer.timeout_fatal_disable && @@ -4259,7 +4259,7 @@ static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev) } static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, - u32 bitmap) + u32 bitmap, int xcc_id) { u32 data; @@ -4269,15 +4269,15 @@ static void gfx_v9_4_3_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; - WREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG, data); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); } -static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev) +static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_id) { u32 data, mask; - data = RREG32_SOC15(GC, GET_INST(GC, 0), regCC_GC_SHADER_ARRAY_CONFIG); - data |= RREG32_SOC15(GC, GET_INST(GC, 0), regGC_USER_SHADER_ARRAY_CONFIG); + data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); + data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; @@ -4290,7 +4290,7 @@ static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev) static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info) { - int i, j, k, counter, active_cu_number = 0; + int i, j, k, counter, xcc_id, active_cu_number = 0; u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; unsigned disable_masks[4 * 4]; @@ -4309,46 +4309,38 @@ static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, adev->gfx.config.max_sh_per_se); mutex_lock(&adev->grbm_idx_mutex); - for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { - for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { - mask = 1; - ao_bitmap = 0; - counter = 0; - gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, 0); - gfx_v9_4_3_set_user_cu_inactive_bitmap( - adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); - bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev); - - /* - * The bitmap(and ao_cu_bitmap) in cu_info structure is - * 4x4 size array, and it's usually suitable for Vega - * ASICs which has 4*2 SE/SH layout. - * But for Arcturus, SE/SH layout is changed to 8*1. - * To mostly reduce the impact, we make it compatible - * with current bitmap array as below: - * SE4,SH0 --> bitmap[0][1] - * SE5,SH0 --> bitmap[1][1] - * SE6,SH0 --> bitmap[2][1] - * SE7,SH0 --> bitmap[3][1] - */ - cu_info->bitmap[i % 4][j + i / 4] = bitmap; - - for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { - if (bitmap & mask) { - if (counter < adev->gfx.config.max_cu_per_sh) - ao_bitmap |= mask; - counter++; + for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + mask = 1; + ao_bitmap = 0; + counter = 0; + gfx_v9_4_3_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); + gfx_v9_4_3_set_user_cu_inactive_bitmap( + adev, + disable_masks[i * adev->gfx.config.max_sh_per_se + j], + xcc_id); + bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev, xcc_id); + + cu_info->bitmap[xcc_id][i][j] = bitmap; + + for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { + if (bitmap & mask) { + if (counter < adev->gfx.config.max_cu_per_sh) + ao_bitmap |= mask; + counter++; + } + mask <<= 1; } - mask <<= 1; + active_cu_number += counter; + if (i < 2 && j < 2) + ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); + cu_info->ao_cu_bitmap[i][j] = ao_bitmap; } - active_cu_number += counter; - if (i < 2 && j < 2) - ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); - cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; } + gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, + xcc_id); } - gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, - 0); mutex_unlock(&adev->grbm_idx_mutex); cu_info->number = active_cu_number; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index 15612915bb6c..1de79d660285 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -360,8 +360,10 @@ static int jpeg_v4_0_3_hw_fini(void *handle) cancel_delayed_work_sync(&adev->jpeg.idle_work); - if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) - ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE); + if (!amdgpu_sriov_vf(adev)) { + if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) + ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE); + } return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c index d5ed9e0e1a5f..e5b5b0f4940f 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c @@ -345,6 +345,9 @@ static void nbio_v4_3_init_registers(struct amdgpu_device *adev) data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK; WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data); } + if (amdgpu_sriov_vf(adev)) + adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, + regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; } static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c index 9ea072374cb7..f85eec05d218 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c @@ -437,6 +437,24 @@ static void nbio_v7_9_init_registers(struct amdgpu_device *adev) XCC_DOORBELL_FENCE__SHUB_SLV_MODE_MASK); } + + if (!amdgpu_sriov_vf(adev)) { + u32 baco_cntl; + for_each_inst(i, adev->aid_mask) { + baco_cntl = RREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL); + if (baco_cntl & (BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK | + BIF_BX0_BACO_CNTL__BACO_EN_MASK)) { + baco_cntl &= ~( + BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK | + BIF_BX0_BACO_CNTL__BACO_EN_MASK); + dev_dbg(adev->dev, + "Unsetting baco dummy mode %x", + baco_cntl); + WREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL, + baco_cntl); + } + } + } } static u64 nbio_v7_9_get_pcie_replay_count(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c index 10b17bd5aebe..469eed084976 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c @@ -133,12 +133,32 @@ static bool psp_v13_0_is_sos_alive(struct psp_context *psp) return sol_reg != 0x0; } -static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) +static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; + int retry_loop, ret; - int ret; - int retry_loop; + for (retry_loop = 0; retry_loop < 70; retry_loop++) { + /* Wait for bootloader to signify that is + ready having bit 31 of C2PMSG_33 set to 1 */ + ret = psp_wait_for( + psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33), + 0x80000000, 0xffffffff, false); + + if (ret == 0) + break; + } + + if (ret) + dev_warn(adev->dev, "Bootloader wait timed out"); + + return ret; +} + +static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) +{ + struct amdgpu_device *adev = psp->adev; + int retry_loop, ret; /* Wait for bootloader to signify that it is ready having bit 31 of * C2PMSG_35 set to 1. All other bits are expected to be cleared. @@ -157,6 +177,19 @@ static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) return ret; } +static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp) +{ + struct amdgpu_device *adev = psp->adev; + + if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) { + psp_v13_0_wait_for_vmbx_ready(psp); + + return psp_v13_0_wait_for_bootloader(psp); + } + + return 0; +} + static int psp_v13_0_bootloader_load_component(struct psp_context *psp, struct psp_bin_desc *bin_desc, enum psp_bootloader_cmd bl_cmd) @@ -714,6 +747,7 @@ static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp) static const struct psp_funcs psp_v13_0_funcs = { .init_microcode = psp_v13_0_init_microcode, + .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state, .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, .bootloader_load_spl = psp_v13_0_bootloader_load_spl, .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index c45721ca916e..f5be40d7ba36 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -559,8 +559,10 @@ soc15_asic_reset_method(struct amdgpu_device *adev) */ if (amdgpu_gpu_recovery == 4 || amdgpu_gpu_recovery == 5) return AMD_RESET_METHOD_MODE2; + else if (!(adev->flags & AMD_IS_APU)) + return AMD_RESET_METHOD_MODE1; else - return AMD_RESET_METHOD_NONE; + return AMD_RESET_METHOD_MODE2; default: break; } diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 40d23738ee4e..8b2ff2b281b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -766,7 +766,7 @@ static int soc21_common_hw_init(void *handle) * for the purpose of expose those registers * to process space */ - if (adev->nbio.funcs->remap_hdp_registers) + if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) adev->nbio.funcs->remap_hdp_registers(adev); /* enable the doorbell aperture */ adev->nbio.funcs->enable_doorbell_aperture(adev, true); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index 86fb7ac7982a..f76b7aee5c0a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -2087,7 +2087,8 @@ static int kfd_create_vcrat_image_gpu(void *pcrat_image, amdgpu_amdkfd_get_cu_info(kdev->adev, &cu_info); cu->num_simd_per_cu = cu_info.simd_per_cu; - cu->num_simd_cores = cu_info.simd_per_cu * cu_info.cu_active_number; + cu->num_simd_cores = cu_info.simd_per_cu * + (cu_info.cu_active_number / kdev->kfd->num_nodes); cu->max_waves_simd = cu_info.max_waves_per_simd; cu->wave_front_size = cu_info.wave_front_size; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h index 387a8ef49385..74c2d7a0d628 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h @@ -79,6 +79,10 @@ struct crat_header { #define CRAT_SUBTYPE_IOLINK_AFFINITY 5 #define CRAT_SUBTYPE_MAX 6 +/* + * Do not change the value of CRAT_SIBLINGMAP_SIZE from 32 + * as it breaks the ABI. + */ #define CRAT_SIBLINGMAP_SIZE 32 /* diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index b166f30f083e..0d3d538b64eb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -216,7 +216,7 @@ static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q, if (q->wptr_bo) { wptr_addr_off = (uint64_t)q->properties.write_ptr & (PAGE_SIZE - 1); - queue_input.wptr_mc_addr = ((uint64_t)q->wptr_bo->tbo.resource->start << PAGE_SHIFT) + wptr_addr_off; + queue_input.wptr_mc_addr = amdgpu_bo_gpu_offset(q->wptr_bo) + wptr_addr_off; } queue_input.is_kfd_process = 1; @@ -1677,8 +1677,7 @@ static int start_cpsch(struct device_queue_manager *dqm) dqm->dev->kfd2kgd->build_grace_period_packet_info( dqm->dev->adev, dqm->wait_times, grace_period, ®_offset, - &dqm->wait_times, - ffs(dqm->dev->xcc_mask) - 1); + &dqm->wait_times); } dqm_unlock(dqm); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index c2e0b79dcc6d..7b38537c7c99 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -162,6 +162,7 @@ void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, return NULL; *doorbell_off = amdgpu_doorbell_index_on_bar(kfd->adev, kfd->doorbells, inx); + inx *= 2; pr_debug("Get kernel queue doorbell\n" " doorbell offset == 0x%08X\n" @@ -176,6 +177,7 @@ void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr) unsigned int inx; inx = (unsigned int)(db_addr - kfd->doorbell_kernel_ptr); + inx /= 2; mutex_lock(&kfd->doorbell_mutex); __clear_bit(inx, kfd->doorbell_bitmap); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c index f0731a6a5306..830396b1c3b1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c @@ -384,7 +384,7 @@ static void event_interrupt_wq_v9(struct kfd_node *dev, default: break; } - kfd_signal_event_interrupt(pasid, context_id0 & 0xffffff, 24); + kfd_signal_event_interrupt(pasid, sq_int_data, 24); } else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE) { kfd_set_dbg_ev_from_interrupt(dev, pasid, KFD_DEBUG_DOORBELL_ID(context_id0), diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c index d01bb57733b3..447829c22295 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c @@ -97,18 +97,22 @@ void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd, void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm, const uint32_t *cu_mask, uint32_t cu_mask_count, - uint32_t *se_mask) + uint32_t *se_mask, uint32_t inst) { struct kfd_cu_info cu_info; uint32_t cu_per_sh[KFD_MAX_NUM_SE][KFD_MAX_NUM_SH_PER_SE] = {0}; bool wgp_mode_req = KFD_GC_VERSION(mm->dev) >= IP_VERSION(10, 0, 0); uint32_t en_mask = wgp_mode_req ? 0x3 : 0x1; - int i, se, sh, cu, cu_bitmap_sh_mul, inc = wgp_mode_req ? 2 : 1; + int i, se, sh, cu, cu_bitmap_sh_mul, cu_inc = wgp_mode_req ? 2 : 1; + uint32_t cu_active_per_node; + int inc = cu_inc * NUM_XCC(mm->dev->xcc_mask); + int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1; amdgpu_amdkfd_get_cu_info(mm->dev->adev, &cu_info); - if (cu_mask_count > cu_info.cu_active_number) - cu_mask_count = cu_info.cu_active_number; + cu_active_per_node = cu_info.cu_active_number / mm->dev->kfd->num_nodes; + if (cu_mask_count > cu_active_per_node) + cu_mask_count = cu_active_per_node; /* Exceeding these bounds corrupts the stack and indicates a coding error. * Returning with no CU's enabled will hang the queue, which should be @@ -141,7 +145,8 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm, for (se = 0; se < cu_info.num_shader_engines; se++) for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) cu_per_sh[se][sh] = hweight32( - cu_info.cu_bitmap[se % 4][sh + (se / 4) * cu_bitmap_sh_mul]); + cu_info.cu_bitmap[xcc_inst][se % 4][sh + (se / 4) * + cu_bitmap_sh_mul]); /* Symmetrically map cu_mask to all SEs & SHs: * se_mask programs up to 2 SH in the upper and lower 16 bits. @@ -164,20 +169,33 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm, * cu_mask[0] bit8 -> se_mask[0] bit1 (SE0,SH0,CU1) * ... * + * For GFX 9.4.3, the following code only looks at a + * subset of the cu_mask corresponding to the inst parameter. + * If we have n XCCs under one GPU node + * cu_mask[0] bit0 -> XCC0 se_mask[0] bit0 (XCC0,SE0,SH0,CU0) + * cu_mask[0] bit1 -> XCC1 se_mask[0] bit0 (XCC1,SE0,SH0,CU0) + * .. + * cu_mask[0] bitn -> XCCn se_mask[0] bit0 (XCCn,SE0,SH0,CU0) + * cu_mask[0] bit n+1 -> XCC0 se_mask[1] bit0 (XCC0,SE1,SH0,CU0) + * + * For example, if there are 6 XCCs under 1 KFD node, this code + * running for each inst, will look at the bits as: + * inst, inst + 6, inst + 12... + * * First ensure all CUs are disabled, then enable user specified CUs. */ for (i = 0; i < cu_info.num_shader_engines; i++) se_mask[i] = 0; - i = 0; - for (cu = 0; cu < 16; cu += inc) { + i = inst; + for (cu = 0; cu < 16; cu += cu_inc) { for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) { for (se = 0; se < cu_info.num_shader_engines; se++) { if (cu_per_sh[se][sh] > cu) { if (cu_mask[i / 32] & (en_mask << (i % 32))) se_mask[se] |= en_mask << (cu + sh * 16); i += inc; - if (i == cu_mask_count) + if (i >= cu_mask_count) return; } } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h index 23158db7da03..57bf5e513f4d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h @@ -138,7 +138,7 @@ void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd, void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm, const uint32_t *cu_mask, uint32_t cu_mask_count, - uint32_t *se_mask); + uint32_t *se_mask, uint32_t inst); int kfd_hiq_load_mqd_kiq(struct mqd_manager *mm, void *mqd, uint32_t pipe_id, uint32_t queue_id, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index ee1d32d957f2..1a4a69943c71 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -52,7 +52,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, return; mqd_symmetrically_map_cu_mask(mm, - minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); + minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); m = get_mqd(mqd); m->compute_static_thread_mgmt_se0 = se_mask[0]; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c index 83699392c808..8b7fed913526 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c @@ -52,7 +52,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, return; mqd_symmetrically_map_cu_mask(mm, - minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); + minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); m = get_mqd(mqd); m->compute_static_thread_mgmt_se0 = se_mask[0]; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c index 2319467d2d95..15277f1d5cf0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -71,7 +71,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, } mqd_symmetrically_map_cu_mask(mm, - minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); + minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); m->compute_static_thread_mgmt_se0 = se_mask[0]; m->compute_static_thread_mgmt_se1 = se_mask[1]; @@ -321,6 +321,43 @@ static int get_wave_state(struct mqd_manager *mm, void *mqd, return 0; } +static void checkpoint_mqd(struct mqd_manager *mm, void *mqd, void *mqd_dst, void *ctl_stack_dst) +{ + struct v11_compute_mqd *m; + + m = get_mqd(mqd); + + memcpy(mqd_dst, m, sizeof(struct v11_compute_mqd)); +} + +static void restore_mqd(struct mqd_manager *mm, void **mqd, + struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, + struct queue_properties *qp, + const void *mqd_src, + const void *ctl_stack_src, const u32 ctl_stack_size) +{ + uint64_t addr; + struct v11_compute_mqd *m; + + m = (struct v11_compute_mqd *) mqd_mem_obj->cpu_ptr; + addr = mqd_mem_obj->gpu_addr; + + memcpy(m, mqd_src, sizeof(*m)); + + *mqd = m; + if (gart_addr) + *gart_addr = addr; + + m->cp_hqd_pq_doorbell_control = + qp->doorbell_off << + CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; + pr_debug("cp_hqd_pq_doorbell_control 0x%x\n", + m->cp_hqd_pq_doorbell_control); + + qp->is_active = 0; +} + + static void init_mqd_hiq(struct mqd_manager *mm, void **mqd, struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr, struct queue_properties *q) @@ -457,6 +494,9 @@ struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, mqd->is_occupied = kfd_is_occupied_cp; mqd->mqd_size = sizeof(struct v11_compute_mqd); mqd->get_wave_state = get_wave_state; + mqd->mqd_stride = kfd_mqd_stride; + mqd->checkpoint_mqd = checkpoint_mqd; + mqd->restore_mqd = restore_mqd; #if defined(CONFIG_DEBUG_FS) mqd->debugfs_show_mqd = debugfs_show_mqd; #endif @@ -472,6 +512,7 @@ struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, mqd->destroy_mqd = destroy_hiq_mqd; mqd->is_occupied = kfd_is_occupied_cp; mqd->mqd_size = sizeof(struct v11_compute_mqd); + mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) mqd->debugfs_show_mqd = debugfs_show_mqd; #endif @@ -500,7 +541,10 @@ struct mqd_manager *mqd_manager_init_v11(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_sdma; mqd->destroy_mqd = kfd_destroy_mqd_sdma; mqd->is_occupied = kfd_is_occupied_sdma; + mqd->checkpoint_mqd = checkpoint_mqd; + mqd->restore_mqd = restore_mqd; mqd->mqd_size = sizeof(struct v11_sdma_mqd); + mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) mqd->debugfs_show_mqd = debugfs_show_mqd_sdma; #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index e23d32f35607..42d881809dc7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -60,7 +60,7 @@ static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) } static void update_cu_mask(struct mqd_manager *mm, void *mqd, - struct mqd_update_info *minfo) + struct mqd_update_info *minfo, uint32_t inst) { struct v9_mqd *m; uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; @@ -69,27 +69,36 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, return; mqd_symmetrically_map_cu_mask(mm, - minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); + minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, inst); m = get_mqd(mqd); + m->compute_static_thread_mgmt_se0 = se_mask[0]; m->compute_static_thread_mgmt_se1 = se_mask[1]; m->compute_static_thread_mgmt_se2 = se_mask[2]; m->compute_static_thread_mgmt_se3 = se_mask[3]; - m->compute_static_thread_mgmt_se4 = se_mask[4]; - m->compute_static_thread_mgmt_se5 = se_mask[5]; - m->compute_static_thread_mgmt_se6 = se_mask[6]; - m->compute_static_thread_mgmt_se7 = se_mask[7]; - - pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", - m->compute_static_thread_mgmt_se0, - m->compute_static_thread_mgmt_se1, - m->compute_static_thread_mgmt_se2, - m->compute_static_thread_mgmt_se3, - m->compute_static_thread_mgmt_se4, - m->compute_static_thread_mgmt_se5, - m->compute_static_thread_mgmt_se6, - m->compute_static_thread_mgmt_se7); + if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3)) { + m->compute_static_thread_mgmt_se4 = se_mask[4]; + m->compute_static_thread_mgmt_se5 = se_mask[5]; + m->compute_static_thread_mgmt_se6 = se_mask[6]; + m->compute_static_thread_mgmt_se7 = se_mask[7]; + + pr_debug("update cu mask to %#x %#x %#x %#x %#x %#x %#x %#x\n", + m->compute_static_thread_mgmt_se0, + m->compute_static_thread_mgmt_se1, + m->compute_static_thread_mgmt_se2, + m->compute_static_thread_mgmt_se3, + m->compute_static_thread_mgmt_se4, + m->compute_static_thread_mgmt_se5, + m->compute_static_thread_mgmt_se6, + m->compute_static_thread_mgmt_se7); + } else { + pr_debug("inst: %u, update cu mask to %#x %#x %#x %#x\n", + inst, m->compute_static_thread_mgmt_se0, + m->compute_static_thread_mgmt_se1, + m->compute_static_thread_mgmt_se2, + m->compute_static_thread_mgmt_se3); + } } static void set_priority(struct v9_mqd *m, struct queue_properties *q) @@ -290,7 +299,8 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) m->cp_hqd_ctx_save_control = 0; - update_cu_mask(mm, mqd, minfo); + if (KFD_GC_VERSION(mm->dev) != IP_VERSION(9, 4, 3)) + update_cu_mask(mm, mqd, minfo, 0); set_priority(m, q); q->is_active = QUEUE_IS_ACTIVE(*q); @@ -676,6 +686,8 @@ static void update_mqd_v9_4_3(struct mqd_manager *mm, void *mqd, m = get_mqd(mqd + size * xcc); update_mqd(mm, m, q, minfo); + update_cu_mask(mm, mqd, minfo, xcc); + if (q->format == KFD_QUEUE_FORMAT_AQL) { switch (xcc) { case 0: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 657c37822980..3e1a574d4ea6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -55,7 +55,7 @@ static void update_cu_mask(struct mqd_manager *mm, void *mqd, return; mqd_symmetrically_map_cu_mask(mm, - minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask); + minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); m = get_mqd(mqd); m->compute_static_thread_mgmt_se0 = se_mask[0]; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c index 8ce6f5200905..1a03173e2313 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c @@ -299,8 +299,7 @@ static int pm_set_grace_period_v9(struct packet_manager *pm, pm->dqm->wait_times, grace_period, ®_offset, - ®_data, - 0); + ®_data); if (grace_period == USE_DEFAULT_GRACE_PERIOD) reg_data = pm->dqm->wait_times; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 3d9ce44d88da..fa24e1852493 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1466,8 +1466,7 @@ void kfd_flush_tlb(struct kfd_process_device *pdd, enum TLB_FLUSH_TYPE type); static inline bool kfd_flush_tlb_after_unmap(struct kfd_dev *dev) { - return KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) || - KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2) || + return KFD_GC_VERSION(dev) > IP_VERSION(9, 4, 2) || (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 1) && dev->sdma_fw_version >= 18) || KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 0); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 011561605983..bb16b795d1bc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1686,6 +1686,8 @@ static int svm_range_validate_and_map(struct mm_struct *mm, WRITE_ONCE(p->svms.faulting_task, NULL); if (r) { pr_debug("failed %d to get svm range pages\n", r); + if (r == -EBUSY) + r = -EAGAIN; goto unreserve_out; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index ff98fded9534..c8c75ff7cea8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -450,8 +450,7 @@ static ssize_t node_show(struct kobject *kobj, struct attribute *attr, sysfs_show_32bit_prop(buffer, offs, "cpu_cores_count", dev->node_props.cpu_cores_count); sysfs_show_32bit_prop(buffer, offs, "simd_count", - dev->gpu ? (dev->node_props.simd_count * - NUM_XCC(dev->gpu->xcc_mask)) : 0); + dev->gpu ? dev->node_props.simd_count : 0); sysfs_show_32bit_prop(buffer, offs, "mem_banks_count", dev->node_props.mem_banks_count); sysfs_show_32bit_prop(buffer, offs, "caches_count", @@ -1597,14 +1596,17 @@ static int fill_in_l1_pcache(struct kfd_cache_properties **props_ext, static int fill_in_l2_l3_pcache(struct kfd_cache_properties **props_ext, struct kfd_gpu_cache_info *pcache_info, struct kfd_cu_info *cu_info, - int cache_type, unsigned int cu_processor_id) + int cache_type, unsigned int cu_processor_id, + struct kfd_node *knode) { unsigned int cu_sibling_map_mask; int first_active_cu; - int i, j, k; + int i, j, k, xcc, start, end; struct kfd_cache_properties *pcache = NULL; - cu_sibling_map_mask = cu_info->cu_bitmap[0][0]; + start = ffs(knode->xcc_mask) - 1; + end = start + NUM_XCC(knode->xcc_mask); + cu_sibling_map_mask = cu_info->cu_bitmap[start][0][0]; cu_sibling_map_mask &= ((1 << pcache_info[cache_type].num_cu_shared) - 1); first_active_cu = ffs(cu_sibling_map_mask); @@ -1639,16 +1641,18 @@ static int fill_in_l2_l3_pcache(struct kfd_cache_properties **props_ext, cu_sibling_map_mask = cu_sibling_map_mask >> (first_active_cu - 1); k = 0; - for (i = 0; i < cu_info->num_shader_engines; i++) { - for (j = 0; j < cu_info->num_shader_arrays_per_engine; j++) { - pcache->sibling_map[k] = (uint8_t)(cu_sibling_map_mask & 0xFF); - pcache->sibling_map[k+1] = (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF); - pcache->sibling_map[k+2] = (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF); - pcache->sibling_map[k+3] = (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF); - k += 4; - - cu_sibling_map_mask = cu_info->cu_bitmap[i % 4][j + i / 4]; - cu_sibling_map_mask &= ((1 << pcache_info[cache_type].num_cu_shared) - 1); + for (xcc = start; xcc < end; xcc++) { + for (i = 0; i < cu_info->num_shader_engines; i++) { + for (j = 0; j < cu_info->num_shader_arrays_per_engine; j++) { + pcache->sibling_map[k] = (uint8_t)(cu_sibling_map_mask & 0xFF); + pcache->sibling_map[k+1] = (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF); + pcache->sibling_map[k+2] = (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF); + pcache->sibling_map[k+3] = (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF); + k += 4; + + cu_sibling_map_mask = cu_info->cu_bitmap[xcc][i % 4][j + i / 4]; + cu_sibling_map_mask &= ((1 << pcache_info[cache_type].num_cu_shared) - 1); + } } } pcache->sibling_map_size = k; @@ -1666,7 +1670,7 @@ static int fill_in_l2_l3_pcache(struct kfd_cache_properties **props_ext, static void kfd_fill_cache_non_crat_info(struct kfd_topology_device *dev, struct kfd_node *kdev) { struct kfd_gpu_cache_info *pcache_info = NULL; - int i, j, k; + int i, j, k, xcc, start, end; int ct = 0; unsigned int cu_processor_id; int ret; @@ -1700,37 +1704,42 @@ static void kfd_fill_cache_non_crat_info(struct kfd_topology_device *dev, struct * then it will consider only one CU from * the shared unit */ + start = ffs(kdev->xcc_mask) - 1; + end = start + NUM_XCC(kdev->xcc_mask); + for (ct = 0; ct < num_of_cache_types; ct++) { cu_processor_id = gpu_processor_id; if (pcache_info[ct].cache_level == 1) { - for (i = 0; i < pcu_info->num_shader_engines; i++) { - for (j = 0; j < pcu_info->num_shader_arrays_per_engine; j++) { - for (k = 0; k < pcu_info->num_cu_per_sh; k += pcache_info[ct].num_cu_shared) { + for (xcc = start; xcc < end; xcc++) { + for (i = 0; i < pcu_info->num_shader_engines; i++) { + for (j = 0; j < pcu_info->num_shader_arrays_per_engine; j++) { + for (k = 0; k < pcu_info->num_cu_per_sh; k += pcache_info[ct].num_cu_shared) { - ret = fill_in_l1_pcache(&props_ext, pcache_info, pcu_info, - pcu_info->cu_bitmap[i % 4][j + i / 4], ct, + ret = fill_in_l1_pcache(&props_ext, pcache_info, pcu_info, + pcu_info->cu_bitmap[xcc][i % 4][j + i / 4], ct, cu_processor_id, k); - if (ret < 0) - break; + if (ret < 0) + break; - if (!ret) { - num_of_entries++; - list_add_tail(&props_ext->list, &dev->cache_props); - } + if (!ret) { + num_of_entries++; + list_add_tail(&props_ext->list, &dev->cache_props); + } - /* Move to next CU block */ - num_cu_shared = ((k + pcache_info[ct].num_cu_shared) <= - pcu_info->num_cu_per_sh) ? - pcache_info[ct].num_cu_shared : - (pcu_info->num_cu_per_sh - k); - cu_processor_id += num_cu_shared; + /* Move to next CU block */ + num_cu_shared = ((k + pcache_info[ct].num_cu_shared) <= + pcu_info->num_cu_per_sh) ? + pcache_info[ct].num_cu_shared : + (pcu_info->num_cu_per_sh - k); + cu_processor_id += num_cu_shared; + } } } } } else { ret = fill_in_l2_l3_pcache(&props_ext, pcache_info, - pcu_info, ct, cu_processor_id); + pcu_info, ct, cu_processor_id, kdev); if (ret < 0) break; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index dea32a9e5506..27386ce9a021 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -89,7 +89,7 @@ struct kfd_mem_properties { struct attribute attr; }; -#define CACHE_SIBLINGMAP_SIZE 64 +#define CACHE_SIBLINGMAP_SIZE 128 struct kfd_cache_properties { struct list_head list; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 268cb99a4c4b..868946dd7ef1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -65,6 +65,7 @@ #include "amdgpu_dm_debugfs.h" #endif #include "amdgpu_dm_psr.h" +#include "amdgpu_dm_replay.h" #include "ivsrcid/ivsrcid_vislands30.h" @@ -1273,11 +1274,15 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_ pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); - page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF; - page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12); - page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF; - page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12); - page_table_base.high_part = upper_32_bits(pt_base) & 0xF; + page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> + AMDGPU_GPU_PAGE_SHIFT); + page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> + AMDGPU_GPU_PAGE_SHIFT); + page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> + AMDGPU_GPU_PAGE_SHIFT); + page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> + AMDGPU_GPU_PAGE_SHIFT); + page_table_base.high_part = upper_32_bits(pt_base); page_table_base.low_part = lower_32_bits(pt_base); pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18; @@ -1639,8 +1644,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) } break; } - if (init_data.flags.gpu_vm_support) - init_data.flags.gpu_vm_support = amdgpu_sg_display_supported(adev); + if (init_data.flags.gpu_vm_support && + (amdgpu_sg_display == 0)) + init_data.flags.gpu_vm_support = false; if (init_data.flags.gpu_vm_support) adev->mode_info.gpu_vm_support = true; @@ -2334,14 +2340,62 @@ static int dm_late_init(void *handle) return detect_mst_link_for_all_connectors(adev_to_drm(adev)); } +static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) +{ + int ret; + u8 guid[16]; + u64 tmp64; + + mutex_lock(&mgr->lock); + if (!mgr->mst_primary) + goto out_fail; + + if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) { + drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); + goto out_fail; + } + + ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, + DP_MST_EN | + DP_UP_REQ_EN | + DP_UPSTREAM_IS_SRC); + if (ret < 0) { + drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n"); + goto out_fail; + } + + /* Some hubs forget their guids after they resume */ + ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16); + if (ret != 16) { + drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); + goto out_fail; + } + + if (memchr_inv(guid, 0, 16) == NULL) { + tmp64 = get_jiffies_64(); + memcpy(&guid[0], &tmp64, sizeof(u64)); + memcpy(&guid[8], &tmp64, sizeof(u64)); + + ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16); + + if (ret != 16) { + drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); + goto out_fail; + } + } + + memcpy(mgr->mst_primary->guid, guid, 16); + +out_fail: + mutex_unlock(&mgr->lock); +} + static void s3_handle_mst(struct drm_device *dev, bool suspend) { struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; struct drm_connector_list_iter iter; struct drm_dp_mst_topology_mgr *mgr; - int ret; - bool need_hotplug = false; drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { @@ -2363,18 +2417,15 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) if (!dp_is_lttpr_present(aconnector->dc_link)) try_to_configure_aux_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD); - ret = drm_dp_mst_topology_mgr_resume(mgr, true); - if (ret < 0) { - dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, - aconnector->dc_link); - need_hotplug = true; - } + /* TODO: move resume_mst_branch_status() into drm mst resume again + * once topology probing work is pulled out from mst resume into mst + * resume 2nd step. mst resume 2nd step should be called after old + * state getting restored (i.e. drm_atomic_helper_resume()). + */ + resume_mst_branch_status(mgr); } } drm_connector_list_iter_end(&iter); - - if (need_hotplug) - drm_kms_helper_hotplug_event(dev); } static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) @@ -2768,7 +2819,8 @@ static int dm_resume(void *handle) struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); enum dc_connection_type new_connection_type = dc_connection_none; struct dc_state *dc_state; - int i, r, j; + int i, r, j, ret; + bool need_hotplug = false; if (amdgpu_in_reset(adev)) { dc_state = dm->cached_dc_state; @@ -2866,7 +2918,7 @@ static int dm_resume(void *handle) continue; /* - * this is the case when traversing through already created + * this is the case when traversing through already created end sink * MST connectors, should be skipped */ if (aconnector && aconnector->mst_root) @@ -2926,6 +2978,27 @@ static int dm_resume(void *handle) dm->cached_state = NULL; + /* Do mst topology probing after resuming cached state*/ + drm_connector_list_iter_begin(ddev, &iter); + drm_for_each_connector_iter(connector, &iter) { + aconnector = to_amdgpu_dm_connector(connector); + if (aconnector->dc_link->type != dc_connection_mst_branch || + aconnector->mst_root) + continue; + + ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true); + + if (ret < 0) { + dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx, + aconnector->dc_link); + need_hotplug = true; + } + } + drm_connector_list_iter_end(&iter); + + if (need_hotplug) + drm_kms_helper_hotplug_event(ddev); + amdgpu_dm_irq_resume_late(adev); amdgpu_dm_smu_write_watermarks_table(adev); @@ -4265,6 +4338,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) enum dc_connection_type new_connection_type = dc_connection_none; const struct dc_plane_cap *plane; bool psr_feature_enabled = false; + bool replay_feature_enabled = false; int max_overlay = dm->dc->caps.max_slave_planes; dm->display_indexes_num = dm->dc->caps.max_streams; @@ -4374,6 +4448,20 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) } } + if (!(amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { + switch (adev->ip_versions[DCE_HWIP][0]) { + case IP_VERSION(3, 1, 4): + case IP_VERSION(3, 1, 5): + case IP_VERSION(3, 1, 6): + case IP_VERSION(3, 2, 0): + case IP_VERSION(3, 2, 1): + replay_feature_enabled = true; + break; + default: + replay_feature_enabled = amdgpu_dc_feature_mask & DC_REPLAY_MASK; + break; + } + } /* loops over all connectors on the board */ for (i = 0; i < link_cnt; i++) { struct dc_link *link = NULL; @@ -4422,6 +4510,12 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) amdgpu_dm_update_connector_after_detect(aconnector); setup_backlight_device(dm, aconnector); + /* + * Disable psr if replay can be enabled + */ + if (replay_feature_enabled && amdgpu_dm_setup_replay(link, aconnector)) + psr_feature_enabled = false; + if (psr_feature_enabled) amdgpu_dm_set_psr_caps(link); @@ -6004,8 +6098,6 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, if (recalculate_timing) drm_mode_set_crtcinfo(&saved_mode, 0); - else - drm_mode_set_crtcinfo(&mode, 0); /* * If scaling is enabled and refresh rate didn't change @@ -6567,6 +6659,8 @@ enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connec goto fail; } + drm_mode_set_crtcinfo(mode, 0); + stream = create_validate_stream_for_sink(aconnector, mode, to_dm_connector_state(connector->state), NULL); @@ -8051,7 +8145,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, bundle->surface_updates[planes_count].plane_info = &bundle->plane_infos[planes_count]; - if (acrtc_state->stream->link->psr_settings.psr_feature_enabled) { + if (acrtc_state->stream->link->psr_settings.psr_feature_enabled || + acrtc_state->stream->link->replay_settings.replay_feature_enabled) { fill_dc_dirty_rects(plane, old_plane_state, new_plane_state, new_crtc_state, &bundle->flip_addrs[planes_count], diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index a2d34be82613..9e4cc5eeda76 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -620,7 +620,7 @@ struct amdgpu_hdmi_vsdb_info { unsigned int max_refresh_rate_hz; /** - * @replay mode: Replay supported + * @replay_mode: Replay supported */ bool replay_mode; }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 30d4c6fd95f5..97b7a0b8a1c2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -29,6 +29,7 @@ #include "dc.h" #include "amdgpu.h" #include "amdgpu_dm_psr.h" +#include "amdgpu_dm_replay.h" #include "amdgpu_dm_crtc.h" #include "amdgpu_dm_plane.h" #include "amdgpu_dm_trace.h" @@ -123,7 +124,12 @@ static void vblank_control_worker(struct work_struct *work) * fill_dc_dirty_rects(). */ if (vblank_work->stream && vblank_work->stream->link) { - if (vblank_work->enable) { + /* + * Prioritize replay, instead of psr + */ + if (vblank_work->stream->link->replay_settings.replay_feature_enabled) + amdgpu_dm_replay_enable(vblank_work->stream, false); + else if (vblank_work->enable) { if (vblank_work->stream->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && vblank_work->stream->link->psr_settings.psr_allow_active) amdgpu_dm_psr_disable(vblank_work->stream); @@ -132,6 +138,7 @@ static void vblank_control_worker(struct work_struct *work) #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY !amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base) && #endif + vblank_work->stream->link->panel_config.psr.disallow_replay && vblank_work->acrtc->dm_irq_params.allow_psr_entry) { amdgpu_dm_psr_enable(vblank_work->stream); } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 8eeca160d434..cc74dd69acf2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1269,6 +1269,13 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, attributes.rotation_angle = 0; attributes.attribute_flags.value = 0; + /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM + * legacy gamma setup. + */ + if (crtc_state->cm_is_degamma_srgb && + adev->dm.dc->caps.color.dpp.gamma_corr) + attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; + attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; if (crtc_state->stream) { @@ -1468,6 +1475,15 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, drm_plane_create_blend_mode_property(plane, blend_caps); } + if (plane->type == DRM_PLANE_TYPE_PRIMARY) { + drm_plane_create_zpos_immutable_property(plane, 0); + } else if (plane->type == DRM_PLANE_TYPE_OVERLAY) { + unsigned int zpos = 1 + drm_plane_index(plane); + drm_plane_create_zpos_property(plane, zpos, 1, 254); + } else if (plane->type == DRM_PLANE_TYPE_CURSOR) { + drm_plane_create_zpos_immutable_property(plane, 255); + } + if (plane->type == DRM_PLANE_TYPE_PRIMARY && plane_cap && (plane_cap->pixel_format_support.nv12 || diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index 69ffd4424dc7..1b8c2aef4633 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -78,3 +78,4 @@ DC_EDID += dc_edid_parser.o AMD_DISPLAY_DMUB = $(addprefix $(AMDDALPATH)/dc/,$(DC_DMUB)) AMD_DISPLAY_EDID = $(addprefix $(AMDDALPATH)/dc/,$(DC_EDID)) AMD_DISPLAY_FILES += $(AMD_DISPLAY_DMUB) $(AMD_DISPLAY_EDID) + diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index c435f7632e8e..5ee87965a078 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -157,7 +157,7 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct int32_t N; int32_t j; - if (!pipe_ctx->stream) + if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER)) continue; /* Virtual encoders don't have this function */ if (!stream_enc->funcs->get_fifo_cal_average_level) @@ -188,7 +188,7 @@ void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, struct int32_t N; int32_t j; - if (!pipe_ctx->stream) + if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER)) continue; /* Virtual encoders don't have this function */ if (!stream_enc->funcs->get_fifo_cal_average_level) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c index 3e0da873cf4c..1042cf1a3ab0 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c @@ -32,6 +32,7 @@ #define MAX_INSTANCE 6 #define MAX_SEGMENT 6 +#define SMU_REGISTER_WRITE_RETRY_COUNT 5 struct IP_BASE_INSTANCE { unsigned int segment[MAX_SEGMENT]; @@ -132,6 +133,8 @@ static int dcn315_smu_send_msg_with_param( unsigned int msg_id, unsigned int param) { uint32_t result; + uint32_t i = 0; + uint32_t read_back_data; result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000); @@ -148,10 +151,19 @@ static int dcn315_smu_send_msg_with_param( /* Set the parameter register for the SMU message, unit is Mhz */ REG_WRITE(MP1_SMN_C2PMSG_37, param); - /* Trigger the message transaction by writing the message ID */ - generic_write_indirect_reg(CTX, - REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA), - mmMP1_C2PMSG_3, msg_id); + for (i = 0; i < SMU_REGISTER_WRITE_RETRY_COUNT; i++) { + /* Trigger the message transaction by writing the message ID */ + generic_write_indirect_reg(CTX, + REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA), + mmMP1_C2PMSG_3, msg_id); + read_back_data = generic_read_indirect_reg(CTX, + REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA), + mmMP1_C2PMSG_3); + if (read_back_data == msg_id) + break; + udelay(2); + smu_print("SMU msg id write fail %x times. \n", i + 1); + } result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000); diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c index 984b52923534..e9345f6554db 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c @@ -355,7 +355,7 @@ static void dcn32_update_clocks_update_dentist( int32_t N; int32_t j; - if (!pipe_ctx->stream) + if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER)) continue; /* Virtual encoders don't have this function */ if (!stream_enc->funcs->get_fifo_cal_average_level) @@ -401,7 +401,7 @@ static void dcn32_update_clocks_update_dentist( int32_t N; int32_t j; - if (!pipe_ctx->stream) + if (!resource_is_pipe_type(pipe_ctx, OTG_MASTER)) continue; /* Virtual encoders don't have this function */ if (!stream_enc->funcs->get_fifo_cal_average_level) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 566d7045b2de..3a9077b60029 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2073,12 +2073,12 @@ enum dc_status dc_commit_streams(struct dc *dc, } } - /* Check for case where we are going from odm 2:1 to max - * pipe scenario. For these cases, we will call - * commit_minimal_transition_state() to exit out of odm 2:1 - * first before processing new streams + /* ODM Combine 2:1 power optimization is only applied for single stream + * scenario, it uses extra pipes than needed to reduce power consumption + * We need to switch off this feature to make room for new streams. */ - if (stream_count == dc->res_pool->pipe_count) { + if (stream_count > dc->current_state->stream_count && + dc->current_state->stream_count == 1) { for (i = 0; i < dc->res_pool->pipe_count; i++) { pipe = &dc->current_state->res_ctx.pipe_ctx[i]; if (pipe->next_odm_pipe) @@ -3501,6 +3501,45 @@ static void commit_planes_for_stream_fast(struct dc *dc, top_pipe_to_program->stream->update_flags.raw = 0; } +static void wait_for_outstanding_hw_updates(struct dc *dc, const struct dc_state *dc_context) +{ +/* + * This function calls HWSS to wait for any potentially double buffered + * operations to complete. It should be invoked as a pre-amble prior + * to full update programming before asserting any HW locks. + */ + int pipe_idx; + int opp_inst; + int opp_count = dc->res_pool->pipe_count; + struct hubp *hubp; + int mpcc_inst; + const struct pipe_ctx *pipe_ctx; + + for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { + pipe_ctx = &dc_context->res_ctx.pipe_ctx[pipe_idx]; + + if (!pipe_ctx->stream) + continue; + + if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear) + pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg); + + hubp = pipe_ctx->plane_res.hubp; + if (!hubp) + continue; + + mpcc_inst = hubp->inst; + // MPCC inst is equal to pipe index in practice + for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { + if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { + dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); + dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; + break; + } + } + } +} + static void commit_planes_for_stream(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, @@ -3519,24 +3558,9 @@ static void commit_planes_for_stream(struct dc *dc, // dc->current_state anymore, so we have to cache it before we apply // the new SubVP context subvp_prev_use = false; - - dc_z10_restore(dc); - - if (update_type == UPDATE_TYPE_FULL) { - /* wait for all double-buffer activity to clear on all pipes */ - int pipe_idx; - - for (pipe_idx = 0; pipe_idx < dc->res_pool->pipe_count; pipe_idx++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; - - if (!pipe_ctx->stream) - continue; - - if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear) - pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg); - } - } + if (update_type == UPDATE_TYPE_FULL) + wait_for_outstanding_hw_updates(dc, context); if (update_type == UPDATE_TYPE_FULL) { dc_allow_idle_optimizations(dc, false); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c index 30c0644d4418..be5a6d008b29 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_enc_cfg.c @@ -169,11 +169,23 @@ static void add_link_enc_assignment( /* Return first available DIG link encoder. */ static enum engine_id find_first_avail_link_enc( const struct dc_context *ctx, - const struct dc_state *state) + const struct dc_state *state, + enum engine_id eng_id_requested) { enum engine_id eng_id = ENGINE_ID_UNKNOWN; int i; + if (eng_id_requested != ENGINE_ID_UNKNOWN) { + + for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { + eng_id = state->res_ctx.link_enc_cfg_ctx.link_enc_avail[i]; + if (eng_id == eng_id_requested) + return eng_id; + } + } + + eng_id = ENGINE_ID_UNKNOWN; + for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { eng_id = state->res_ctx.link_enc_cfg_ctx.link_enc_avail[i]; if (eng_id != ENGINE_ID_UNKNOWN) @@ -287,7 +299,7 @@ void link_enc_cfg_link_encs_assign( struct dc_stream_state *streams[], uint8_t stream_count) { - enum engine_id eng_id = ENGINE_ID_UNKNOWN; + enum engine_id eng_id = ENGINE_ID_UNKNOWN, eng_id_req = ENGINE_ID_UNKNOWN; int i; int j; @@ -377,8 +389,14 @@ void link_enc_cfg_link_encs_assign( * assigned to that endpoint. */ link_enc = get_link_enc_used_by_link(state, stream->link); - if (link_enc == NULL) - eng_id = find_first_avail_link_enc(stream->ctx, state); + if (link_enc == NULL) { + + if (stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && + stream->link->dpia_preferred_eng_id != ENGINE_ID_UNKNOWN) + eng_id_req = stream->link->dpia_preferred_eng_id; + + eng_id = find_first_avail_link_enc(stream->ctx, state, eng_id_req); + } else eng_id = link_enc->preferred_engine; @@ -402,7 +420,9 @@ void link_enc_cfg_link_encs_assign( DC_LOG_DEBUG("%s: CUR %s(%d) - enc_id(%d)\n", __func__, assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? "PHY" : "DPIA", - assignment.ep_id.link_id.enum_id - 1, + assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? + assignment.ep_id.link_id.enum_id : + assignment.ep_id.link_id.enum_id - 1, assignment.eng_id); } for (i = 0; i < MAX_PIPES; i++) { @@ -413,7 +433,9 @@ void link_enc_cfg_link_encs_assign( DC_LOG_DEBUG("%s: NEW %s(%d) - enc_id(%d)\n", __func__, assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? "PHY" : "DPIA", - assignment.ep_id.link_id.enum_id - 1, + assignment.ep_id.ep_type == DISPLAY_ENDPOINT_PHY ? + assignment.ep_id.link_id.enum_id : + assignment.ep_id.link_id.enum_id - 1, assignment.eng_id); } @@ -478,7 +500,6 @@ struct dc_link *link_enc_cfg_get_link_using_link_enc( if (stream) link = stream->link; - // dm_output_to_console("%s: No link using DIG(%d).\n", __func__, eng_id); return link; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 0d0bef8eb331..31e3183497a7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1496,6 +1496,7 @@ struct dc_link { * object creation. */ enum engine_id eng_id; + enum engine_id dpia_preferred_eng_id; bool test_pattern_enabled; enum dp_test_pattern current_test_pattern; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index ad967b58d7be..2a6157555fd1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -964,7 +964,9 @@ void dce110_edp_backlight_control( return; } - if (link->panel_cntl) { + if (link->panel_cntl && !(link->dpcd_sink_ext_caps.bits.oled || + link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || + link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) { bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl); if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) { @@ -1176,12 +1178,15 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) dto_params.otg_inst = tg->inst; dto_params.timing = &pipe_ctx->stream->timing; dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; - dccg->funcs->set_dtbclk_dto(dccg, &dto_params); - dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst); - dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst); - } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->disable_symclk_se) + if (dccg) { + dccg->funcs->set_dtbclk_dto(dccg, &dto_params); + dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst); + dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst); + } + } else if (dccg && dccg->funcs->disable_symclk_se) { dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A); + } if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { /* TODO: This looks like a bug to me as we are disabling HPO IO when @@ -2656,11 +2661,11 @@ void dce110_prepare_bandwidth( struct clk_mgr *dccg = dc->clk_mgr; dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); - - dccg->funcs->update_clocks( - dccg, - context, - false); + if (dccg) + dccg->funcs->update_clocks( + dccg, + context, + false); } void dce110_optimize_bandwidth( @@ -2671,10 +2676,11 @@ void dce110_optimize_bandwidth( dce110_set_displaymarks(dc, context); - dccg->funcs->update_clocks( - dccg, - context, - true); + if (dccg) + dccg->funcs->update_clocks( + dccg, + context, + true); } static void dce110_program_front_end_for_pipe( diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 65fa9e21ad9c..aeadc587433f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -1106,29 +1106,6 @@ void dcn20_blank_pixel_data( v_active, offset); - if (!blank && dc->debug.enable_single_display_2to1_odm_policy) { - /* when exiting dynamic ODM need to reinit DPG state for unused pipes */ - struct pipe_ctx *old_odm_pipe = dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx].next_odm_pipe; - - odm_pipe = pipe_ctx->next_odm_pipe; - - while (old_odm_pipe) { - if (!odm_pipe || old_odm_pipe->pipe_idx != odm_pipe->pipe_idx) - dc->hwss.set_disp_pattern_generator(dc, - old_odm_pipe, - CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, - CONTROLLER_DP_COLOR_SPACE_UDEFINED, - COLOR_DEPTH_888, - NULL, - 0, - 0, - 0); - old_odm_pipe = old_odm_pipe->next_odm_pipe; - if (odm_pipe) - odm_pipe = odm_pipe->next_odm_pipe; - } - } - if (!blank) if (stream_res->abm) { dc->hwss.set_pipe(pipe_ctx); @@ -1584,17 +1561,6 @@ static void dcn20_update_dchubp_dpp( || plane_state->update_flags.bits.global_alpha_change || plane_state->update_flags.bits.per_pixel_alpha_change) { // MPCC inst is equal to pipe index in practice - int mpcc_inst = hubp->inst; - int opp_inst; - int opp_count = dc->res_pool->pipe_count; - - for (opp_inst = 0; opp_inst < opp_count; opp_inst++) { - if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { - dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); - dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; - break; - } - } hws->funcs.update_mpcc(dc, pipe_ctx); } @@ -1722,11 +1688,16 @@ static void dcn20_program_pipe( struct dc_state *context) { struct dce_hwseq *hws = dc->hwseq; - /* Only need to unblank on top pipe */ - if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level) - && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe) - hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible); + /* Only need to unblank on top pipe */ + if (resource_is_pipe_type(pipe_ctx, OTG_MASTER)) { + if (pipe_ctx->update_flags.bits.enable || + pipe_ctx->update_flags.bits.odm || + pipe_ctx->stream->update_flags.bits.abm_level) + hws->funcs.blank_pixel_data(dc, pipe_ctx, + !pipe_ctx->plane_state || + !pipe_ctx->plane_state->visible); + } /* Only update TG on top pipe */ if (pipe_ctx->update_flags.bits.global_sync && !pipe_ctx->top_pipe @@ -2721,8 +2692,6 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) struct dce_hwseq *hws = dc->hwseq; unsigned int k1_div = PIXEL_RATE_DIV_NA; unsigned int k2_div = PIXEL_RATE_DIV_NA; - struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link); - struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { if (dc->hwseq->funcs.setup_hpo_hw_control) @@ -2742,10 +2711,8 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) dto_params.timing = &pipe_ctx->stream->timing; dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); dccg->funcs->set_dtbclk_dto(dccg, &dto_params); - } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST && dccg->funcs->enable_symclk_se) - dccg->funcs->enable_symclk_se(dccg, - stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A); - + } else { + } if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) { hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c index 6cef62d7a2e5..255713ec29bb 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c @@ -987,3 +987,20 @@ void dcn30_prepare_bandwidth(struct dc *dc, } } +void dcn30_set_static_screen_control(struct pipe_ctx **pipe_ctx, + int num_pipes, const struct dc_static_screen_params *params) +{ + unsigned int i; + unsigned int triggers = 0; + + if (params->triggers.surface_update) + triggers |= 0x100; + if (params->triggers.cursor_update) + triggers |= 0x8; + if (params->triggers.force_trigger) + triggers |= 0x1; + + for (i = 0; i < num_pipes; i++) + pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(pipe_ctx[i]->stream_res.tg, + triggers, params->num_frames); +} diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h index a24a8e33a3d2..ce19c54097f8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h @@ -87,5 +87,7 @@ void dcn30_set_hubp_blank(const struct dc *dc, void dcn30_prepare_bandwidth(struct dc *dc, struct dc_state *context); +void dcn30_set_static_screen_control(struct pipe_ctx **pipe_ctx, + int num_pipes, const struct dc_static_screen_params *params); #endif /* __DC_HWSS_DCN30_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c index 3d19acaa12f3..0de8b2783cf6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c @@ -64,7 +64,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = { .update_bandwidth = dcn20_update_bandwidth, .set_drr = dcn10_set_drr, .get_position = dcn10_get_position, - .set_static_screen_control = dcn10_set_static_screen_control, + .set_static_screen_control = dcn30_set_static_screen_control, .setup_stereo = dcn10_setup_stereo, .set_avmute = dcn30_set_avmute, .log_hw_state = dcn10_log_hw_state, diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c index 257df8660b4c..61205cdbe2d5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c @@ -75,6 +75,7 @@ static const struct hw_sequencer_funcs dcn301_funcs = { .get_hw_state = dcn10_get_hw_state, .clear_status_bits = dcn10_clear_status_bits, .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, + .edp_backlight_control = dce110_edp_backlight_control, .edp_power_control = dce110_edp_power_control, .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, .set_cursor_position = dcn10_set_cursor_position, diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c index fc25cc300a17..1d7bc1e39afe 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c @@ -67,7 +67,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = { .update_bandwidth = dcn20_update_bandwidth, .set_drr = dcn10_set_drr, .get_position = dcn10_get_position, - .set_static_screen_control = dcn10_set_static_screen_control, + .set_static_screen_control = dcn30_set_static_screen_control, .setup_stereo = dcn10_setup_stereo, .set_avmute = dcn30_set_avmute, .log_hw_state = dcn10_log_hw_state, diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c index ca8fe55c33b8..4ef85c3a0688 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_init.c @@ -69,7 +69,7 @@ static const struct hw_sequencer_funcs dcn314_funcs = { .update_bandwidth = dcn20_update_bandwidth, .set_drr = dcn10_set_drr, .get_position = dcn10_get_position, - .set_static_screen_control = dcn10_set_static_screen_control, + .set_static_screen_control = dcn30_set_static_screen_control, .setup_stereo = dcn10_setup_stereo, .set_avmute = dcn30_set_avmute, .log_hw_state = dcn10_log_hw_state, diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c index 1c1fb2fa0822..004beed9bd44 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c @@ -1032,6 +1032,28 @@ static const struct dce_i2c_mask i2c_masks = { I2C_COMMON_MASK_SH_LIST_DCN30(_MASK) }; +/* ========================================================== */ + +/* + * DPIA index | Preferred Encoder | Host Router + * 0 | C | 0 + * 1 | First Available | 0 + * 2 | D | 1 + * 3 | First Available | 1 + */ +/* ========================================================== */ +static const enum engine_id dpia_to_preferred_enc_id_table[] = { + ENGINE_ID_DIGC, + ENGINE_ID_DIGC, + ENGINE_ID_DIGD, + ENGINE_ID_DIGD +}; + +static enum engine_id dcn314_get_preferred_eng_id_dpia(unsigned int dpia_index) +{ + return dpia_to_preferred_enc_id_table[dpia_index]; +} + static struct dce_i2c_hw *dcn31_i2c_hw_create( struct dc_context *ctx, uint32_t inst) @@ -1785,6 +1807,7 @@ static struct resource_funcs dcn314_res_pool_funcs = { .update_bw_bounding_box = dcn314_update_bw_bounding_box, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .get_panel_config_defaults = dcn314_get_panel_config_defaults, + .get_preferred_eng_id_dpia = dcn314_get_preferred_eng_id_dpia, }; static struct clock_source *dcn30_clock_source_create( diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c index 777b2fac20c4..c7417147dff1 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_init.c @@ -65,7 +65,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = { .update_bandwidth = dcn20_update_bandwidth, .set_drr = dcn10_set_drr, .get_position = dcn10_get_position, - .set_static_screen_control = dcn10_set_static_screen_control, + .set_static_screen_control = dcn30_set_static_screen_control, .setup_stereo = dcn10_setup_stereo, .set_avmute = dcn30_set_avmute, .log_hw_state = dcn10_log_hw_state, diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c index 3082da04a63d..1d052f08aff5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_mpc.c @@ -75,7 +75,7 @@ void mpc32_power_on_blnd_lut( if (power_on) { REG_UPDATE(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_FORCE, 0); REG_WAIT(MPCC_MCM_MEM_PWR_CTRL[mpcc_id], MPCC_MCM_1DLUT_MEM_PWR_STATE, 0, 1, 5); - } else { + } else if (!mpc->ctx->dc->debug.disable_mem_low_power) { ASSERT(false); /* TODO: change to mpc * dpp_base->ctx->dc->optimized_required = true; diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c index 935cd23e6a01..f9d601c8c721 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -2564,18 +2564,128 @@ static int find_optimal_free_pipe_as_secondary_dpp_pipe( return free_pipe_idx; } +static struct pipe_ctx *find_idle_secondary_pipe_check_mpo( + struct resource_context *res_ctx, + const struct resource_pool *pool, + const struct pipe_ctx *primary_pipe) +{ + int i; + struct pipe_ctx *secondary_pipe = NULL; + struct pipe_ctx *next_odm_mpo_pipe = NULL; + int primary_index, preferred_pipe_idx; + struct pipe_ctx *old_primary_pipe = NULL; + + /* + * Modified from find_idle_secondary_pipe + * With windowed MPO and ODM, we want to avoid the case where we want a + * free pipe for the left side but the free pipe is being used on the + * right side. + * Add check on current_state if the primary_pipe is the left side, + * to check the right side ( primary_pipe->next_odm_pipe ) to see if + * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe ) + * - If so, then don't use this pipe + * EXCEPTION - 3 plane ( 2 MPO plane ) case + * - in this case, the primary pipe has already gotten a free pipe for the + * MPO window in the left + * - when it tries to get a free pipe for the MPO window on the right, + * it will see that it is already assigned to the right side + * ( primary_pipe->next_odm_pipe ). But in this case, we want this + * free pipe, since it will be for the right side. So add an + * additional condition, that skipping the free pipe on the right only + * applies if the primary pipe has no bottom pipe currently assigned + */ + if (primary_pipe) { + primary_index = primary_pipe->pipe_idx; + old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index]; + if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe) + && (!primary_pipe->bottom_pipe)) + next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe; + + preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; + if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) && + !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { + secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; + secondary_pipe->pipe_idx = preferred_pipe_idx; + } + } + + /* + * search backwards for the second pipe to keep pipe + * assignment more consistent + */ + if (!secondary_pipe) + for (i = pool->pipe_count - 1; i >= 0; i--) { + if ((res_ctx->pipe_ctx[i].stream == NULL) && + !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { + secondary_pipe = &res_ctx->pipe_ctx[i]; + secondary_pipe->pipe_idx = i; + break; + } + } + + return secondary_pipe; +} + +static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer( + struct dc_state *state, + const struct resource_pool *pool, + struct dc_stream_state *stream, + const struct pipe_ctx *head_pipe) +{ + struct resource_context *res_ctx = &state->res_ctx; + struct pipe_ctx *idle_pipe, *pipe; + struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx; + int head_index; + + if (!head_pipe) + ASSERT(0); + + /* + * Modified from dcn20_acquire_idle_pipe_for_layer + * Check if head_pipe in old_context already has bottom_pipe allocated. + * - If so, check if that pipe is available in the current context. + * -- If so, reuse pipe from old_context + */ + head_index = head_pipe->pipe_idx; + pipe = &old_ctx->pipe_ctx[head_index]; + if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { + idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; + idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx; + } else { + idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe); + if (!idle_pipe) + return NULL; + } + + idle_pipe->stream = head_pipe->stream; + idle_pipe->stream_res.tg = head_pipe->stream_res.tg; + idle_pipe->stream_res.opp = head_pipe->stream_res.opp; + + idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; + idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; + idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; + idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; + + return idle_pipe; +} + struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe( const struct dc_state *cur_ctx, struct dc_state *new_ctx, const struct resource_pool *pool, const struct pipe_ctx *opp_head_pipe) { - int free_pipe_idx = - find_optimal_free_pipe_as_secondary_dpp_pipe( - &cur_ctx->res_ctx, &new_ctx->res_ctx, - pool, opp_head_pipe); + + int free_pipe_idx; struct pipe_ctx *free_pipe; + if (!opp_head_pipe->stream->ctx->dc->config.enable_windowed_mpo_odm) + return dcn32_acquire_idle_pipe_for_head_pipe_in_layer( + new_ctx, pool, opp_head_pipe->stream, opp_head_pipe); + + free_pipe_idx = find_optimal_free_pipe_as_secondary_dpp_pipe( + &cur_ctx->res_ctx, &new_ctx->res_ctx, + pool, opp_head_pipe); if (free_pipe_idx >= 0) { free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx]; free_pipe->pipe_idx = free_pipe_idx; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c index 8afda5ecc0cd..5805fb02af14 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c @@ -1099,6 +1099,11 @@ void dcn20_calculate_dlg_params(struct dc *dc, context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; + if (dc->ctx->dce_version < DCN_VERSION_3_1 && + context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid) + dcn20_adjust_freesync_v_startup( + &context->res_ctx.pipe_ctx[i].stream->timing, + &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start); pipe_idx++; } @@ -1927,7 +1932,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co int vlevel = 0; int pipe_split_from[MAX_PIPES]; int pipe_cnt = 0; - int i = 0; display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); DC_LOGGER_INIT(dc->ctx->logger); @@ -1951,15 +1955,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate); dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); - for (i = 0; i < dc->res_pool->pipe_count; i++) { - if (!context->res_ctx.pipe_ctx[i].stream) - continue; - if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid) - dcn20_adjust_freesync_v_startup( - &context->res_ctx.pipe_ctx[i].stream->timing, - &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start); - } - BW_VAL_TRACE_END_WATERMARKS(); goto validate_out; @@ -2232,7 +2227,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc, int vlevel = 0; int pipe_split_from[MAX_PIPES]; int pipe_cnt = 0; - int i = 0; display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC); DC_LOGGER_INIT(dc->ctx->logger); @@ -2261,15 +2255,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc, dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate); dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel); - for (i = 0; i < dc->res_pool->pipe_count; i++) { - if (!context->res_ctx.pipe_ctx[i].stream) - continue; - if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid) - dcn20_adjust_freesync_v_startup( - &context->res_ctx.pipe_ctx[i].stream->timing, - &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start); - } - BW_VAL_TRACE_END_WATERMARKS(); goto validate_out; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c index 07adb614366e..fb21572750e8 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c @@ -293,6 +293,17 @@ static unsigned int micro_sec_to_vert_lines(unsigned int num_us, struct dc_crtc_ return num_lines; } +static unsigned int get_vertical_back_porch(struct dc_crtc_timing *timing) +{ + unsigned int v_active = 0, v_blank = 0, v_back_porch = 0; + + v_active = timing->v_border_top + timing->v_addressable + timing->v_border_bottom; + v_blank = timing->v_total - v_active; + v_back_porch = v_blank - timing->v_front_porch - timing->v_sync_width; + + return v_back_porch; +} + int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate) @@ -310,6 +321,7 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { struct dc_crtc_timing *timing; unsigned int num_lines = 0; + unsigned int v_back_porch = 0; if (!res_ctx->pipe_ctx[i].stream) continue; @@ -323,9 +335,16 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c else pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; + v_back_porch = get_vertical_back_porch(timing); + pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); - pipes[pipe_cnt].pipe.dest.vblank_nom = max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width); + // vblank_nom should not smaller than (VSync (timing->v_sync_width + v_back_porch) + 2) + // + 2 is because + // 1 -> VStartup_start should be 1 line before VSync + // 1 -> always reserve 1 line between start of vblank to vstartup signal + pipes[pipe_cnt].pipe.dest.vblank_nom = + max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2); pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblank_nom); if (pipe->plane_state && diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 027aec70c070..eaad1260bfd1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -65,6 +65,7 @@ struct resource_context; struct clk_bw_params; struct resource_funcs { + enum engine_id (*get_preferred_eng_id_dpia)(unsigned int dpia_index); void (*destroy)(struct resource_pool **pool); void (*link_init)(struct dc_link *link); struct panel_cntl*(*panel_cntl_create)( diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index 195ca9e52eda..0895742a3102 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -791,6 +791,10 @@ static bool construct_dpia(struct dc_link *link, /* Set dpia port index : 0 to number of dpia ports */ link->ddc_hw_inst = init_params->connector_index; + // Assign Dpia preferred eng_id + if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia) + link->dpia_preferred_eng_id = link->dc->res_pool->funcs->get_preferred_eng_id_dpia(link->ddc_hw_inst); + /* TODO: Create link encoder */ link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index dbd60811f95d..ef3a67409021 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -338,7 +338,9 @@ static void apply_below_the_range(struct core_freesync *core_freesync, * - Delta for CEIL: delta_from_mid_point_in_us_1 * - Delta for FLOOR: delta_from_mid_point_in_us_2 */ - if ((last_render_time_in_us / mid_point_frames_ceil) < in_out_vrr->min_duration_in_us) { + if (mid_point_frames_ceil && + (last_render_time_in_us / mid_point_frames_ceil) < + in_out_vrr->min_duration_in_us) { /* Check for out of range. * If using CEIL produces a value that is out of range, * then we are forced to use FLOOR. @@ -385,8 +387,9 @@ static void apply_below_the_range(struct core_freesync *core_freesync, /* Either we've calculated the number of frames to insert, * or we need to insert min duration frames */ - if (last_render_time_in_us / frames_to_insert < - in_out_vrr->min_duration_in_us){ + if (frames_to_insert && + (last_render_time_in_us / frames_to_insert) < + in_out_vrr->min_duration_in_us){ frames_to_insert -= (frames_to_insert > 1) ? 1 : 0; } diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index abe829bbd54a..67d7b7ee8a2a 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -240,6 +240,7 @@ enum DC_FEATURE_MASK { DC_DISABLE_LTTPR_DP2_0 = (1 << 6), //0x40, disabled by default DC_PSR_ALLOW_SMU_OPT = (1 << 7), //0x80, disabled by default DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), //0x100, disabled by default + DC_REPLAY_MASK = (1 << 9), //0x200, disabled by default for dcn < 3.1.4 }; enum DC_DEBUG_MASK { @@ -250,6 +251,7 @@ enum DC_DEBUG_MASK { DC_DISABLE_PSR = 0x10, DC_FORCE_SUBVP_MCLK_SWITCH = 0x20, DC_DISABLE_MPO = 0x40, + DC_DISABLE_REPLAY = 0x50, DC_ENABLE_DPIA_TRACE = 0x80, }; diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index e68c1e280322..fa7d6ced786f 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -3117,6 +3117,24 @@ enum atom_umc_config1_def { UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000, }; +struct atom_umc_info_v4_0 { + struct atom_common_table_header table_header; + uint32_t ucode_reserved[5]; + uint8_t umcip_min_ver; + uint8_t umcip_max_ver; + uint8_t vram_type; + uint8_t umc_config; + uint32_t mem_refclk_10khz; + uint32_t clk_reserved[4]; + uint32_t golden_reserved; + uint32_t umc_config1; + uint32_t reserved[2]; + uint8_t channel_num; + uint8_t channel_width; + uint8_t channel_reserve[2]; + uint8_t umc_info_reserved[16]; +}; + /* *************************************************************************** Data Table vram_info structure diff --git a/drivers/gpu/drm/amd/include/discovery.h b/drivers/gpu/drm/amd/include/discovery.h index f43e29722ef7..7a9d473d0917 100644 --- a/drivers/gpu/drm/amd/include/discovery.h +++ b/drivers/gpu/drm/amd/include/discovery.h @@ -30,7 +30,7 @@ #define GC_TABLE_ID 0x4347 #define HARVEST_TABLE_SIGNATURE 0x56524148 #define VCN_INFO_TABLE_ID 0x004E4356 -#define MALL_INFO_TABLE_ID 0x4D414C4C +#define MALL_INFO_TABLE_ID 0x4C4C414D typedef enum { @@ -280,6 +280,36 @@ struct gc_info_v2_0 { uint32_t gc_num_packer_per_sc; }; +struct gc_info_v2_1 { + struct gpu_info_header header; + + uint32_t gc_num_se; + uint32_t gc_num_cu_per_sh; + uint32_t gc_num_sh_per_se; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_tccs; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; + uint32_t gc_num_sc_per_se; + uint32_t gc_num_packer_per_sc; + /* new for v2_1 */ + uint32_t gc_num_tcp_per_sh; + uint32_t gc_tcp_size_per_cu; + uint32_t gc_num_sdp_interface; + uint32_t gc_num_cu_per_sqc; + uint32_t gc_instruction_cache_size_per_sqc; + uint32_t gc_scalar_data_cache_size_per_sqc; + uint32_t gc_tcc_size; +}; + typedef struct harvest_info_header { uint32_t signature; /* Table Signature */ uint32_t version; /* Table Version */ @@ -312,6 +342,12 @@ struct mall_info_v1_0 { uint32_t reserved[5]; }; +struct mall_info_v2_0 { + struct mall_info_header header; + uint32_t mall_size_per_umc; + uint32_t reserved[8]; +}; + #define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4 struct vcn_info_header { diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 8433f99f6667..3b5a56585c4b 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -31,12 +31,12 @@ #include <linux/types.h> #include <linux/bitmap.h> #include <linux/dma-fence.h> +#include "amdgpu_irq.h" +#include "amdgpu_gfx.h" struct pci_dev; struct amdgpu_device; -#define KGD_MAX_QUEUES 128 - struct kfd_dev; struct kgd_mem; @@ -68,7 +68,7 @@ struct kfd_cu_info { uint32_t wave_front_size; uint32_t max_scratch_slots_per_cu; uint32_t lds_size; - uint32_t cu_bitmap[4][4]; + uint32_t cu_bitmap[AMDGPU_MAX_GC_INSTANCES][4][4]; }; /* For getting GPU local memory information from KGD */ @@ -326,8 +326,7 @@ struct kfd2kgd_calls { uint32_t wait_times, uint32_t grace_period, uint32_t *reg_offset, - uint32_t *reg_data, - uint32_t inst); + uint32_t *reg_data); void (*get_cu_occupancy)(struct amdgpu_device *adev, int pasid, int *wave_cnt, int *max_waves_per_cu, uint32_t inst); void (*program_trap_handler_settings)(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 5b1d73b00ef7..8bb2da13826f 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -2040,6 +2040,7 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_ case IP_VERSION(11, 0, 0): case IP_VERSION(11, 0, 1): case IP_VERSION(11, 0, 2): + case IP_VERSION(11, 0, 3): *states = ATTR_STATE_SUPPORTED; break; default: @@ -3311,8 +3312,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, (gc_ver != IP_VERSION(9, 4, 3)) && (attr == &sensor_dev_attr_temp2_input.dev_attr.attr || attr == &sensor_dev_attr_temp2_label.dev_attr.attr || + attr == &sensor_dev_attr_temp2_crit.dev_attr.attr || attr == &sensor_dev_attr_temp3_input.dev_attr.attr || - attr == &sensor_dev_attr_temp3_label.dev_attr.attr)) + attr == &sensor_dev_attr_temp3_label.dev_attr.attr || + attr == &sensor_dev_attr_temp3_crit.dev_attr.attr)) return 0; /* hotspot temperature for gc 9,4,3*/ @@ -3324,9 +3327,7 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, /* only SOC15 dGPUs support hotspot and mem temperatures */ if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0) || (gc_ver == IP_VERSION(9, 4, 3))) && - (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr || - attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr || - attr == &sensor_dev_attr_temp3_crit.dev_attr.attr || + (attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr || attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr || attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr || attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr || @@ -3471,6 +3472,9 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a size = sizeof(uint32_t); if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&query, &size)) seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff); + size = sizeof(uint32_t); + if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&query, &size)) + seq_printf(m, "\t%u.%u W (current GPU)\n", query >> 8, query & 0xff); size = sizeof(value); seq_printf(m, "\n"); diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 95eb8a5eb54f..5a52098bcf16 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -1031,10 +1031,7 @@ struct pptable_funcs { enum smu_feature_mask mask); /** - * @notify_display_change: Enable fast memory clock switching. - * - * Allows for fine grained memory clock switching but has more stringent - * timing requirements. + * @notify_display_change: General interface call to let SMU know about DC change */ int (*notify_display_change)(struct smu_context *smu); diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h index 10cff75b44d5..e2ee855c7748 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h @@ -138,7 +138,10 @@ #define PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel 0x4A #define PPSMC_MSG_SetPriorityDeltaGain 0x4B #define PPSMC_MSG_AllowIHHostInterrupt 0x4C -#define PPSMC_Message_Count 0x4D + +#define PPSMC_MSG_DALNotPresent 0x4E + +#define PPSMC_Message_Count 0x4F //Debug Dump Message #define DEBUGSMC_MSG_TestMessage 0x1 diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h index 252aef190c5c..9be4051c0865 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h @@ -123,7 +123,7 @@ typedef enum { VOLTAGE_GUARDBAND_COUNT } GFX_GUARDBAND_e; -#define SMU_METRICS_TABLE_VERSION 0x5 +#define SMU_METRICS_TABLE_VERSION 0x7 typedef struct __attribute__((packed, aligned(4))) { uint32_t AccumulationCounter; @@ -198,7 +198,7 @@ typedef struct __attribute__((packed, aligned(4))) { uint32_t SocketThmResidencyAcc; uint32_t VrThmResidencyAcc; uint32_t HbmThmResidencyAcc; - uint32_t spare; + uint32_t GfxLockXCDMak; // New Items at end to maintain driver compatibility uint32_t GfxclkFrequency[8]; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h index ae4f44c4b877..70a4a717fd3f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h @@ -83,13 +83,27 @@ #define PPSMC_MSG_GetMinGfxDpmFreq 0x32 #define PPSMC_MSG_GetMaxGfxDpmFreq 0x33 #define PPSMC_MSG_PrepareForDriverUnload 0x34 -#define PPSMC_Message_Count 0x35 +#define PPSMC_MSG_ReadThrottlerLimit 0x35 +#define PPSMC_MSG_QueryValidMcaCount 0x36 +#define PPSMC_MSG_McaBankDumpDW 0x37 +#define PPSMC_MSG_GetCTFLimit 0x38 +#define PPSMC_Message_Count 0x39 //PPSMC Reset Types for driver msg argument #define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x1 #define PPSMC_RESET_TYPE_DRIVER_MODE_2_RESET 0x2 #define PPSMC_RESET_TYPE_DRIVER_MODE_3_RESET 0x3 +//PPSMC Reset Types for driver msg argument +#define PPSMC_THROTTLING_LIMIT_TYPE_SOCKET 0x1 +#define PPSMC_THROTTLING_LIMIT_TYPE_HBM 0x2 + +//CTF/Throttle Limit types +#define PPSMC_AID_THM_TYPE 0x1 +#define PPSMC_CCD_THM_TYPE 0x2 +#define PPSMC_XCD_THM_TYPE 0x3 +#define PPSMC_HBM_THM_TYPE 0x4 + typedef uint32_t PPSMC_Result; typedef uint32_t PPSMC_MSG; diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index 297b70b9388f..e57265cf637c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -84,6 +84,7 @@ __SMU_DUMMY_MAP(SetTjMax), \ __SMU_DUMMY_MAP(SetFanTemperatureTarget), \ __SMU_DUMMY_MAP(PrepareMp1ForUnload), \ + __SMU_DUMMY_MAP(GetCTFLimit), \ __SMU_DUMMY_MAP(DramLogSetDramAddrHigh), \ __SMU_DUMMY_MAP(DramLogSetDramAddrLow), \ __SMU_DUMMY_MAP(DramLogSetDramSize), \ @@ -245,7 +246,8 @@ __SMU_DUMMY_MAP(AllowGpo), \ __SMU_DUMMY_MAP(Mode2Reset), \ __SMU_DUMMY_MAP(RequestI2cTransaction), \ - __SMU_DUMMY_MAP(GetMetricsTable), + __SMU_DUMMY_MAP(GetMetricsTable), \ + __SMU_DUMMY_MAP(DALNotPresent), #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(type) SMU_MSG_##type diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 4bb289f9b4b8..da2860da6018 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -2082,36 +2082,41 @@ static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context return ret; } +#define MAX(a, b) ((a) > (b) ? (a) : (b)) + static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu, uint32_t pcie_gen_cap, uint32_t pcie_width_cap) { struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; struct smu_11_0_pcie_table *pcie_table = &dpm_context->dpm_tables.pcie_table; - u32 smu_pcie_arg; + uint8_t *table_member1, *table_member2; + uint32_t min_gen_speed, max_gen_speed; + uint32_t min_lane_width, max_lane_width; + uint32_t smu_pcie_arg; int ret, i; - /* PCIE gen speed and lane width override */ - if (!amdgpu_device_pcie_dynamic_switching_supported()) { - if (pcie_table->pcie_gen[NUM_LINK_LEVELS - 1] < pcie_gen_cap) - pcie_gen_cap = pcie_table->pcie_gen[NUM_LINK_LEVELS - 1]; + GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1); + GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2); - if (pcie_table->pcie_lane[NUM_LINK_LEVELS - 1] < pcie_width_cap) - pcie_width_cap = pcie_table->pcie_lane[NUM_LINK_LEVELS - 1]; + min_gen_speed = MAX(0, table_member1[0]); + max_gen_speed = MIN(pcie_gen_cap, table_member1[1]); + min_gen_speed = min_gen_speed > max_gen_speed ? + max_gen_speed : min_gen_speed; + min_lane_width = MAX(1, table_member2[0]); + max_lane_width = MIN(pcie_width_cap, table_member2[1]); + min_lane_width = min_lane_width > max_lane_width ? + max_lane_width : min_lane_width; - /* Force all levels to use the same settings */ - for (i = 0; i < NUM_LINK_LEVELS; i++) { - pcie_table->pcie_gen[i] = pcie_gen_cap; - pcie_table->pcie_lane[i] = pcie_width_cap; - } + if (!amdgpu_device_pcie_dynamic_switching_supported()) { + pcie_table->pcie_gen[0] = max_gen_speed; + pcie_table->pcie_lane[0] = max_lane_width; } else { - for (i = 0; i < NUM_LINK_LEVELS; i++) { - if (pcie_table->pcie_gen[i] > pcie_gen_cap) - pcie_table->pcie_gen[i] = pcie_gen_cap; - if (pcie_table->pcie_lane[i] > pcie_width_cap) - pcie_table->pcie_lane[i] = pcie_width_cap; - } + pcie_table->pcie_gen[0] = min_gen_speed; + pcie_table->pcie_lane[0] = min_lane_width; } + pcie_table->pcie_gen[1] = max_gen_speed; + pcie_table->pcie_lane[1] = max_lane_width; for (i = 0; i < NUM_LINK_LEVELS; i++) { smu_pcie_arg = (i << 16 | diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index f1282fc4b90a..0232adb95df3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -837,12 +837,8 @@ int smu_v13_0_notify_display_change(struct smu_context *smu) { int ret = 0; - if (!smu->pm_enabled) - return ret; - - if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && - smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL); + if (!amdgpu_device_has_dc_support(smu->adev)) + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DALNotPresent, NULL); return ret; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index 8b7403ba89d7..3903a47669e4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -162,6 +162,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = MSG_MAP(AllowGpo, PPSMC_MSG_SetGpoAllow, 0), MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0), MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0), + MSG_MAP(DALNotPresent, PPSMC_MSG_DALNotPresent, 0), }; static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = { @@ -2687,6 +2688,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { .send_hbm_bad_channel_flag = smu_v13_0_0_send_bad_mem_channel_flag, .gpo_control = smu_v13_0_gpo_control, .get_ecc_info = smu_v13_0_0_get_ecc_info, + .notify_display_change = smu_v13_0_notify_display_change, }; void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 6ed9cd0a1e4e..de80e191a92c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -132,6 +132,7 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxClk, 0), MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0), MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareForDriverUnload, 0), + MSG_MAP(GetCTFLimit, PPSMC_MSG_GetCTFLimit, 0), }; static const struct cmn2asic_mapping smu_v13_0_6_clk_map[SMU_CLK_COUNT] = { @@ -335,7 +336,7 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu) /* Store one-time values in driver PPTable */ if (!pptable->Init) { - while (retry--) { + while (--retry) { ret = smu_v13_0_6_get_metrics_table(smu, NULL, true); if (ret) return ret; @@ -2081,6 +2082,55 @@ out: return ret; } +static int smu_v13_0_6_get_thermal_temperature_range(struct smu_context *smu, + struct smu_temperature_range *range) +{ + struct amdgpu_device *adev = smu->adev; + u32 aid_temp, xcd_temp, mem_temp; + uint32_t smu_version; + u32 ccd_temp = 0; + int ret; + + if (amdgpu_sriov_vf(smu->adev)) + return 0; + + if (!range) + return -EINVAL; + + /*Check smu version, GetCtfLimit message only supported for smu version 85.69 or higher */ + smu_cmn_get_smc_version(smu, NULL, &smu_version); + if (smu_version < 0x554500) + return 0; + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit, + PPSMC_AID_THM_TYPE, &aid_temp); + if (ret) + goto failed; + + if (adev->flags & AMD_IS_APU) { + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit, + PPSMC_CCD_THM_TYPE, &ccd_temp); + if (ret) + goto failed; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit, + PPSMC_XCD_THM_TYPE, &xcd_temp); + if (ret) + goto failed; + + range->hotspot_crit_max = max3(aid_temp, xcd_temp, ccd_temp) * + SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit, + PPSMC_HBM_THM_TYPE, &mem_temp); + if (ret) + goto failed; + + range->mem_crit_max = mem_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; +failed: + return ret; +} + static int smu_v13_0_6_mode1_reset(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; @@ -2108,8 +2158,7 @@ static int smu_v13_0_6_mode1_reset(struct smu_context *smu) static bool smu_v13_0_6_is_mode1_reset_supported(struct smu_context *smu) { - /* TODO: Enable this when FW support is added */ - return false; + return true; } static bool smu_v13_0_6_is_mode2_reset_supported(struct smu_context *smu) @@ -2177,6 +2226,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, .get_gpu_metrics = smu_v13_0_6_get_gpu_metrics, + .get_thermal_temperature_range = smu_v13_0_6_get_thermal_temperature_range, .mode1_reset_is_support = smu_v13_0_6_is_mode1_reset_supported, .mode2_reset_is_support = smu_v13_0_6_is_mode2_reset_supported, .mode1_reset = smu_v13_0_6_mode1_reset, diff --git a/drivers/gpu/drm/ci/arm.config b/drivers/gpu/drm/ci/arm.config new file mode 100644 index 000000000000..871f4de063ad --- /dev/null +++ b/drivers/gpu/drm/ci/arm.config @@ -0,0 +1,69 @@ +CONFIG_LOCALVERSION_AUTO=y +CONFIG_DEBUG_KERNEL=y + +CONFIG_CRYPTO_ZSTD=y +CONFIG_ZRAM_MEMORY_TRACKING=y +CONFIG_ZRAM_WRITEBACK=y +CONFIG_ZRAM=y +CONFIG_ZSMALLOC_STAT=y + +# abootimg with a 'dummy' rootfs fails with root=/dev/nfs +CONFIG_BLK_DEV_INITRD=n + +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_DEVFREQ_GOV_PASSIVE=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y + +CONFIG_DRM=y +CONFIG_DRM_ETNAVIV=y +CONFIG_DRM_ROCKCHIP=y +CONFIG_DRM_PANFROST=y +CONFIG_DRM_LIMA=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_PWM_CROS_EC=y +CONFIG_BACKLIGHT_PWM=y + +CONFIG_ROCKCHIP_CDN_DP=n + +CONFIG_SPI_ROCKCHIP=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_DP=y +CONFIG_DWMAC_ROCKCHIP=y + +CONFIG_MFD_RK808=y +CONFIG_REGULATOR_RK808=y +CONFIG_RTC_DRV_RK808=y +CONFIG_COMMON_CLK_RK808=y + +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR=y + +CONFIG_REGULATOR_VCTRL=y + +CONFIG_KASAN=n +CONFIG_KASAN_INLINE=n +CONFIG_STACKTRACE=n + +CONFIG_TMPFS=y + +CONFIG_PROVE_LOCKING=n +CONFIG_DEBUG_LOCKDEP=n +CONFIG_SOFTLOCKUP_DETECTOR=n +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=n + +CONFIG_FW_LOADER_COMPRESS=y + +CONFIG_USB_USBNET=y +CONFIG_NETDEVICES=y +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_RTL8152=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_SMSC95XX=y + +# TK1 +CONFIG_ARM_TEGRA_DEVFREQ=y + +# 32-bit build failure +CONFIG_DRM_MSM=n diff --git a/drivers/gpu/drm/ci/arm64.config b/drivers/gpu/drm/ci/arm64.config new file mode 100644 index 000000000000..817e18ddfd4f --- /dev/null +++ b/drivers/gpu/drm/ci/arm64.config @@ -0,0 +1,199 @@ +CONFIG_LOCALVERSION_AUTO=y +CONFIG_DEBUG_KERNEL=y + +CONFIG_CRYPTO_ZSTD=y +CONFIG_ZRAM_MEMORY_TRACKING=y +CONFIG_ZRAM_WRITEBACK=y +CONFIG_ZRAM=y +CONFIG_ZSMALLOC_STAT=y + +# abootimg with a 'dummy' rootfs fails with root=/dev/nfs +CONFIG_BLK_DEV_INITRD=n + +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_DEVFREQ_GOV_PASSIVE=y + +CONFIG_DRM=y +CONFIG_DRM_ROCKCHIP=y +CONFIG_DRM_PANFROST=y +CONFIG_DRM_LIMA=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_EDP=y +CONFIG_DRM_MSM=y +CONFIG_DRM_ETNAVIV=y +CONFIG_DRM_I2C_ADV7511=y +CONFIG_PWM_CROS_EC=y +CONFIG_BACKLIGHT_PWM=y + +CONFIG_ROCKCHIP_CDN_DP=n + +CONFIG_SPI_ROCKCHIP=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_DP=y +CONFIG_DWMAC_ROCKCHIP=y +CONFIG_STMMAC_ETH=y +CONFIG_TYPEC_FUSB302=y +CONFIG_TYPEC=y +CONFIG_TYPEC_TCPM=y + +# MSM platform bits + +# For CONFIG_QCOM_LMH +CONFIG_OF=y + +CONFIG_ARM_SMMU_QCOM=y +CONFIG_QCOM_COMMAND_DB=y +CONFIG_QCOM_RPMHPD=y +CONFIG_QCOM_RPMPD=y +CONFIG_QCOM_OCMEM=y +CONFIG_SDM_GPUCC_845=y +CONFIG_SDM_VIDEOCC_845=y +CONFIG_SDM_DISPCC_845=y +CONFIG_SDM_LPASSCC_845=y +CONFIG_SDM_CAMCC_845=y +CONFIG_RESET_QCOM_PDC=y +CONFIG_DRM_TI_SN65DSI86=y +CONFIG_I2C_QCOM_GENI=y +CONFIG_SPI_QCOM_GENI=y +CONFIG_PHY_QCOM_QUSB2=y +CONFIG_PHY_QCOM_QMP=y +CONFIG_MSM_GCC_8996=y +CONFIG_QCOM_CLK_APCC_MSM8996=y +CONFIG_QCOM_LLCC=y +CONFIG_QCOM_LMH=y +CONFIG_QCOM_SPMI_TEMP_ALARM=y +CONFIG_QCOM_WDT=y +CONFIG_POWER_RESET_QCOM_PON=y +CONFIG_RTC_DRV_PM8XXX=y +CONFIG_INTERCONNECT=y +CONFIG_INTERCONNECT_QCOM=y +CONFIG_INTERCONNECT_QCOM_MSM8996=y +CONFIG_INTERCONNECT_QCOM_SDM845=y +CONFIG_INTERCONNECT_QCOM_MSM8916=y +CONFIG_INTERCONNECT_QCOM_MSM8996=y +CONFIG_INTERCONNECT_QCOM_OSM_L3=y +CONFIG_INTERCONNECT_QCOM_SC7180=y +CONFIG_INTERCONNECT_QCOM_SM8350=y +CONFIG_CRYPTO_DEV_QCOM_RNG=y +CONFIG_SC_DISPCC_7180=y +CONFIG_SC_GPUCC_7180=y +CONFIG_SM_GPUCC_8350=y +CONFIG_QCOM_SPMI_ADC5=y +CONFIG_DRM_PARADE_PS8640=y +CONFIG_DRM_LONTIUM_LT9611UXC=y +CONFIG_PHY_QCOM_USB_HS=y +CONFIG_QCOM_GPI_DMA=y +CONFIG_USB_ONBOARD_HUB=y +CONFIG_NVMEM_QCOM_QFPROM=y +CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y + + +# db410c ethernet +CONFIG_USB_RTL8152=y +# db820c ethernet +CONFIG_ATL1C=y +# Chromebooks ethernet +CONFIG_USB_ONBOARD_HUB=y +# 888 HDK ethernet +CONFIG_USB_LAN78XX=y + +CONFIG_ARCH_ALPINE=n +CONFIG_ARCH_BCM2835=y +CONFIG_ARCH_BCM_IPROC=n +CONFIG_ARCH_BERLIN=n +CONFIG_ARCH_BRCMSTB=n +CONFIG_ARCH_EXYNOS=n +CONFIG_ARCH_K3=n +CONFIG_ARCH_LAYERSCAPE=n +CONFIG_ARCH_LG1K=n +CONFIG_ARCH_HISI=n +CONFIG_ARCH_MVEBU=n +CONFIG_ARCH_SEATTLE=n +CONFIG_ARCH_SYNQUACER=n +CONFIG_ARCH_RENESAS=n +CONFIG_ARCH_R8A774A1=n +CONFIG_ARCH_R8A774C0=n +CONFIG_ARCH_R8A7795=n +CONFIG_ARCH_R8A7796=n +CONFIG_ARCH_R8A77965=n +CONFIG_ARCH_R8A77970=n +CONFIG_ARCH_R8A77980=n +CONFIG_ARCH_R8A77990=n +CONFIG_ARCH_R8A77995=n +CONFIG_ARCH_STRATIX10=n +CONFIG_ARCH_TEGRA=n +CONFIG_ARCH_SPRD=n +CONFIG_ARCH_THUNDER=n +CONFIG_ARCH_THUNDER2=n +CONFIG_ARCH_UNIPHIER=n +CONFIG_ARCH_VEXPRESS=n +CONFIG_ARCH_XGENE=n +CONFIG_ARCH_ZX=n +CONFIG_ARCH_ZYNQMP=n + +# Strip out some stuff we don't need for graphics testing, to reduce +# the build. +CONFIG_CAN=n +CONFIG_WIRELESS=n +CONFIG_RFKILL=n +CONFIG_WLAN=n + +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR=y + +CONFIG_REGULATOR_VCTRL=y + +CONFIG_KASAN=n +CONFIG_KASAN_INLINE=n +CONFIG_STACKTRACE=n + +CONFIG_TMPFS=y + +CONFIG_PROVE_LOCKING=n +CONFIG_DEBUG_LOCKDEP=n +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y + +CONFIG_DETECT_HUNG_TASK=y + +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_USER_HELPER=n + +CONFIG_USB_USBNET=y +CONFIG_NETDEVICES=y +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_RTL8152=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_SMSC95XX=y + +# For amlogic +CONFIG_MESON_GXL_PHY=y +CONFIG_MDIO_BUS_MUX_MESON_G12A=y +CONFIG_DRM_MESON=y + +# For Mediatek +CONFIG_DRM_MEDIATEK=y +CONFIG_PWM_MEDIATEK=y +CONFIG_DRM_MEDIATEK_HDMI=y +CONFIG_GNSS=y +CONFIG_GNSS_MTK_SERIAL=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MTK=y +CONFIG_MTK_DEVAPC=y +CONFIG_PWM_MTK_DISP=y +CONFIG_MTK_CMDQ=y + +# For nouveau. Note that DRM must be a module so that it's loaded after NFS is up to provide the firmware. +CONFIG_ARCH_TEGRA=y +CONFIG_DRM_NOUVEAU=m +CONFIG_DRM_TEGRA=m +CONFIG_R8169=y +CONFIG_STAGING=y +CONFIG_DRM_TEGRA_STAGING=y +CONFIG_TEGRA_HOST1X=y +CONFIG_ARM_TEGRA_DEVFREQ=y +CONFIG_TEGRA_SOCTHERM=y +CONFIG_DRM_TEGRA_DEBUG=y +CONFIG_PWM_TEGRA=y diff --git a/drivers/gpu/drm/ci/build-igt.sh b/drivers/gpu/drm/ci/build-igt.sh new file mode 100644 index 000000000000..500fa4f5c30a --- /dev/null +++ b/drivers/gpu/drm/ci/build-igt.sh @@ -0,0 +1,35 @@ +#!/bin/bash +# SPDX-License-Identifier: MIT + +set -ex + +git clone https://gitlab.freedesktop.org/drm/igt-gpu-tools.git --single-branch --no-checkout +cd igt-gpu-tools +git checkout $IGT_VERSION + +if [[ "$KERNEL_ARCH" = "arm" ]]; then + . ../.gitlab-ci/container/create-cross-file.sh armhf + EXTRA_MESON_ARGS="--cross-file /cross_file-armhf.txt" +fi + +MESON_OPTIONS="-Doverlay=disabled \ + -Dchamelium=disabled \ + -Dvalgrind=disabled \ + -Dman=enabled \ + -Dtests=enabled \ + -Drunner=enabled \ + -Dlibunwind=enabled \ + -Dprefix=/igt" + +mkdir -p /igt +meson build $MESON_OPTIONS $EXTRA_MESON_ARGS +ninja -C build -j${FDO_CI_CONCURRENT:-4} || ninja -C build -j 1 +ninja -C build install + +mkdir -p artifacts/ +tar -cf artifacts/igt.tar /igt + +# Pass needed files to the test stage +S3_ARTIFACT_NAME="igt.tar.gz" +gzip -c artifacts/igt.tar > ${S3_ARTIFACT_NAME} +ci-fairy s3cp --token-file "${CI_JOB_JWT_FILE}" ${S3_ARTIFACT_NAME} https://${PIPELINE_ARTIFACTS_BASE}/${KERNEL_ARCH}/${S3_ARTIFACT_NAME} diff --git a/drivers/gpu/drm/ci/build.sh b/drivers/gpu/drm/ci/build.sh new file mode 100644 index 000000000000..7b014287a041 --- /dev/null +++ b/drivers/gpu/drm/ci/build.sh @@ -0,0 +1,157 @@ +#!/bin/bash +# SPDX-License-Identifier: MIT + +set -ex + +# Clean up stale rebases that GitLab might not have removed when reusing a checkout dir +rm -rf .git/rebase-apply + +. .gitlab-ci/container/container_pre_build.sh + +# libssl-dev was uninstalled because it was considered an ephemeral package +apt-get update +apt-get install -y libssl-dev + +if [[ "$KERNEL_ARCH" = "arm64" ]]; then + GCC_ARCH="aarch64-linux-gnu" + DEBIAN_ARCH="arm64" + DEVICE_TREES="arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dtb" + DEVICE_TREES+=" arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dtb" + DEVICE_TREES+=" arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dtb" + DEVICE_TREES+=" arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dtb" + DEVICE_TREES+=" arch/arm64/boot/dts/qcom/apq8016-sbc.dtb" + DEVICE_TREES+=" arch/arm64/boot/dts/qcom/apq8096-db820c.dtb" + DEVICE_TREES+=" arch/arm64/boot/dts/amlogic/meson-g12b-a311d-khadas-vim3.dtb" + DEVICE_TREES+=" arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtb" + DEVICE_TREES+=" arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb" + DEVICE_TREES+=" arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dtb" + DEVICE_TREES+=" arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dtb" +elif [[ "$KERNEL_ARCH" = "arm" ]]; then + GCC_ARCH="arm-linux-gnueabihf" + DEBIAN_ARCH="armhf" + DEVICE_TREES="arch/arm/boot/dts/rockchip/rk3288-veyron-jaq.dtb" + DEVICE_TREES+=" arch/arm/boot/dts/allwinner/sun8i-h3-libretech-all-h3-cc.dtb" + DEVICE_TREES+=" arch/arm/boot/dts/nxp/imx/imx6q-cubox-i.dtb" + apt-get install -y libssl-dev:armhf +else + GCC_ARCH="x86_64-linux-gnu" + DEBIAN_ARCH="x86_64" + DEVICE_TREES="" +fi + +export ARCH=${KERNEL_ARCH} +export CROSS_COMPILE="${GCC_ARCH}-" + +# The kernel doesn't like the gold linker (or the old lld in our debians). +# Sneak in some override symlinks during kernel build until we can update +# debian. +mkdir -p ld-links +for i in /usr/bin/*-ld /usr/bin/ld; do + i=$(basename $i) + ln -sf /usr/bin/$i.bfd ld-links/$i +done + +NEWPATH=$(pwd)/ld-links +export PATH=$NEWPATH:$PATH + +git config --global user.email "fdo@example.com" +git config --global user.name "freedesktop.org CI" +git config --global pull.rebase true + +# Try to merge fixes from target repo +if [ "$(git ls-remote --exit-code --heads ${UPSTREAM_REPO} ${TARGET_BRANCH}-external-fixes)" ]; then + git pull ${UPSTREAM_REPO} ${TARGET_BRANCH}-external-fixes +fi + +# Try to merge fixes from local repo if this isn't a merge request +if [ -z "$CI_MERGE_REQUEST_PROJECT_PATH" ]; then + if [ "$(git ls-remote --exit-code --heads origin ${TARGET_BRANCH}-external-fixes)" ]; then + git pull origin ${TARGET_BRANCH}-external-fixes + fi +fi + +for opt in $ENABLE_KCONFIGS; do + echo CONFIG_$opt=y >> drivers/gpu/drm/ci/${KERNEL_ARCH}.config +done +for opt in $DISABLE_KCONFIGS; do + echo CONFIG_$opt=n >> drivers/gpu/drm/ci/${KERNEL_ARCH}.config +done + +if [[ -n "${MERGE_FRAGMENT}" ]]; then + ./scripts/kconfig/merge_config.sh ${DEFCONFIG} drivers/gpu/drm/ci/${MERGE_FRAGMENT} +else + make `basename ${DEFCONFIG}` +fi + +make ${KERNEL_IMAGE_NAME} + +mkdir -p /lava-files/ +for image in ${KERNEL_IMAGE_NAME}; do + cp arch/${KERNEL_ARCH}/boot/${image} /lava-files/. +done + +if [[ -n ${DEVICE_TREES} ]]; then + make dtbs + cp ${DEVICE_TREES} /lava-files/. +fi + +make modules +mkdir -p install/modules/ +INSTALL_MOD_PATH=install/modules/ make modules_install + +if [[ ${DEBIAN_ARCH} = "arm64" ]]; then + make Image.lzma + mkimage \ + -f auto \ + -A arm \ + -O linux \ + -d arch/arm64/boot/Image.lzma \ + -C lzma\ + -b arch/arm64/boot/dts/qcom/sdm845-cheza-r3.dtb \ + /lava-files/cheza-kernel + KERNEL_IMAGE_NAME+=" cheza-kernel" + + # Make a gzipped copy of the Image for db410c. + gzip -k /lava-files/Image + KERNEL_IMAGE_NAME+=" Image.gz" +fi + +# Pass needed files to the test stage +mkdir -p install +cp -rfv .gitlab-ci/* install/. +cp -rfv install/common install/ci-common +cp -rfv drivers/gpu/drm/ci/* install/. + +. .gitlab-ci/container/container_post_build.sh + +if [[ "$UPLOAD_TO_MINIO" = "1" ]]; then + xz -7 -c -T${FDO_CI_CONCURRENT:-4} vmlinux > /lava-files/vmlinux.xz + FILES_TO_UPLOAD="$KERNEL_IMAGE_NAME vmlinux.xz" + + if [[ -n $DEVICE_TREES ]]; then + FILES_TO_UPLOAD="$FILES_TO_UPLOAD $(basename -a $DEVICE_TREES)" + fi + + for f in $FILES_TO_UPLOAD; do + ci-fairy s3cp --token-file "${CI_JOB_JWT_FILE}" /lava-files/$f \ + https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}/$f + done + + S3_ARTIFACT_NAME="kernel-files.tar.zst" + tar --zstd -cf $S3_ARTIFACT_NAME install + ci-fairy s3cp --token-file "${CI_JOB_JWT_FILE}" ${S3_ARTIFACT_NAME} https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}/${S3_ARTIFACT_NAME} + + echo "Download vmlinux.xz from https://${PIPELINE_ARTIFACTS_BASE}/${DEBIAN_ARCH}/vmlinux.xz" +fi + +mkdir -p artifacts/install/lib +mv install/* artifacts/install/. +rm -rf artifacts/install/modules +ln -s common artifacts/install/ci-common + +for image in ${KERNEL_IMAGE_NAME}; do + cp /lava-files/$image artifacts/install/. +done + +tar -C artifacts -cf artifacts/install.tar install +rm -rf artifacts/install diff --git a/drivers/gpu/drm/ci/build.yml b/drivers/gpu/drm/ci/build.yml new file mode 100644 index 000000000000..e6503f1c5927 --- /dev/null +++ b/drivers/gpu/drm/ci/build.yml @@ -0,0 +1,110 @@ +.build: + extends: + - .build-rules + stage: build + artifacts: + paths: + - artifacts + script: + - FDO_CI_CONCURRENT=${FDO_CI_CONCURRENT} bash drivers/gpu/drm/ci/build.sh + +.build:arm32: + extends: + - .build + - .use-debian/arm64_build + tags: + - aarch64 + variables: + DEFCONFIG: "arch/arm/configs/multi_v7_defconfig" + KERNEL_IMAGE_NAME: "zImage" + KERNEL_ARCH: "arm" + +.build:arm64: + extends: + - .build + - .use-debian/arm64_build + tags: + - aarch64 + variables: + DEFCONFIG: "arch/arm64/configs/defconfig" + KERNEL_IMAGE_NAME: "Image" + KERNEL_ARCH: "arm64" + +.build:x86_64: + extends: + - .build + - .use-debian/x86_64_build + variables: + DEFCONFIG: "arch/x86/configs/x86_64_defconfig" + KERNEL_IMAGE_NAME: "bzImage" + KERNEL_ARCH: "x86_64" + + +# Build IGT for testing on devices + +igt:arm32: + extends: .build:arm32 + script: + - FDO_CI_CONCURRENT=${FDO_CI_CONCURRENT} bash drivers/gpu/drm/ci/build-igt.sh + +igt:arm64: + extends: .build:arm64 + script: + - FDO_CI_CONCURRENT=${FDO_CI_CONCURRENT} bash drivers/gpu/drm/ci/build-igt.sh + +igt:x86_64: + extends: .build:x86_64 + script: + - FDO_CI_CONCURRENT=${FDO_CI_CONCURRENT} bash drivers/gpu/drm/ci/build-igt.sh + +# Build kernels for testing on devices + +testing:arm32: + extends: .build:arm32 + variables: + # Would be good to have DEBUG_KMEMLEAK, but it doesn't work well with any of + # PROVE_LOCKING and KASAN as of 5.17. + # + # db410c and db820c don't boot with KASAN_INLINE, probably due to the kernel + # becoming too big for their bootloaders. + ENABLE_KCONFIGS: "PROVE_LOCKING DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT" + UPLOAD_TO_MINIO: 1 + MERGE_FRAGMENT: arm.config + +testing:arm64: + extends: .build:arm64 + variables: + # Would be good to have DEBUG_KMEMLEAK, but it doesn't work well with any of + # PROVE_LOCKING and KASAN as of 5.17. + # + # db410c and db820c don't boot with KASAN_INLINE, probably due to the kernel + # becoming too big for their bootloaders. + ENABLE_KCONFIGS: "PROVE_LOCKING DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT" + UPLOAD_TO_MINIO: 1 + MERGE_FRAGMENT: arm64.config + +testing:x86_64: + extends: .build:x86_64 + variables: + # Would be good to have DEBUG_KMEMLEAK, but it doesn't work well with any of + # PROVE_LOCKING and KASAN as of 5.17. + # + # db410c and db820c don't boot with KASAN_INLINE, probably due to the kernel + # becoming too big for their bootloaders. + ENABLE_KCONFIGS: "PROVE_LOCKING DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT" + UPLOAD_TO_MINIO: 1 + MERGE_FRAGMENT: x86_64.config + + +# Jobs for build-testing different configurations + +build:arm32: + extends: .build:arm32 + +build-nodebugfs:arm64: + extends: .build:arm64 + variables: + DISABLE_KCONFIGS: "DEBUG_FS" + +build:x86_64: + extends: .build:x86_64 diff --git a/drivers/gpu/drm/ci/check-patch.py b/drivers/gpu/drm/ci/check-patch.py new file mode 100755 index 000000000000..a5f399a20e25 --- /dev/null +++ b/drivers/gpu/drm/ci/check-patch.py @@ -0,0 +1,57 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: GPL-2.0-or-later +# +# check-patch.py: run checkpatch.pl across all commits in a branch +# +# Based on qemu/.gitlab-ci.d/check-patch.py +# +# Copyright (C) 2020 Red Hat, Inc. +# Copyright (C) 2022 Collabora Ltd. + +import os +import os.path +import sys +import subprocess + +repourl = "https://gitlab.freedesktop.org/%s.git" % os.environ["CI_MERGE_REQUEST_PROJECT_PATH"] + +# GitLab CI environment does not give us any direct info about the +# base for the user's branch. We thus need to figure out a common +# ancestor between the user's branch and current git master. +os.environ["GIT_DEPTH"] = "1000" +subprocess.call(["git", "remote", "remove", "check-patch"], stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL) +subprocess.check_call(["git", "remote", "add", "check-patch", repourl]) +subprocess.check_call(["git", "fetch", "check-patch", os.environ["CI_MERGE_REQUEST_TARGET_BRANCH_NAME"]], + stdout=subprocess.DEVNULL, + stderr=subprocess.DEVNULL) + +ancestor = subprocess.check_output(["git", "merge-base", + "check-patch/%s" % os.environ["CI_MERGE_REQUEST_TARGET_BRANCH_NAME"], "HEAD"], + universal_newlines=True) + +ancestor = ancestor.strip() + +log = subprocess.check_output(["git", "log", "--format=%H %s", + ancestor + "..."], + universal_newlines=True) + +subprocess.check_call(["git", "remote", "rm", "check-patch"]) + +if log == "": + print("\nNo commits since %s, skipping checks\n" % ancestor) + sys.exit(0) + +errors = False + +print("\nChecking all commits since %s...\n" % ancestor, flush=True) + +ret = subprocess.run(["scripts/checkpatch.pl", + "--terse", + "--types", os.environ["CHECKPATCH_TYPES"], + "--git", ancestor + "..."]) + +if ret.returncode != 0: + print(" ❌ FAIL one or more commits failed scripts/checkpatch.pl") + sys.exit(1) + +sys.exit(0) diff --git a/drivers/gpu/drm/ci/container.yml b/drivers/gpu/drm/ci/container.yml new file mode 100644 index 000000000000..9764e7921a4f --- /dev/null +++ b/drivers/gpu/drm/ci/container.yml @@ -0,0 +1,65 @@ +.container: + variables: + CI_REPOSITORY_URL: ${DRM_CI_PROJECT_URL}.git # So ci-templates clones drm-ci instead of the repo to test + CI_COMMIT_SHA: ${DRM_CI_COMMIT_SHA} + +debian/x86_64_build-base: + variables: + EXTRA_LOCAL_PACKAGES: "libcairo-dev libdw-dev libjson-c-dev libkmod2 libkmod-dev libpciaccess-dev libproc2-dev libudev-dev libunwind-dev python3-docutils bc python3-ply libssl-dev bc" + +debian/x86_64_test-gl: + variables: + EXTRA_LOCAL_PACKAGES: "jq libasound2 libcairo2 libdw1 libglib2.0-0 libjson-c5 libkmod-dev libkmod2 libgles2 libproc2-dev" + +debian/arm64_build: + variables: + EXTRA_LOCAL_PACKAGES: "libcairo-dev libdw-dev libjson-c-dev libproc2-dev libkmod2 libkmod-dev libpciaccess-dev libudev-dev libunwind-dev python3-docutils libssl-dev crossbuild-essential-armhf libkmod-dev:armhf libproc2-dev:armhf libunwind-dev:armhf libdw-dev:armhf libpixman-1-dev:armhf libcairo-dev:armhf libudev-dev:armhf libjson-c-dev:armhf" + +.kernel+rootfs: + variables: + EXTRA_LOCAL_PACKAGES: "jq libasound2 libcairo2 libdw1 libglib2.0-0 libjson-c5" + +# Disable container jobs that we won't use +alpine/x86_64_build: + rules: + - when: never + +debian/x86_64_test-vk: + rules: + - when: never + +fedora/x86_64_build: + rules: + - when: never + +debian/android_build: + rules: + - when: never + +debian/x86_64_test-android: + rules: + - when: never + +windows_build_vs2019: + rules: + - when: never + +windows_test_vs2019: + rules: + - when: never + +.debian/x86_64_build-mingw: + rules: + - when: never + +rustfmt: + rules: + - when: never + +windows_vs2019: + rules: + - when: never + +clang-format: + rules: + - when: never
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/gitlab-ci.yml b/drivers/gpu/drm/ci/gitlab-ci.yml new file mode 100644 index 000000000000..2c4df53f5dfe --- /dev/null +++ b/drivers/gpu/drm/ci/gitlab-ci.yml @@ -0,0 +1,251 @@ +variables: + DRM_CI_PROJECT_PATH: &drm-ci-project-path mesa/mesa + DRM_CI_COMMIT_SHA: &drm-ci-commit-sha 0dc961645c4f0241f8512cb0ec3ad59635842072 + + UPSTREAM_REPO: git://anongit.freedesktop.org/drm/drm + TARGET_BRANCH: drm-next + + IGT_VERSION: 471bfababd070e1dac0ebb87470ac4f2ae85e663 + + DEQP_RUNNER_GIT_URL: https://gitlab.freedesktop.org/anholt/deqp-runner.git + DEQP_RUNNER_GIT_TAG: v0.15.0 + + FDO_UPSTREAM_REPO: helen.fornazier/linux # The repo where the git-archive daily runs + MESA_TEMPLATES_COMMIT: &ci-templates-commit d5aa3941aa03c2f716595116354fb81eb8012acb + DRM_CI_PROJECT_URL: https://gitlab.freedesktop.org/${DRM_CI_PROJECT_PATH} + CI_PRE_CLONE_SCRIPT: |- + set -o xtrace + curl -L --retry 4 -f --retry-all-errors --retry-delay 60 -s ${DRM_CI_PROJECT_URL}/-/raw/${DRM_CI_COMMIT_SHA}/.gitlab-ci/download-git-cache.sh -o download-git-cache.sh + bash download-git-cache.sh + rm download-git-cache.sh + set +o xtrace + S3_HOST: s3.freedesktop.org + # per-pipeline artifact storage on MinIO + PIPELINE_ARTIFACTS_BASE: ${S3_HOST}/artifacts/${CI_PROJECT_PATH}/${CI_PIPELINE_ID} + # per-job artifact storage on MinIO + JOB_ARTIFACTS_BASE: ${PIPELINE_ARTIFACTS_BASE}/${CI_JOB_ID} + + LAVA_JOB_PRIORITY: 30 + +default: + before_script: + - export SCRIPTS_DIR=$(mktemp -d) + - curl -L -s --retry 4 -f --retry-all-errors --retry-delay 60 -O --output-dir "${SCRIPTS_DIR}" "${DRM_CI_PROJECT_URL}/-/raw/${DRM_CI_COMMIT_SHA}/.gitlab-ci/setup-test-env.sh" + - source ${SCRIPTS_DIR}/setup-test-env.sh + - echo -e "\e[0Ksection_start:$(date +%s):unset_env_vars_section[collapsed=true]\r\e[0KUnsetting vulnerable environment variables" + - export CI_JOB_JWT_FILE="${CI_JOB_JWT_FILE:-$(mktemp)}" + - echo -n "${CI_JOB_JWT}" > "${CI_JOB_JWT_FILE}" + - unset CI_JOB_JWT + - echo -e "\e[0Ksection_end:$(date +%s):unset_env_vars_section\r\e[0K" + + - echo -e "\e[0Ksection_start:$(date +%s):drm_ci_download_section[collapsed=true]\r\e[0KDownloading mesa from $DRM_CI_PROJECT_URL/-/archive/$DRM_CI_COMMIT_SHA/mesa-$DRM_CI_COMMIT_SHA.tar.gz" + - cd $CI_PROJECT_DIR + - curl --output - $DRM_CI_PROJECT_URL/-/archive/$DRM_CI_COMMIT_SHA/mesa-$DRM_CI_COMMIT_SHA.tar.gz | tar -xz + - mv mesa-$DRM_CI_COMMIT_SHA/.gitlab-ci* . + - rm -rf mesa-$DRM_CI_COMMIT_SHA/ + - echo -e "\e[0Ksection_end:$(date +%s):drm_ci_download_section\r\e[0K" + + after_script: + - > + set +x + + test -e "${CI_JOB_JWT_FILE}" && + export CI_JOB_JWT="$(<${CI_JOB_JWT_FILE})" && + rm "${CI_JOB_JWT_FILE}" + + # Retry when job fails. + retry: + max: 1 + # Ignore runner_unsupported, stale_schedule, archived_failure, or + # unmet_prerequisites + when: + - api_failure + - runner_system_failure + - script_failure + - job_execution_timeout + - scheduler_failure + - data_integrity_failure + - unknown_failure + +include: + - project: 'freedesktop/ci-templates' + ref: 16bc29078de5e0a067ff84a1a199a3760d3b3811 + file: + - '/templates/ci-fairy.yml' + - project: 'freedesktop/ci-templates' + ref: *ci-templates-commit + file: + - '/templates/alpine.yml' + - '/templates/debian.yml' + - '/templates/fedora.yml' + - project: *drm-ci-project-path + ref: *drm-ci-commit-sha + file: + - '/.gitlab-ci/farm-rules.yml' + - '/.gitlab-ci/test-source-dep.yml' + - '/.gitlab-ci/container/gitlab-ci.yml' + - '/.gitlab-ci/test/gitlab-ci.yml' + - '/.gitlab-ci/lava/lava-gitlab-ci.yml' + - drivers/gpu/drm/ci/image-tags.yml + - drivers/gpu/drm/ci/container.yml + - drivers/gpu/drm/ci/static-checks.yml + - drivers/gpu/drm/ci/build.yml + - drivers/gpu/drm/ci/test.yml + - 'https://gitlab.freedesktop.org/gfx-ci/lab-status/-/raw/main/lab-status.yml' + + +stages: + - sanity + - container + - git-archive + - build + - amdgpu + - i915 + - mediatek + - meson + - msm + - rockchip + - virtio-gpu + - lint + +# YAML anchors for rule conditions +# -------------------------------- +.rules-anchors: + rules: + # Pipeline for forked project branch + - if: &is-forked-branch '$CI_COMMIT_BRANCH && $CI_PROJECT_NAMESPACE != "mesa"' + when: manual + # Forked project branch / pre-merge pipeline not for Marge bot + - if: &is-forked-branch-or-pre-merge-not-for-marge '$CI_PROJECT_NAMESPACE != "mesa" || ($GITLAB_USER_LOGIN != "marge-bot" && $CI_PIPELINE_SOURCE == "merge_request_event")' + when: manual + # Pipeline runs for the main branch of the upstream Mesa project + - if: &is-mesa-main '$CI_PROJECT_NAMESPACE == "mesa" && $CI_COMMIT_REF_NAME == $CI_DEFAULT_BRANCH && $CI_COMMIT_BRANCH' + when: always + # Post-merge pipeline + - if: &is-post-merge '$CI_PROJECT_NAMESPACE == "mesa" && $CI_COMMIT_BRANCH' + when: on_success + # Post-merge pipeline, not for Marge Bot + - if: &is-post-merge-not-for-marge '$CI_PROJECT_NAMESPACE == "mesa" && $GITLAB_USER_LOGIN != "marge-bot" && $CI_COMMIT_BRANCH' + when: on_success + # Pre-merge pipeline + - if: &is-pre-merge '$CI_PIPELINE_SOURCE == "merge_request_event"' + when: on_success + # Pre-merge pipeline for Marge Bot + - if: &is-pre-merge-for-marge '$GITLAB_USER_LOGIN == "marge-bot" && $CI_PIPELINE_SOURCE == "merge_request_event"' + when: on_success + +# Rule to filter for only scheduled pipelines. +.scheduled_pipeline-rules: + rules: + - if: &is-scheduled-pipeline '$CI_PIPELINE_SOURCE == "schedule"' + when: on_success + +# Generic rule to not run the job during scheduled pipelines. Jobs that aren't +# something like a nightly run should include this rule. +.no_scheduled_pipelines-rules: + rules: + - if: *is-scheduled-pipeline + when: never + +# When to automatically run the CI for build jobs +.build-rules: + rules: + - !reference [.no_scheduled_pipelines-rules, rules] + # Run automatically once all dependency jobs have passed + - when: on_success + + +.ci-deqp-artifacts: + artifacts: + name: "mesa_${CI_JOB_NAME}" + when: always + untracked: false + paths: + # Watch out! Artifacts are relative to the build dir. + # https://gitlab.com/gitlab-org/gitlab-ce/commit/8788fb925706cad594adf6917a6c5f6587dd1521 + - artifacts + - _build/meson-logs/*.txt + - _build/meson-logs/strace + + +.container-rules: + rules: + - !reference [.no_scheduled_pipelines-rules, rules] + # Run pipeline by default in the main project if any CI pipeline + # configuration files were changed, to ensure docker images are up to date + - if: *is-post-merge + changes: + - drivers/gpu/drm/ci/**/* + when: on_success + # Run pipeline by default if it was triggered by Marge Bot, is for a + # merge request, and any files affecting the pipeline were changed + - if: *is-pre-merge-for-marge + when: on_success + # Run pipeline by default in the main project if it was not triggered by + # Marge Bot, and any files affecting the pipeline were changed + - if: *is-post-merge-not-for-marge + when: on_success + # Allow triggering jobs manually in other cases + - when: manual + + + +# Git archive + +make git archive: + extends: + - .fdo.ci-fairy + stage: git-archive + rules: + - !reference [.scheduled_pipeline-rules, rules] + # ensure we are running on packet + tags: + - packet.net + script: + # Remove drm-ci files we just added + - rm -rf .gitlab-ci.* + + # Compactify the .git directory + - git gc --aggressive + # compress the current folder + - tar -cvzf ../$CI_PROJECT_NAME.tar.gz . + + # login with the JWT token file + - ci-fairy s3cp --token-file "${CI_JOB_JWT_FILE}" ../$CI_PROJECT_NAME.tar.gz https://$S3_HOST/git-cache/$CI_PROJECT_NAMESPACE/$CI_PROJECT_NAME/$CI_PROJECT_NAME.tar.gz + + +# Sanity checks of MR settings and commit logs +sanity: + extends: + - .fdo.ci-fairy + stage: sanity + rules: + - if: *is-pre-merge + when: on_success + # Other cases default to never + variables: + GIT_STRATEGY: none + script: + # ci-fairy check-commits --junit-xml=check-commits.xml + - ci-fairy check-merge-request --require-allow-collaboration --junit-xml=check-merge-request.xml + artifacts: + when: on_failure + reports: + junit: check-*.xml + +# Rules for tests that should not block merging, but should be available to +# optionally run with the "play" button in the UI in pre-merge non-marge +# pipelines. This should appear in "extends:" after any includes of +# test-source-dep.yml rules, so that these rules replace those. +.test-manual-mr: + rules: + - !reference [.no_scheduled_pipelines-rules, rules] + - if: *is-forked-branch-or-pre-merge-not-for-marge + when: manual + variables: + JOB_TIMEOUT: 80 + + +# Jobs that need to pass before spending hardware resources on further testing +.required-for-hardware-jobs: + needs: []
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/igt_runner.sh b/drivers/gpu/drm/ci/igt_runner.sh new file mode 100755 index 000000000000..2bb759165063 --- /dev/null +++ b/drivers/gpu/drm/ci/igt_runner.sh @@ -0,0 +1,77 @@ +#!/bin/sh +# SPDX-License-Identifier: MIT + +set -ex + +export IGT_FORCE_DRIVER=${DRIVER_NAME} +export PATH=$PATH:/igt/bin/ +export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/igt/lib/aarch64-linux-gnu/:/igt/lib/x86_64-linux-gnu:/igt/lib:/igt/lib64 + +# Uncomment the below to debug problems with driver probing +: ' +ls -l /dev/dri/ +cat /sys/kernel/debug/devices_deferred +cat /sys/kernel/debug/device_component/* +' + +# Dump drm state to confirm that kernel was able to find a connected display: +# TODO this path might not exist for all drivers.. maybe run modetest instead? +set +e +cat /sys/kernel/debug/dri/*/state +set -e + +# Cannot use HWCI_KERNEL_MODULES as at that point we don't have the module in /lib +if [ "$IGT_FORCE_DRIVER" = "amdgpu" ]; then + mv /install/modules/lib/modules/* /lib/modules/. + modprobe amdgpu +fi + +if [ -e "/install/xfails/$DRIVER_NAME-$GPU_VERSION-skips.txt" ]; then + IGT_SKIPS="--skips /install/xfails/$DRIVER_NAME-$GPU_VERSION-skips.txt" +fi + +if [ -e "/install/xfails/$DRIVER_NAME-$GPU_VERSION-flakes.txt" ]; then + IGT_FLAKES="--flakes /install/xfails/$DRIVER_NAME-$GPU_VERSION-flakes.txt" +fi + +if [ -e "/install/xfails/$DRIVER_NAME-$GPU_VERSION-fails.txt" ]; then + IGT_FAILS="--baseline /install/xfails/$DRIVER_NAME-$GPU_VERSION-fails.txt" +fi + +if [ "`uname -m`" = "aarch64" ]; then + ARCH="arm64" +elif [ "`uname -m`" = "armv7l" ]; then + ARCH="arm" +else + ARCH="x86_64" +fi + +curl -L --retry 4 -f --retry-all-errors --retry-delay 60 -s ${FDO_HTTP_CACHE_URI:-}$PIPELINE_ARTIFACTS_BASE/$ARCH/igt.tar.gz | tar --zstd -v -x -C / + +set +e +igt-runner \ + run \ + --igt-folder /igt/libexec/igt-gpu-tools \ + --caselist /install/testlist.txt \ + --output /results \ + $IGT_SKIPS \ + $IGT_FLAKES \ + $IGT_FAILS \ + --fraction-start $CI_NODE_INDEX \ + --fraction $CI_NODE_TOTAL \ + --jobs 1 +ret=$? +set -e + +deqp-runner junit \ + --testsuite IGT \ + --results /results/failures.csv \ + --output /results/junit.xml \ + --limit 50 \ + --template "See https://$CI_PROJECT_ROOT_NAMESPACE.pages.freedesktop.org/-/$CI_PROJECT_NAME/-/jobs/$CI_JOB_ID/artifacts/results/{{testcase}}.xml" + +# Store the results also in the simpler format used by the runner in ChromeOS CI +#sed -r 's/(dmesg-warn|pass)/success/g' /results/results.txt > /results/results_simple.txt + +cd $oldpath +exit $ret diff --git a/drivers/gpu/drm/ci/image-tags.yml b/drivers/gpu/drm/ci/image-tags.yml new file mode 100644 index 000000000000..f051b6c547c5 --- /dev/null +++ b/drivers/gpu/drm/ci/image-tags.yml @@ -0,0 +1,15 @@ +variables: + CONTAINER_TAG: "2023-08-10-mesa-uprev" + DEBIAN_X86_64_BUILD_BASE_IMAGE: "debian/x86_64_build-base" + DEBIAN_BASE_TAG: "${CONTAINER_TAG}" + + DEBIAN_X86_64_BUILD_IMAGE_PATH: "debian/x86_64_build" + DEBIAN_BUILD_TAG: "${CONTAINER_TAG}" + + KERNEL_ROOTFS_TAG: "${CONTAINER_TAG}" + + DEBIAN_X86_64_TEST_BASE_IMAGE: "debian/x86_64_test-base" + DEBIAN_X86_64_TEST_IMAGE_GL_PATH: "debian/x86_64_test-gl" + DEBIAN_X86_64_TEST_GL_TAG: "${CONTAINER_TAG}" + + ALPINE_X86_64_LAVA_SSH_TAG: "${CONTAINER_TAG}"
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/lava-submit.sh b/drivers/gpu/drm/ci/lava-submit.sh new file mode 100755 index 000000000000..0c4456b21b0f --- /dev/null +++ b/drivers/gpu/drm/ci/lava-submit.sh @@ -0,0 +1,57 @@ +#!/bin/bash +# SPDX-License-Identifier: MIT + +set -e +set -x + +# Try to use the kernel and rootfs built in mainline first, so we're more +# likely to hit cache +if curl -L --retry 4 -f --retry-all-errors --retry-delay 60 -s "https://${BASE_SYSTEM_MAINLINE_HOST_PATH}/done"; then + BASE_SYSTEM_HOST_PATH="${BASE_SYSTEM_MAINLINE_HOST_PATH}" +else + BASE_SYSTEM_HOST_PATH="${BASE_SYSTEM_FORK_HOST_PATH}" +fi + +rm -rf results +mkdir -p results/job-rootfs-overlay/ + +cp artifacts/ci-common/capture-devcoredump.sh results/job-rootfs-overlay/ +cp artifacts/ci-common/init-*.sh results/job-rootfs-overlay/ +cp artifacts/ci-common/intel-gpu-freq.sh results/job-rootfs-overlay/ +cp "$SCRIPTS_DIR"/setup-test-env.sh results/job-rootfs-overlay/ + +# Prepare env vars for upload. +section_start variables "Variables passed through:" +KERNEL_IMAGE_BASE_URL="https://${BASE_SYSTEM_HOST_PATH}" \ + artifacts/ci-common/generate-env.sh | tee results/job-rootfs-overlay/set-job-env-vars.sh +section_end variables + +tar zcf job-rootfs-overlay.tar.gz -C results/job-rootfs-overlay/ . +ci-fairy s3cp --token-file "${CI_JOB_JWT_FILE}" job-rootfs-overlay.tar.gz "https://${JOB_ROOTFS_OVERLAY_PATH}" + +touch results/lava.log +tail -f results/lava.log & + +PYTHONPATH=artifacts/ artifacts/lava/lava_job_submitter.py \ + submit \ + --dump-yaml \ + --pipeline-info "$CI_JOB_NAME: $CI_PIPELINE_URL on $CI_COMMIT_REF_NAME ${CI_NODE_INDEX}/${CI_NODE_TOTAL}" \ + --rootfs-url-prefix "https://${BASE_SYSTEM_HOST_PATH}" \ + --kernel-url-prefix "https://${PIPELINE_ARTIFACTS_BASE}/${ARCH}" \ + --build-url "${FDO_HTTP_CACHE_URI:-}https://${PIPELINE_ARTIFACTS_BASE}/${ARCH}/kernel-files.tar.zst" \ + --job-rootfs-overlay-url "${FDO_HTTP_CACHE_URI:-}https://${JOB_ROOTFS_OVERLAY_PATH}" \ + --job-timeout-min ${JOB_TIMEOUT:-80} \ + --first-stage-init artifacts/ci-common/init-stage1.sh \ + --ci-project-dir "${CI_PROJECT_DIR}" \ + --device-type "${DEVICE_TYPE}" \ + --dtb-filename "${DTB}" \ + --jwt-file "${CI_JOB_JWT_FILE}" \ + --kernel-image-name "${KERNEL_IMAGE_NAME}" \ + --kernel-image-type "${KERNEL_IMAGE_TYPE}" \ + --boot-method "${BOOT_METHOD}" \ + --visibility-group "${VISIBILITY_GROUP}" \ + --lava-tags "${LAVA_TAGS}" \ + --mesa-job-name "$CI_JOB_NAME" \ + --structured-log-file "results/lava_job_detail.json" \ + --ssh-client-image "${LAVA_SSH_CLIENT_IMAGE}" \ + >> results/lava.log diff --git a/drivers/gpu/drm/ci/static-checks.yml b/drivers/gpu/drm/ci/static-checks.yml new file mode 100644 index 000000000000..13ffa827b7fa --- /dev/null +++ b/drivers/gpu/drm/ci/static-checks.yml @@ -0,0 +1,12 @@ +check-patch: + extends: + - .build + - .use-debian/x86_64_build + script: + - drivers/gpu/drm/ci/check-patch.py + variables: + CHECKPATCH_TYPES: "BAD_SIGN_OFF,BAD_STABLE_ADDRESS_STYLE,COMMIT_COMMENT_SYMBOL,COMMIT_MESSAGE,EMAIL_SUBJECT,FROM_SIGN_OFF_MISMATCH,MISSING_SIGN_OFF,NO_AUTHOR_SIGN_OFF,DIFF_IN_COMMIT_MSG,GERRIT_CHANGE_ID,GIT_COMMIT_ID,UNKNOWN_COMMIT_ID,CODE_INDENT,BIT_MACRO,DOS_LINE_ENDINGS" + rules: + - if: '$CI_PIPELINE_SOURCE == "merge_request_event"' + when: on_success + # Other cases default to never diff --git a/drivers/gpu/drm/ci/test.yml b/drivers/gpu/drm/ci/test.yml new file mode 100644 index 000000000000..6473cddaa7a9 --- /dev/null +++ b/drivers/gpu/drm/ci/test.yml @@ -0,0 +1,335 @@ +.test-rules: + rules: + - if: '$FD_FARM == "offline" && $RUNNER_TAG =~ /^google-freedreno-/' + when: never + - if: '$COLLABORA_FARM == "offline" && $RUNNER_TAG =~ /^mesa-ci-x86-64-lava-/' + when: never + - !reference [.no_scheduled_pipelines-rules, rules] + - when: on_success + +.lava-test: + extends: + - .test-rules + script: + # Note: Build dir (and thus install) may be dirty due to GIT_STRATEGY + - rm -rf install + - tar -xf artifacts/install.tar + - mv install/* artifacts/. + # Override it with our lava-submit.sh script + - ./artifacts/lava-submit.sh + +.lava-igt:arm32: + extends: + - .lava-test:arm32 + variables: + HWCI_TEST_SCRIPT: "/install/igt_runner.sh" + ARCH: "armhf" + dependencies: + - testing:arm32 + needs: + - alpine/x86_64_lava_ssh_client + - kernel+rootfs_arm32 + - debian/x86_64_build + - testing:arm32 + - igt:arm32 + +.lava-igt:arm64: + extends: + - .lava-test:arm64 + variables: + HWCI_TEST_SCRIPT: "/install/igt_runner.sh" + ARCH: "arm64" + dependencies: + - testing:arm64 + needs: + - alpine/x86_64_lava_ssh_client + - kernel+rootfs_arm64 + - debian/x86_64_build + - testing:arm64 + - igt:arm64 + +.lava-igt:x86_64: + extends: + - .lava-test:x86_64 + variables: + HWCI_TEST_SCRIPT: "/install/igt_runner.sh" + ARCH: "x86_64" + dependencies: + - testing:x86_64 + needs: + - alpine/x86_64_lava_ssh_client + - kernel+rootfs_x86_64 + - debian/x86_64_build + - testing:x86_64 + - igt:x86_64 + +.baremetal-igt-arm64: + extends: + - .baremetal-test-arm64 + - .use-debian/arm64_test + - .test-rules + variables: + FDO_CI_CONCURRENT: 10 + HWCI_TEST_SCRIPT: "/install/igt_runner.sh" + S3_ARTIFACT_NAME: "arm64/kernel-files" + BM_KERNEL: https://${PIPELINE_ARTIFACTS_BASE}/arm64/Image.gz + BM_CMDLINE: "ip=dhcp console=ttyMSM0,115200n8 $BM_KERNEL_EXTRA_ARGS root=/dev/nfs rw nfsrootdebug nfsroot=,tcp,nfsvers=4.2 init=/init $BM_KERNELARGS" + needs: + - debian/arm64_test + - job: testing:arm64 + artifacts: false + - igt:arm64 + tags: + - $RUNNER_TAG + +msm:sc7180: + extends: + - .lava-igt:arm64 + stage: msm + parallel: 2 + variables: + DRIVER_NAME: msm + DEVICE_TYPE: sc7180-trogdor-lazor-limozeen + DTB: sc7180-trogdor-lazor-limozeen-nots-r5 + BOOT_METHOD: depthcharge + KERNEL_IMAGE_TYPE: "" + GPU_VERSION: sc7180 + RUNNER_TAG: mesa-ci-x86-64-lava-sc7180-trogdor-lazor-limozeen + +msm:apq8016: + extends: + - .baremetal-igt-arm64 + stage: msm + variables: + DRIVER_NAME: msm + BM_DTB: https://${PIPELINE_ARTIFACTS_BASE}/arm64/apq8016-sbc.dtb + GPU_VERSION: apq8016 + BM_CMDLINE: "ip=dhcp console=ttyMSM0,115200n8 $BM_KERNEL_EXTRA_ARGS root=/dev/nfs rw nfsrootdebug nfsroot=,tcp,nfsvers=4.2 init=/init $BM_KERNELARGS" + RUNNER_TAG: google-freedreno-db410c + script: + - ./install/bare-metal/fastboot.sh + rules: + # TODO: current issue: it is not fiding the NFS root. Fix and remove this rule. + - when: never + +msm:apq8096: + extends: + - .baremetal-igt-arm64 + stage: msm + variables: + DRIVER_NAME: msm + BM_KERNEL_EXTRA_ARGS: maxcpus=2 + BM_DTB: https://${PIPELINE_ARTIFACTS_BASE}/arm64/apq8096-db820c.dtb + GPU_VERSION: apq8096 + RUNNER_TAG: google-freedreno-db820c + script: + - ./install/bare-metal/fastboot.sh + +msm:sdm845: + extends: + - .baremetal-igt-arm64 + stage: msm + parallel: 6 + variables: + DRIVER_NAME: msm + BM_KERNEL: https://${PIPELINE_ARTIFACTS_BASE}/arm64/cheza-kernel + GPU_VERSION: sdm845 + RUNNER_TAG: google-freedreno-cheza + script: + - ./install/bare-metal/cros-servo.sh + +rockchip:rk3288: + extends: + - .lava-igt:arm32 + stage: rockchip + variables: + DRIVER_NAME: rockchip + DEVICE_TYPE: rk3288-veyron-jaq + DTB: ${DEVICE_TYPE} + BOOT_METHOD: depthcharge + KERNEL_IMAGE_TYPE: "zimage" + GPU_VERSION: rk3288 + RUNNER_TAG: mesa-ci-x86-64-lava-rk3288-veyron-jaq + +rockchip:rk3399: + extends: + - .lava-igt:arm64 + stage: rockchip + parallel: 3 + variables: + DRIVER_NAME: rockchip + DEVICE_TYPE: rk3399-gru-kevin + DTB: ${DEVICE_TYPE} + BOOT_METHOD: depthcharge + KERNEL_IMAGE_TYPE: "" + GPU_VERSION: rk3399 + RUNNER_TAG: mesa-ci-x86-64-lava-rk3399-gru-kevin + +.i915: + extends: + - .lava-igt:x86_64 + stage: i915 + variables: + DRIVER_NAME: i915 + DTB: "" + BOOT_METHOD: depthcharge + KERNEL_IMAGE_TYPE: "" + +i915:apl: + extends: + - .i915 + parallel: 12 + variables: + DEVICE_TYPE: asus-C523NA-A20057-coral + GPU_VERSION: apl + RUNNER_TAG: mesa-ci-x86-64-lava-asus-C523NA-A20057-coral + +i915:glk: + extends: + - .i915 + parallel: 5 + variables: + DEVICE_TYPE: hp-x360-12b-ca0010nr-n4020-octopus + GPU_VERSION: glk + RUNNER_TAG: mesa-ci-x86-64-lava-hp-x360-12b-ca0010nr-n4020-octopus + +i915:amly: + extends: + - .i915 + parallel: 8 + variables: + DEVICE_TYPE: asus-C433TA-AJ0005-rammus + GPU_VERSION: amly + RUNNER_TAG: mesa-ci-x86-64-lava-asus-C433TA-AJ0005-rammus + +i915:kbl: + extends: + - .i915 + parallel: 5 + variables: + DEVICE_TYPE: hp-x360-14-G1-sona + GPU_VERSION: kbl + RUNNER_TAG: mesa-ci-x86-64-lava-hp-x360-14-G1-sona + +i915:whl: + extends: + - .i915 + parallel: 8 + variables: + DEVICE_TYPE: dell-latitude-5400-8665U-sarien + GPU_VERSION: whl + RUNNER_TAG: mesa-ci-x86-64-lava-dell-latitude-5400-8665U-sarien + +i915:cml: + extends: + - .i915 + parallel: 6 + variables: + DEVICE_TYPE: asus-C436FA-Flip-hatch + GPU_VERSION: cml + RUNNER_TAG: mesa-ci-x86-64-lava-asus-C436FA-flip-hatch + +i915:tgl: + extends: + - .i915 + parallel: 6 + variables: + DEVICE_TYPE: asus-cx9400-volteer + GPU_VERSION: tgl + RUNNER_TAG: mesa-ci-x86-64-lava-asus-cx9400-volteer + +.amdgpu: + extends: + - .lava-igt:x86_64 + stage: amdgpu + variables: + DRIVER_NAME: amdgpu + DTB: "" + BOOT_METHOD: depthcharge + KERNEL_IMAGE_TYPE: "" + +amdgpu:stoney: + extends: + - .amdgpu + variables: + DEVICE_TYPE: hp-11A-G6-EE-grunt + GPU_VERSION: stoney + RUNNER_TAG: mesa-ci-x86-64-lava-hp-11A-G6-EE-grunt + +.mediatek: + extends: + - .lava-igt:arm64 + stage: mediatek + variables: + DRIVER_NAME: mediatek + DTB: ${DEVICE_TYPE} + BOOT_METHOD: depthcharge + KERNEL_IMAGE_TYPE: "" + +mediatek:mt8173: + extends: + - .mediatek + variables: + DEVICE_TYPE: mt8173-elm-hana + GPU_VERSION: mt8173 + RUNNER_TAG: mesa-ci-x86-64-lava-mt8173-elm-hana + rules: + # TODO: current issue: device is hanging. Fix and remove this rule. + - when: never + +mediatek:mt8183: + extends: + - .mediatek + variables: + DEVICE_TYPE: mt8183-kukui-jacuzzi-juniper-sku16 + GPU_VERSION: mt8183 + RUNNER_TAG: mesa-ci-x86-64-lava-mt8183-kukui-jacuzzi-juniper-sku16 + +# drm-mtk doesn't even probe yet in mainline for mt8192 +.mediatek:mt8192: + extends: + - .mediatek + variables: + DEVICE_TYPE: mt8192-asurada-spherion-r0 + GPU_VERSION: mt8192 + RUNNER_TAG: mesa-ci-x86-64-lava-mt8192-asurada-spherion-r0 + +.meson: + extends: + - .lava-igt:arm64 + stage: meson + variables: + DRIVER_NAME: meson + DTB: ${DEVICE_TYPE} + BOOT_METHOD: u-boot + KERNEL_IMAGE_TYPE: "image" + +meson:g12b: + extends: + - .meson + variables: + DEVICE_TYPE: meson-g12b-a311d-khadas-vim3 + GPU_VERSION: g12b + RUNNER_TAG: mesa-ci-x86-64-lava-meson-g12b-a311d-khadas-vim3 + +virtio_gpu:none: + stage: virtio-gpu + variables: + CROSVM_GALLIUM_DRIVER: llvmpipe + DRIVER_NAME: virtio_gpu + GPU_VERSION: none + extends: + - .test-gl + tags: + - kvm + script: + - ln -sf $CI_PROJECT_DIR/install /install + - mv install/bzImage /lava-files/bzImage + - install/crosvm-runner.sh install/igt_runner.sh + needs: + - debian/x86_64_test-gl + - testing:x86_64 + - igt:x86_64 + rules: + # TODO: current issue: malloc(): corrupted top size. Fix and remove this rule. + - when: never
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/testlist.txt b/drivers/gpu/drm/ci/testlist.txt new file mode 100644 index 000000000000..f82cd90372f4 --- /dev/null +++ b/drivers/gpu/drm/ci/testlist.txt @@ -0,0 +1,2912 @@ +core_auth@getclient-simple +core_auth@getclient-master-drop +core_auth@basic-auth +core_auth@many-magics +core_getclient +core_getstats +core_getversion +core_setmaster_vs_auth +drm_read@invalid-buffer +drm_read@fault-buffer +drm_read@empty-block +drm_read@empty-nonblock +drm_read@short-buffer-block +drm_read@short-buffer-nonblock +drm_read@short-buffer-wakeup +gem_eio@throttle +gem_eio@create +gem_eio@create-ext +gem_eio@context-create +gem_eio@execbuf +gem_eio@banned +gem_eio@suspend +gem_eio@hibernate +gem_eio@in-flight-external +gem_eio@in-flight-suspend +gem_eio@reset-stress +gem_eio@unwedge-stress +gem_eio@wait-immediate +gem_eio@wait-wedge-immediate +gem_eio@in-flight-immediate +gem_eio@in-flight-contexts-immediate +gem_eio@in-flight-internal-immediate +gem_eio@wait-1us +gem_eio@wait-wedge-1us +gem_eio@in-flight-1us +gem_eio@in-flight-contexts-1us +gem_eio@in-flight-internal-1us +gem_eio@wait-10ms +gem_eio@wait-wedge-10ms +gem_eio@in-flight-10ms +gem_eio@in-flight-contexts-10ms +gem_eio@in-flight-internal-10ms +gem_eio@kms +kms_3d +kms_addfb_basic@unused-handle +kms_addfb_basic@unused-pitches +kms_addfb_basic@unused-offsets +kms_addfb_basic@unused-modifier +kms_addfb_basic@clobberred-modifier +kms_addfb_basic@invalid-smem-bo-on-discrete +kms_addfb_basic@legacy-format +kms_addfb_basic@no-handle +kms_addfb_basic@basic +kms_addfb_basic@bad-pitch-0 +kms_addfb_basic@bad-pitch-32 +kms_addfb_basic@bad-pitch-63 +kms_addfb_basic@bad-pitch-128 +kms_addfb_basic@bad-pitch-256 +kms_addfb_basic@bad-pitch-1024 +kms_addfb_basic@bad-pitch-999 +kms_addfb_basic@bad-pitch-65536 +kms_addfb_basic@invalid-get-prop-any +kms_addfb_basic@invalid-get-prop +kms_addfb_basic@invalid-set-prop-any +kms_addfb_basic@invalid-set-prop +kms_addfb_basic@master-rmfb +kms_addfb_basic@addfb25-modifier-no-flag +kms_addfb_basic@addfb25-bad-modifier +kms_addfb_basic@addfb25-x-tiled-mismatch-legacy +kms_addfb_basic@addfb25-x-tiled-legacy +kms_addfb_basic@addfb25-framebuffer-vs-set-tiling +kms_addfb_basic@basic-x-tiled-legacy +kms_addfb_basic@framebuffer-vs-set-tiling +kms_addfb_basic@tile-pitch-mismatch +kms_addfb_basic@basic-y-tiled-legacy +kms_addfb_basic@size-max +kms_addfb_basic@too-wide +kms_addfb_basic@too-high +kms_addfb_basic@bo-too-small +kms_addfb_basic@small-bo +kms_addfb_basic@bo-too-small-due-to-tiling +kms_addfb_basic@addfb25-y-tiled-legacy +kms_addfb_basic@addfb25-yf-tiled-legacy +kms_addfb_basic@addfb25-y-tiled-small-legacy +kms_addfb_basic@addfb25-4-tiled +kms_async_flips@async-flip-with-page-flip-events +kms_async_flips@alternate-sync-async-flip +kms_async_flips@test-time-stamp +kms_async_flips@test-cursor +kms_async_flips@invalid-async-flip +kms_async_flips@crc +kms_atomic@plane-overlay-legacy +kms_atomic@plane-primary-legacy +kms_atomic@plane-primary-overlay-mutable-zpos +kms_atomic@plane-immutable-zpos +kms_atomic@test-only +kms_atomic@plane-cursor-legacy +kms_atomic@plane-invalid-params +kms_atomic@plane-invalid-params-fence +kms_atomic@crtc-invalid-params +kms_atomic@crtc-invalid-params-fence +kms_atomic@atomic-invalid-params +kms_atomic@atomic_plane_damage +kms_atomic_interruptible@legacy-setmode +kms_atomic_interruptible@atomic-setmode +kms_atomic_interruptible@legacy-dpms +kms_atomic_interruptible@legacy-pageflip +kms_atomic_interruptible@legacy-cursor +kms_atomic_interruptible@universal-setplane-primary +kms_atomic_interruptible@universal-setplane-cursor +kms_atomic_transition@plane-primary-toggle-with-vblank-wait +kms_atomic_transition@plane-all-transition +kms_atomic_transition@plane-all-transition-fencing +kms_atomic_transition@plane-all-transition-nonblocking +kms_atomic_transition@plane-all-transition-nonblocking-fencing +kms_atomic_transition@plane-use-after-nonblocking-unbind +kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing +kms_atomic_transition@plane-all-modeset-transition +kms_atomic_transition@plane-all-modeset-transition-fencing +kms_atomic_transition@plane-all-modeset-transition-internal-panels +kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels +kms_atomic_transition@plane-toggle-modeset-transition +kms_atomic_transition@modeset-transition +kms_atomic_transition@modeset-transition-fencing +kms_atomic_transition@modeset-transition-nonblocking +kms_atomic_transition@modeset-transition-nonblocking-fencing +kms_big_fb@x-tiled-addfb-size-overflow +kms_big_fb@y-tiled-addfb-size-overflow +kms_big_fb@yf-tiled-addfb-size-overflow +kms_big_fb@4-tiled-addfb-size-overflow +kms_big_fb@x-tiled-addfb-size-offset-overflow +kms_big_fb@y-tiled-addfb-size-offset-overflow +kms_big_fb@yf-tiled-addfb-size-offset-overflow +kms_big_fb@4-tiled-addfb-size-offset-overflow +kms_big_fb@linear-addfb +kms_big_fb@x-tiled-addfb +kms_big_fb@y-tiled-addfb +kms_big_fb@yf-tiled-addfb +kms_big_fb@4-tiled-addfb +kms_big_fb@linear-8bpp-rotate-0 +kms_big_fb@linear-8bpp-rotate-90 +kms_big_fb@linear-8bpp-rotate-180 +kms_big_fb@linear-8bpp-rotate-270 +kms_big_fb@linear-16bpp-rotate-0 +kms_big_fb@linear-16bpp-rotate-90 +kms_big_fb@linear-16bpp-rotate-180 +kms_big_fb@linear-16bpp-rotate-270 +kms_big_fb@linear-32bpp-rotate-0 +kms_big_fb@linear-32bpp-rotate-90 +kms_big_fb@linear-32bpp-rotate-180 +kms_big_fb@linear-32bpp-rotate-270 +kms_big_fb@linear-64bpp-rotate-0 +kms_big_fb@linear-64bpp-rotate-90 +kms_big_fb@linear-64bpp-rotate-180 +kms_big_fb@linear-64bpp-rotate-270 +kms_big_fb@x-tiled-8bpp-rotate-0 +kms_big_fb@x-tiled-8bpp-rotate-90 +kms_big_fb@x-tiled-8bpp-rotate-180 +kms_big_fb@x-tiled-8bpp-rotate-270 +kms_big_fb@x-tiled-16bpp-rotate-0 +kms_big_fb@x-tiled-16bpp-rotate-90 +kms_big_fb@x-tiled-16bpp-rotate-180 +kms_big_fb@x-tiled-16bpp-rotate-270 +kms_big_fb@x-tiled-32bpp-rotate-0 +kms_big_fb@x-tiled-32bpp-rotate-90 +kms_big_fb@x-tiled-32bpp-rotate-180 +kms_big_fb@x-tiled-32bpp-rotate-270 +kms_big_fb@x-tiled-64bpp-rotate-0 +kms_big_fb@x-tiled-64bpp-rotate-90 +kms_big_fb@x-tiled-64bpp-rotate-180 +kms_big_fb@x-tiled-64bpp-rotate-270 +kms_big_fb@y-tiled-8bpp-rotate-0 +kms_big_fb@y-tiled-8bpp-rotate-90 +kms_big_fb@y-tiled-8bpp-rotate-180 +kms_big_fb@y-tiled-8bpp-rotate-270 +kms_big_fb@y-tiled-16bpp-rotate-0 +kms_big_fb@y-tiled-16bpp-rotate-90 +kms_big_fb@y-tiled-16bpp-rotate-180 +kms_big_fb@y-tiled-16bpp-rotate-270 +kms_big_fb@y-tiled-32bpp-rotate-0 +kms_big_fb@y-tiled-32bpp-rotate-90 +kms_big_fb@y-tiled-32bpp-rotate-180 +kms_big_fb@y-tiled-32bpp-rotate-270 +kms_big_fb@y-tiled-64bpp-rotate-0 +kms_big_fb@y-tiled-64bpp-rotate-90 +kms_big_fb@y-tiled-64bpp-rotate-180 +kms_big_fb@y-tiled-64bpp-rotate-270 +kms_big_fb@yf-tiled-8bpp-rotate-0 +kms_big_fb@yf-tiled-8bpp-rotate-90 +kms_big_fb@yf-tiled-8bpp-rotate-180 +kms_big_fb@yf-tiled-8bpp-rotate-270 +kms_big_fb@yf-tiled-16bpp-rotate-0 +kms_big_fb@yf-tiled-16bpp-rotate-90 +kms_big_fb@yf-tiled-16bpp-rotate-180 +kms_big_fb@yf-tiled-16bpp-rotate-270 +kms_big_fb@yf-tiled-32bpp-rotate-0 +kms_big_fb@yf-tiled-32bpp-rotate-90 +kms_big_fb@yf-tiled-32bpp-rotate-180 +kms_big_fb@yf-tiled-32bpp-rotate-270 +kms_big_fb@yf-tiled-64bpp-rotate-0 +kms_big_fb@yf-tiled-64bpp-rotate-90 +kms_big_fb@yf-tiled-64bpp-rotate-180 +kms_big_fb@yf-tiled-64bpp-rotate-270 +kms_big_fb@4-tiled-8bpp-rotate-0 +kms_big_fb@4-tiled-8bpp-rotate-90 +kms_big_fb@4-tiled-8bpp-rotate-180 +kms_big_fb@4-tiled-8bpp-rotate-270 +kms_big_fb@4-tiled-16bpp-rotate-0 +kms_big_fb@4-tiled-16bpp-rotate-90 +kms_big_fb@4-tiled-16bpp-rotate-180 +kms_big_fb@4-tiled-16bpp-rotate-270 +kms_big_fb@4-tiled-32bpp-rotate-0 +kms_big_fb@4-tiled-32bpp-rotate-90 +kms_big_fb@4-tiled-32bpp-rotate-180 +kms_big_fb@4-tiled-32bpp-rotate-270 +kms_big_fb@4-tiled-64bpp-rotate-0 +kms_big_fb@4-tiled-64bpp-rotate-90 +kms_big_fb@4-tiled-64bpp-rotate-180 +kms_big_fb@4-tiled-64bpp-rotate-270 +kms_big_fb@linear-max-hw-stride-32bpp-rotate-0 +kms_big_fb@linear-max-hw-stride-32bpp-rotate-180 +kms_big_fb@linear-max-hw-stride-64bpp-rotate-0 +kms_big_fb@linear-max-hw-stride-64bpp-rotate-180 +kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0 +kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip +kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180 +kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip +kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0 +kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip +kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180 +kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip +kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip +kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip +kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip +kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip +kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip +kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip +kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip +kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip +kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0 +kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip +kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180 +kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip +kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0 +kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip +kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180 +kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip +kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip +kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip +kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip +kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip +kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip +kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip +kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip +kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip +kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0 +kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip +kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180 +kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip +kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0 +kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-async-flip +kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180 +kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip +kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip +kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip +kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip +kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip +kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip +kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip +kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip +kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip +kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0 +kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip +kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180 +kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip +kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0 +kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip +kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180 +kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip +kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip +kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip +kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip +kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip +kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip +kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip +kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip +kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip +kms_big_joiner@basic +kms_big_joiner@invalid-modeset +kms_big_joiner@2x-modeset +kms_busy@basic +kms_busy@basic-hang +kms_busy@extended-pageflip-modeset-hang-oldfb +kms_busy@extended-pageflip-hang-oldfb +kms_busy@extended-pageflip-hang-newfb +kms_busy@extended-modeset-hang-oldfb +kms_busy@extended-modeset-hang-newfb +kms_busy@extended-modeset-hang-oldfb-with-reset +kms_busy@extended-modeset-hang-newfb-with-reset +kms_bw@linear-tiling-1-displays-1920x1080p +kms_bw@linear-tiling-1-displays-2560x1440p +kms_bw@linear-tiling-1-displays-3840x2160p +kms_bw@linear-tiling-2-displays-1920x1080p +kms_bw@linear-tiling-2-displays-2560x1440p +kms_bw@linear-tiling-2-displays-3840x2160p +kms_bw@linear-tiling-3-displays-1920x1080p +kms_bw@linear-tiling-3-displays-2560x1440p +kms_bw@linear-tiling-3-displays-3840x2160p +kms_bw@linear-tiling-4-displays-1920x1080p +kms_bw@linear-tiling-4-displays-2560x1440p +kms_bw@linear-tiling-4-displays-3840x2160p +kms_bw@linear-tiling-5-displays-1920x1080p +kms_bw@linear-tiling-5-displays-2560x1440p +kms_bw@linear-tiling-5-displays-3840x2160p +kms_bw@linear-tiling-6-displays-1920x1080p +kms_bw@linear-tiling-6-displays-2560x1440p +kms_bw@linear-tiling-6-displays-3840x2160p +kms_bw@linear-tiling-7-displays-1920x1080p +kms_bw@linear-tiling-7-displays-2560x1440p +kms_bw@linear-tiling-7-displays-3840x2160p +kms_bw@linear-tiling-8-displays-1920x1080p +kms_bw@linear-tiling-8-displays-2560x1440p +kms_bw@linear-tiling-8-displays-3840x2160p +kms_ccs@pipe-A-bad-pixel-format-y_tiled_ccs +kms_ccs@pipe-A-bad-pixel-format-yf_tiled_ccs +kms_ccs@pipe-A-bad-pixel-format-y_tiled_gen12_rc_ccs +kms_ccs@pipe-A-bad-pixel-format-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-A-bad-pixel-format-y_tiled_gen12_mc_ccs +kms_ccs@pipe-A-bad-pixel-format-4_tiled_dg2_rc_ccs +kms_ccs@pipe-A-bad-pixel-format-4_tiled_dg2_mc_ccs +kms_ccs@pipe-A-bad-pixel-format-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-A-bad-pixel-format-4_tiled_mtl_rc_ccs +kms_ccs@pipe-A-bad-pixel-format-4_tiled_mtl_mc_ccs +kms_ccs@pipe-A-bad-pixel-format-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-A-bad-rotation-90-y_tiled_ccs +kms_ccs@pipe-A-bad-rotation-90-yf_tiled_ccs +kms_ccs@pipe-A-bad-rotation-90-y_tiled_gen12_rc_ccs +kms_ccs@pipe-A-bad-rotation-90-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-A-bad-rotation-90-y_tiled_gen12_mc_ccs +kms_ccs@pipe-A-bad-rotation-90-4_tiled_dg2_rc_ccs +kms_ccs@pipe-A-bad-rotation-90-4_tiled_dg2_mc_ccs +kms_ccs@pipe-A-bad-rotation-90-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-A-bad-rotation-90-4_tiled_mtl_rc_ccs +kms_ccs@pipe-A-bad-rotation-90-4_tiled_mtl_mc_ccs +kms_ccs@pipe-A-bad-rotation-90-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-A-crc-primary-basic-y_tiled_ccs +kms_ccs@pipe-A-crc-primary-basic-yf_tiled_ccs +kms_ccs@pipe-A-crc-primary-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-A-crc-primary-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-A-crc-primary-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-A-crc-primary-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-A-crc-primary-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-A-crc-primary-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-A-crc-primary-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-A-crc-primary-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-A-crc-primary-basic-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-A-crc-primary-rotation-180-y_tiled_ccs +kms_ccs@pipe-A-crc-primary-rotation-180-yf_tiled_ccs +kms_ccs@pipe-A-crc-primary-rotation-180-y_tiled_gen12_rc_ccs +kms_ccs@pipe-A-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-A-crc-primary-rotation-180-y_tiled_gen12_mc_ccs +kms_ccs@pipe-A-crc-primary-rotation-180-4_tiled_dg2_rc_ccs +kms_ccs@pipe-A-crc-primary-rotation-180-4_tiled_dg2_mc_ccs +kms_ccs@pipe-A-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-A-crc-primary-rotation-180-4_tiled_mtl_rc_ccs +kms_ccs@pipe-A-crc-primary-rotation-180-4_tiled_mtl_mc_ccs +kms_ccs@pipe-A-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-A-random-ccs-data-y_tiled_ccs +kms_ccs@pipe-A-random-ccs-data-yf_tiled_ccs +kms_ccs@pipe-A-random-ccs-data-y_tiled_gen12_rc_ccs +kms_ccs@pipe-A-random-ccs-data-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-A-random-ccs-data-y_tiled_gen12_mc_ccs +kms_ccs@pipe-A-random-ccs-data-4_tiled_dg2_rc_ccs +kms_ccs@pipe-A-random-ccs-data-4_tiled_dg2_mc_ccs +kms_ccs@pipe-A-random-ccs-data-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-A-random-ccs-data-4_tiled_mtl_rc_ccs +kms_ccs@pipe-A-random-ccs-data-4_tiled_mtl_mc_ccs +kms_ccs@pipe-A-random-ccs-data-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-A-missing-ccs-buffer-y_tiled_ccs +kms_ccs@pipe-A-missing-ccs-buffer-yf_tiled_ccs +kms_ccs@pipe-A-missing-ccs-buffer-y_tiled_gen12_rc_ccs +kms_ccs@pipe-A-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-A-missing-ccs-buffer-y_tiled_gen12_mc_ccs +kms_ccs@pipe-A-missing-ccs-buffer-4_tiled_mtl_rc_ccs +kms_ccs@pipe-A-missing-ccs-buffer-4_tiled_mtl_mc_ccs +kms_ccs@pipe-A-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-A-ccs-on-another-bo-y_tiled_ccs +kms_ccs@pipe-A-ccs-on-another-bo-yf_tiled_ccs +kms_ccs@pipe-A-ccs-on-another-bo-y_tiled_gen12_rc_ccs +kms_ccs@pipe-A-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-A-ccs-on-another-bo-y_tiled_gen12_mc_ccs +kms_ccs@pipe-A-ccs-on-another-bo-4_tiled_mtl_rc_ccs +kms_ccs@pipe-A-ccs-on-another-bo-4_tiled_mtl_mc_ccs +kms_ccs@pipe-A-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-A-bad-aux-stride-y_tiled_ccs +kms_ccs@pipe-A-bad-aux-stride-yf_tiled_ccs +kms_ccs@pipe-A-bad-aux-stride-y_tiled_gen12_rc_ccs +kms_ccs@pipe-A-bad-aux-stride-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-A-bad-aux-stride-y_tiled_gen12_mc_ccs +kms_ccs@pipe-A-bad-aux-stride-4_tiled_mtl_rc_ccs +kms_ccs@pipe-A-bad-aux-stride-4_tiled_mtl_mc_ccs +kms_ccs@pipe-A-bad-aux-stride-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-A-crc-sprite-planes-basic-y_tiled_ccs +kms_ccs@pipe-A-crc-sprite-planes-basic-yf_tiled_ccs +kms_ccs@pipe-A-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-A-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-A-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-A-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-A-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-A-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-A-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-A-crc-sprite-planes-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-A-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-B-bad-pixel-format-y_tiled_ccs +kms_ccs@pipe-B-bad-pixel-format-yf_tiled_ccs +kms_ccs@pipe-B-bad-pixel-format-y_tiled_gen12_rc_ccs +kms_ccs@pipe-B-bad-pixel-format-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-B-bad-pixel-format-y_tiled_gen12_mc_ccs +kms_ccs@pipe-B-bad-pixel-format-4_tiled_dg2_rc_ccs +kms_ccs@pipe-B-bad-pixel-format-4_tiled_dg2_mc_ccs +kms_ccs@pipe-B-bad-pixel-format-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-B-bad-pixel-format-4_tiled_mtl_rc_ccs +kms_ccs@pipe-B-bad-pixel-format-4_tiled_mtl_mc_ccs +kms_ccs@pipe-B-bad-pixel-format-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-B-bad-rotation-90-y_tiled_ccs +kms_ccs@pipe-B-bad-rotation-90-yf_tiled_ccs +kms_ccs@pipe-B-bad-rotation-90-y_tiled_gen12_rc_ccs +kms_ccs@pipe-B-bad-rotation-90-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-B-bad-rotation-90-y_tiled_gen12_mc_ccs +kms_ccs@pipe-B-bad-rotation-90-4_tiled_dg2_rc_ccs +kms_ccs@pipe-B-bad-rotation-90-4_tiled_dg2_mc_ccs +kms_ccs@pipe-B-bad-rotation-90-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-B-bad-rotation-90-4_tiled_mtl_rc_ccs +kms_ccs@pipe-B-bad-rotation-90-4_tiled_mtl_mc_ccs +kms_ccs@pipe-B-bad-rotation-90-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-B-crc-primary-basic-y_tiled_ccs +kms_ccs@pipe-B-crc-primary-basic-yf_tiled_ccs +kms_ccs@pipe-B-crc-primary-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-B-crc-primary-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-B-crc-primary-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-B-crc-primary-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-B-crc-primary-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-B-crc-primary-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-B-crc-primary-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-B-crc-primary-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-B-crc-primary-basic-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-B-crc-primary-rotation-180-y_tiled_ccs +kms_ccs@pipe-B-crc-primary-rotation-180-yf_tiled_ccs +kms_ccs@pipe-B-crc-primary-rotation-180-y_tiled_gen12_rc_ccs +kms_ccs@pipe-B-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-B-crc-primary-rotation-180-y_tiled_gen12_mc_ccs +kms_ccs@pipe-B-crc-primary-rotation-180-4_tiled_dg2_rc_ccs +kms_ccs@pipe-B-crc-primary-rotation-180-4_tiled_dg2_mc_ccs +kms_ccs@pipe-B-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-B-crc-primary-rotation-180-4_tiled_mtl_rc_ccs +kms_ccs@pipe-B-crc-primary-rotation-180-4_tiled_mtl_mc_ccs +kms_ccs@pipe-B-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-B-random-ccs-data-y_tiled_ccs +kms_ccs@pipe-B-random-ccs-data-yf_tiled_ccs +kms_ccs@pipe-B-random-ccs-data-y_tiled_gen12_rc_ccs +kms_ccs@pipe-B-random-ccs-data-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-B-random-ccs-data-y_tiled_gen12_mc_ccs +kms_ccs@pipe-B-random-ccs-data-4_tiled_dg2_rc_ccs +kms_ccs@pipe-B-random-ccs-data-4_tiled_dg2_mc_ccs +kms_ccs@pipe-B-random-ccs-data-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-B-random-ccs-data-4_tiled_mtl_rc_ccs +kms_ccs@pipe-B-random-ccs-data-4_tiled_mtl_mc_ccs +kms_ccs@pipe-B-random-ccs-data-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-B-missing-ccs-buffer-y_tiled_ccs +kms_ccs@pipe-B-missing-ccs-buffer-yf_tiled_ccs +kms_ccs@pipe-B-missing-ccs-buffer-y_tiled_gen12_rc_ccs +kms_ccs@pipe-B-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-B-missing-ccs-buffer-y_tiled_gen12_mc_ccs +kms_ccs@pipe-B-missing-ccs-buffer-4_tiled_mtl_rc_ccs +kms_ccs@pipe-B-missing-ccs-buffer-4_tiled_mtl_mc_ccs +kms_ccs@pipe-B-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-B-ccs-on-another-bo-y_tiled_ccs +kms_ccs@pipe-B-ccs-on-another-bo-yf_tiled_ccs +kms_ccs@pipe-B-ccs-on-another-bo-y_tiled_gen12_rc_ccs +kms_ccs@pipe-B-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-B-ccs-on-another-bo-y_tiled_gen12_mc_ccs +kms_ccs@pipe-B-ccs-on-another-bo-4_tiled_mtl_rc_ccs +kms_ccs@pipe-B-ccs-on-another-bo-4_tiled_mtl_mc_ccs +kms_ccs@pipe-B-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-B-bad-aux-stride-y_tiled_ccs +kms_ccs@pipe-B-bad-aux-stride-yf_tiled_ccs +kms_ccs@pipe-B-bad-aux-stride-y_tiled_gen12_rc_ccs +kms_ccs@pipe-B-bad-aux-stride-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-B-bad-aux-stride-y_tiled_gen12_mc_ccs +kms_ccs@pipe-B-bad-aux-stride-4_tiled_mtl_rc_ccs +kms_ccs@pipe-B-bad-aux-stride-4_tiled_mtl_mc_ccs +kms_ccs@pipe-B-bad-aux-stride-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-B-crc-sprite-planes-basic-y_tiled_ccs +kms_ccs@pipe-B-crc-sprite-planes-basic-yf_tiled_ccs +kms_ccs@pipe-B-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-B-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-B-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-B-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-B-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-B-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-B-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-B-crc-sprite-planes-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-B-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-C-bad-pixel-format-y_tiled_ccs +kms_ccs@pipe-C-bad-pixel-format-yf_tiled_ccs +kms_ccs@pipe-C-bad-pixel-format-y_tiled_gen12_rc_ccs +kms_ccs@pipe-C-bad-pixel-format-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-C-bad-pixel-format-y_tiled_gen12_mc_ccs +kms_ccs@pipe-C-bad-pixel-format-4_tiled_dg2_rc_ccs +kms_ccs@pipe-C-bad-pixel-format-4_tiled_dg2_mc_ccs +kms_ccs@pipe-C-bad-pixel-format-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-C-bad-pixel-format-4_tiled_mtl_rc_ccs +kms_ccs@pipe-C-bad-pixel-format-4_tiled_mtl_mc_ccs +kms_ccs@pipe-C-bad-pixel-format-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-C-bad-rotation-90-y_tiled_ccs +kms_ccs@pipe-C-bad-rotation-90-yf_tiled_ccs +kms_ccs@pipe-C-bad-rotation-90-y_tiled_gen12_rc_ccs +kms_ccs@pipe-C-bad-rotation-90-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-C-bad-rotation-90-y_tiled_gen12_mc_ccs +kms_ccs@pipe-C-bad-rotation-90-4_tiled_dg2_rc_ccs +kms_ccs@pipe-C-bad-rotation-90-4_tiled_dg2_mc_ccs +kms_ccs@pipe-C-bad-rotation-90-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-C-bad-rotation-90-4_tiled_mtl_rc_ccs +kms_ccs@pipe-C-bad-rotation-90-4_tiled_mtl_mc_ccs +kms_ccs@pipe-C-bad-rotation-90-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-C-crc-primary-basic-y_tiled_ccs +kms_ccs@pipe-C-crc-primary-basic-yf_tiled_ccs +kms_ccs@pipe-C-crc-primary-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-C-crc-primary-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-C-crc-primary-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-C-crc-primary-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-C-crc-primary-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-C-crc-primary-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-C-crc-primary-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-C-crc-primary-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-C-crc-primary-basic-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-C-crc-primary-rotation-180-y_tiled_ccs +kms_ccs@pipe-C-crc-primary-rotation-180-yf_tiled_ccs +kms_ccs@pipe-C-crc-primary-rotation-180-y_tiled_gen12_rc_ccs +kms_ccs@pipe-C-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-C-crc-primary-rotation-180-y_tiled_gen12_mc_ccs +kms_ccs@pipe-C-crc-primary-rotation-180-4_tiled_dg2_rc_ccs +kms_ccs@pipe-C-crc-primary-rotation-180-4_tiled_dg2_mc_ccs +kms_ccs@pipe-C-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-C-crc-primary-rotation-180-4_tiled_mtl_rc_ccs +kms_ccs@pipe-C-crc-primary-rotation-180-4_tiled_mtl_mc_ccs +kms_ccs@pipe-C-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-C-random-ccs-data-y_tiled_ccs +kms_ccs@pipe-C-random-ccs-data-yf_tiled_ccs +kms_ccs@pipe-C-random-ccs-data-y_tiled_gen12_rc_ccs +kms_ccs@pipe-C-random-ccs-data-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-C-random-ccs-data-y_tiled_gen12_mc_ccs +kms_ccs@pipe-C-random-ccs-data-4_tiled_dg2_rc_ccs +kms_ccs@pipe-C-random-ccs-data-4_tiled_dg2_mc_ccs +kms_ccs@pipe-C-random-ccs-data-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-C-random-ccs-data-4_tiled_mtl_rc_ccs +kms_ccs@pipe-C-random-ccs-data-4_tiled_mtl_mc_ccs +kms_ccs@pipe-C-random-ccs-data-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-C-missing-ccs-buffer-y_tiled_ccs +kms_ccs@pipe-C-missing-ccs-buffer-yf_tiled_ccs +kms_ccs@pipe-C-missing-ccs-buffer-y_tiled_gen12_rc_ccs +kms_ccs@pipe-C-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-C-missing-ccs-buffer-y_tiled_gen12_mc_ccs +kms_ccs@pipe-C-missing-ccs-buffer-4_tiled_mtl_rc_ccs +kms_ccs@pipe-C-missing-ccs-buffer-4_tiled_mtl_mc_ccs +kms_ccs@pipe-C-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-C-ccs-on-another-bo-y_tiled_ccs +kms_ccs@pipe-C-ccs-on-another-bo-yf_tiled_ccs +kms_ccs@pipe-C-ccs-on-another-bo-y_tiled_gen12_rc_ccs +kms_ccs@pipe-C-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-C-ccs-on-another-bo-y_tiled_gen12_mc_ccs +kms_ccs@pipe-C-ccs-on-another-bo-4_tiled_mtl_rc_ccs +kms_ccs@pipe-C-ccs-on-another-bo-4_tiled_mtl_mc_ccs +kms_ccs@pipe-C-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-C-bad-aux-stride-y_tiled_ccs +kms_ccs@pipe-C-bad-aux-stride-yf_tiled_ccs +kms_ccs@pipe-C-bad-aux-stride-y_tiled_gen12_rc_ccs +kms_ccs@pipe-C-bad-aux-stride-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-C-bad-aux-stride-y_tiled_gen12_mc_ccs +kms_ccs@pipe-C-bad-aux-stride-4_tiled_mtl_rc_ccs +kms_ccs@pipe-C-bad-aux-stride-4_tiled_mtl_mc_ccs +kms_ccs@pipe-C-bad-aux-stride-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-C-crc-sprite-planes-basic-y_tiled_ccs +kms_ccs@pipe-C-crc-sprite-planes-basic-yf_tiled_ccs +kms_ccs@pipe-C-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-C-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-C-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-C-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-C-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-C-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-C-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-C-crc-sprite-planes-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-C-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-D-bad-pixel-format-y_tiled_ccs +kms_ccs@pipe-D-bad-pixel-format-yf_tiled_ccs +kms_ccs@pipe-D-bad-pixel-format-y_tiled_gen12_rc_ccs +kms_ccs@pipe-D-bad-pixel-format-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-D-bad-pixel-format-y_tiled_gen12_mc_ccs +kms_ccs@pipe-D-bad-pixel-format-4_tiled_dg2_rc_ccs +kms_ccs@pipe-D-bad-pixel-format-4_tiled_dg2_mc_ccs +kms_ccs@pipe-D-bad-pixel-format-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-D-bad-pixel-format-4_tiled_mtl_rc_ccs +kms_ccs@pipe-D-bad-pixel-format-4_tiled_mtl_mc_ccs +kms_ccs@pipe-D-bad-pixel-format-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-D-bad-rotation-90-y_tiled_ccs +kms_ccs@pipe-D-bad-rotation-90-yf_tiled_ccs +kms_ccs@pipe-D-bad-rotation-90-y_tiled_gen12_rc_ccs +kms_ccs@pipe-D-bad-rotation-90-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-D-bad-rotation-90-y_tiled_gen12_mc_ccs +kms_ccs@pipe-D-bad-rotation-90-4_tiled_dg2_rc_ccs +kms_ccs@pipe-D-bad-rotation-90-4_tiled_dg2_mc_ccs +kms_ccs@pipe-D-bad-rotation-90-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-D-bad-rotation-90-4_tiled_mtl_rc_ccs +kms_ccs@pipe-D-bad-rotation-90-4_tiled_mtl_mc_ccs +kms_ccs@pipe-D-bad-rotation-90-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-D-crc-primary-basic-y_tiled_ccs +kms_ccs@pipe-D-crc-primary-basic-yf_tiled_ccs +kms_ccs@pipe-D-crc-primary-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-D-crc-primary-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-D-crc-primary-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-D-crc-primary-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-D-crc-primary-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-D-crc-primary-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-D-crc-primary-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-D-crc-primary-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-D-crc-primary-basic-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-D-crc-primary-rotation-180-y_tiled_ccs +kms_ccs@pipe-D-crc-primary-rotation-180-yf_tiled_ccs +kms_ccs@pipe-D-crc-primary-rotation-180-y_tiled_gen12_rc_ccs +kms_ccs@pipe-D-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-D-crc-primary-rotation-180-y_tiled_gen12_mc_ccs +kms_ccs@pipe-D-crc-primary-rotation-180-4_tiled_dg2_rc_ccs +kms_ccs@pipe-D-crc-primary-rotation-180-4_tiled_dg2_mc_ccs +kms_ccs@pipe-D-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-D-crc-primary-rotation-180-4_tiled_mtl_rc_ccs +kms_ccs@pipe-D-crc-primary-rotation-180-4_tiled_mtl_mc_ccs +kms_ccs@pipe-D-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-D-random-ccs-data-y_tiled_ccs +kms_ccs@pipe-D-random-ccs-data-yf_tiled_ccs +kms_ccs@pipe-D-random-ccs-data-y_tiled_gen12_rc_ccs +kms_ccs@pipe-D-random-ccs-data-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-D-random-ccs-data-y_tiled_gen12_mc_ccs +kms_ccs@pipe-D-random-ccs-data-4_tiled_dg2_rc_ccs +kms_ccs@pipe-D-random-ccs-data-4_tiled_dg2_mc_ccs +kms_ccs@pipe-D-random-ccs-data-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-D-random-ccs-data-4_tiled_mtl_rc_ccs +kms_ccs@pipe-D-random-ccs-data-4_tiled_mtl_mc_ccs +kms_ccs@pipe-D-random-ccs-data-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-D-missing-ccs-buffer-y_tiled_ccs +kms_ccs@pipe-D-missing-ccs-buffer-yf_tiled_ccs +kms_ccs@pipe-D-missing-ccs-buffer-y_tiled_gen12_rc_ccs +kms_ccs@pipe-D-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-D-missing-ccs-buffer-y_tiled_gen12_mc_ccs +kms_ccs@pipe-D-missing-ccs-buffer-4_tiled_mtl_rc_ccs +kms_ccs@pipe-D-missing-ccs-buffer-4_tiled_mtl_mc_ccs +kms_ccs@pipe-D-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-D-ccs-on-another-bo-y_tiled_ccs +kms_ccs@pipe-D-ccs-on-another-bo-yf_tiled_ccs +kms_ccs@pipe-D-ccs-on-another-bo-y_tiled_gen12_rc_ccs +kms_ccs@pipe-D-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-D-ccs-on-another-bo-y_tiled_gen12_mc_ccs +kms_ccs@pipe-D-ccs-on-another-bo-4_tiled_mtl_rc_ccs +kms_ccs@pipe-D-ccs-on-another-bo-4_tiled_mtl_mc_ccs +kms_ccs@pipe-D-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-D-bad-aux-stride-y_tiled_ccs +kms_ccs@pipe-D-bad-aux-stride-yf_tiled_ccs +kms_ccs@pipe-D-bad-aux-stride-y_tiled_gen12_rc_ccs +kms_ccs@pipe-D-bad-aux-stride-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-D-bad-aux-stride-y_tiled_gen12_mc_ccs +kms_ccs@pipe-D-bad-aux-stride-4_tiled_mtl_rc_ccs +kms_ccs@pipe-D-bad-aux-stride-4_tiled_mtl_mc_ccs +kms_ccs@pipe-D-bad-aux-stride-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-D-crc-sprite-planes-basic-y_tiled_ccs +kms_ccs@pipe-D-crc-sprite-planes-basic-yf_tiled_ccs +kms_ccs@pipe-D-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-D-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-D-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-D-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-D-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-D-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-D-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-D-crc-sprite-planes-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-D-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-E-bad-pixel-format-y_tiled_ccs +kms_ccs@pipe-E-bad-pixel-format-yf_tiled_ccs +kms_ccs@pipe-E-bad-pixel-format-y_tiled_gen12_rc_ccs +kms_ccs@pipe-E-bad-pixel-format-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-E-bad-pixel-format-y_tiled_gen12_mc_ccs +kms_ccs@pipe-E-bad-pixel-format-4_tiled_dg2_rc_ccs +kms_ccs@pipe-E-bad-pixel-format-4_tiled_dg2_mc_ccs +kms_ccs@pipe-E-bad-pixel-format-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-E-bad-pixel-format-4_tiled_mtl_rc_ccs +kms_ccs@pipe-E-bad-pixel-format-4_tiled_mtl_mc_ccs +kms_ccs@pipe-E-bad-pixel-format-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-E-bad-rotation-90-y_tiled_ccs +kms_ccs@pipe-E-bad-rotation-90-yf_tiled_ccs +kms_ccs@pipe-E-bad-rotation-90-y_tiled_gen12_rc_ccs +kms_ccs@pipe-E-bad-rotation-90-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-E-bad-rotation-90-y_tiled_gen12_mc_ccs +kms_ccs@pipe-E-bad-rotation-90-4_tiled_dg2_rc_ccs +kms_ccs@pipe-E-bad-rotation-90-4_tiled_dg2_mc_ccs +kms_ccs@pipe-E-bad-rotation-90-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-E-bad-rotation-90-4_tiled_mtl_rc_ccs +kms_ccs@pipe-E-bad-rotation-90-4_tiled_mtl_mc_ccs +kms_ccs@pipe-E-bad-rotation-90-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-E-crc-primary-basic-y_tiled_ccs +kms_ccs@pipe-E-crc-primary-basic-yf_tiled_ccs +kms_ccs@pipe-E-crc-primary-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-E-crc-primary-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-E-crc-primary-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-E-crc-primary-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-E-crc-primary-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-E-crc-primary-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-E-crc-primary-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-E-crc-primary-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-E-crc-primary-basic-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-E-crc-primary-rotation-180-y_tiled_ccs +kms_ccs@pipe-E-crc-primary-rotation-180-yf_tiled_ccs +kms_ccs@pipe-E-crc-primary-rotation-180-y_tiled_gen12_rc_ccs +kms_ccs@pipe-E-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-E-crc-primary-rotation-180-y_tiled_gen12_mc_ccs +kms_ccs@pipe-E-crc-primary-rotation-180-4_tiled_dg2_rc_ccs +kms_ccs@pipe-E-crc-primary-rotation-180-4_tiled_dg2_mc_ccs +kms_ccs@pipe-E-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-E-crc-primary-rotation-180-4_tiled_mtl_rc_ccs +kms_ccs@pipe-E-crc-primary-rotation-180-4_tiled_mtl_mc_ccs +kms_ccs@pipe-E-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-E-random-ccs-data-y_tiled_ccs +kms_ccs@pipe-E-random-ccs-data-yf_tiled_ccs +kms_ccs@pipe-E-random-ccs-data-y_tiled_gen12_rc_ccs +kms_ccs@pipe-E-random-ccs-data-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-E-random-ccs-data-y_tiled_gen12_mc_ccs +kms_ccs@pipe-E-random-ccs-data-4_tiled_dg2_rc_ccs +kms_ccs@pipe-E-random-ccs-data-4_tiled_dg2_mc_ccs +kms_ccs@pipe-E-random-ccs-data-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-E-random-ccs-data-4_tiled_mtl_rc_ccs +kms_ccs@pipe-E-random-ccs-data-4_tiled_mtl_mc_ccs +kms_ccs@pipe-E-random-ccs-data-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-E-missing-ccs-buffer-y_tiled_ccs +kms_ccs@pipe-E-missing-ccs-buffer-yf_tiled_ccs +kms_ccs@pipe-E-missing-ccs-buffer-y_tiled_gen12_rc_ccs +kms_ccs@pipe-E-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-E-missing-ccs-buffer-y_tiled_gen12_mc_ccs +kms_ccs@pipe-E-missing-ccs-buffer-4_tiled_mtl_rc_ccs +kms_ccs@pipe-E-missing-ccs-buffer-4_tiled_mtl_mc_ccs +kms_ccs@pipe-E-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-E-ccs-on-another-bo-y_tiled_ccs +kms_ccs@pipe-E-ccs-on-another-bo-yf_tiled_ccs +kms_ccs@pipe-E-ccs-on-another-bo-y_tiled_gen12_rc_ccs +kms_ccs@pipe-E-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-E-ccs-on-another-bo-y_tiled_gen12_mc_ccs +kms_ccs@pipe-E-ccs-on-another-bo-4_tiled_mtl_rc_ccs +kms_ccs@pipe-E-ccs-on-another-bo-4_tiled_mtl_mc_ccs +kms_ccs@pipe-E-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-E-bad-aux-stride-y_tiled_ccs +kms_ccs@pipe-E-bad-aux-stride-yf_tiled_ccs +kms_ccs@pipe-E-bad-aux-stride-y_tiled_gen12_rc_ccs +kms_ccs@pipe-E-bad-aux-stride-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-E-bad-aux-stride-y_tiled_gen12_mc_ccs +kms_ccs@pipe-E-bad-aux-stride-4_tiled_mtl_rc_ccs +kms_ccs@pipe-E-bad-aux-stride-4_tiled_mtl_mc_ccs +kms_ccs@pipe-E-bad-aux-stride-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-E-crc-sprite-planes-basic-y_tiled_ccs +kms_ccs@pipe-E-crc-sprite-planes-basic-yf_tiled_ccs +kms_ccs@pipe-E-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-E-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-E-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-E-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-E-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-E-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-E-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-E-crc-sprite-planes-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-E-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-F-bad-pixel-format-y_tiled_ccs +kms_ccs@pipe-F-bad-pixel-format-yf_tiled_ccs +kms_ccs@pipe-F-bad-pixel-format-y_tiled_gen12_rc_ccs +kms_ccs@pipe-F-bad-pixel-format-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-F-bad-pixel-format-y_tiled_gen12_mc_ccs +kms_ccs@pipe-F-bad-pixel-format-4_tiled_dg2_rc_ccs +kms_ccs@pipe-F-bad-pixel-format-4_tiled_dg2_mc_ccs +kms_ccs@pipe-F-bad-pixel-format-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-F-bad-pixel-format-4_tiled_mtl_rc_ccs +kms_ccs@pipe-F-bad-pixel-format-4_tiled_mtl_mc_ccs +kms_ccs@pipe-F-bad-pixel-format-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-F-bad-rotation-90-y_tiled_ccs +kms_ccs@pipe-F-bad-rotation-90-yf_tiled_ccs +kms_ccs@pipe-F-bad-rotation-90-y_tiled_gen12_rc_ccs +kms_ccs@pipe-F-bad-rotation-90-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-F-bad-rotation-90-y_tiled_gen12_mc_ccs +kms_ccs@pipe-F-bad-rotation-90-4_tiled_dg2_rc_ccs +kms_ccs@pipe-F-bad-rotation-90-4_tiled_dg2_mc_ccs +kms_ccs@pipe-F-bad-rotation-90-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-F-bad-rotation-90-4_tiled_mtl_rc_ccs +kms_ccs@pipe-F-bad-rotation-90-4_tiled_mtl_mc_ccs +kms_ccs@pipe-F-bad-rotation-90-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-F-crc-primary-basic-y_tiled_ccs +kms_ccs@pipe-F-crc-primary-basic-yf_tiled_ccs +kms_ccs@pipe-F-crc-primary-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-F-crc-primary-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-F-crc-primary-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-F-crc-primary-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-F-crc-primary-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-F-crc-primary-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-F-crc-primary-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-F-crc-primary-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-F-crc-primary-basic-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-F-crc-primary-rotation-180-y_tiled_ccs +kms_ccs@pipe-F-crc-primary-rotation-180-yf_tiled_ccs +kms_ccs@pipe-F-crc-primary-rotation-180-y_tiled_gen12_rc_ccs +kms_ccs@pipe-F-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-F-crc-primary-rotation-180-y_tiled_gen12_mc_ccs +kms_ccs@pipe-F-crc-primary-rotation-180-4_tiled_dg2_rc_ccs +kms_ccs@pipe-F-crc-primary-rotation-180-4_tiled_dg2_mc_ccs +kms_ccs@pipe-F-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-F-crc-primary-rotation-180-4_tiled_mtl_rc_ccs +kms_ccs@pipe-F-crc-primary-rotation-180-4_tiled_mtl_mc_ccs +kms_ccs@pipe-F-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-F-random-ccs-data-y_tiled_ccs +kms_ccs@pipe-F-random-ccs-data-yf_tiled_ccs +kms_ccs@pipe-F-random-ccs-data-y_tiled_gen12_rc_ccs +kms_ccs@pipe-F-random-ccs-data-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-F-random-ccs-data-y_tiled_gen12_mc_ccs +kms_ccs@pipe-F-random-ccs-data-4_tiled_dg2_rc_ccs +kms_ccs@pipe-F-random-ccs-data-4_tiled_dg2_mc_ccs +kms_ccs@pipe-F-random-ccs-data-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-F-random-ccs-data-4_tiled_mtl_rc_ccs +kms_ccs@pipe-F-random-ccs-data-4_tiled_mtl_mc_ccs +kms_ccs@pipe-F-random-ccs-data-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-F-missing-ccs-buffer-y_tiled_ccs +kms_ccs@pipe-F-missing-ccs-buffer-yf_tiled_ccs +kms_ccs@pipe-F-missing-ccs-buffer-y_tiled_gen12_rc_ccs +kms_ccs@pipe-F-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-F-missing-ccs-buffer-y_tiled_gen12_mc_ccs +kms_ccs@pipe-F-missing-ccs-buffer-4_tiled_mtl_rc_ccs +kms_ccs@pipe-F-missing-ccs-buffer-4_tiled_mtl_mc_ccs +kms_ccs@pipe-F-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-F-ccs-on-another-bo-y_tiled_ccs +kms_ccs@pipe-F-ccs-on-another-bo-yf_tiled_ccs +kms_ccs@pipe-F-ccs-on-another-bo-y_tiled_gen12_rc_ccs +kms_ccs@pipe-F-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-F-ccs-on-another-bo-y_tiled_gen12_mc_ccs +kms_ccs@pipe-F-ccs-on-another-bo-4_tiled_mtl_rc_ccs +kms_ccs@pipe-F-ccs-on-another-bo-4_tiled_mtl_mc_ccs +kms_ccs@pipe-F-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-F-bad-aux-stride-y_tiled_ccs +kms_ccs@pipe-F-bad-aux-stride-yf_tiled_ccs +kms_ccs@pipe-F-bad-aux-stride-y_tiled_gen12_rc_ccs +kms_ccs@pipe-F-bad-aux-stride-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-F-bad-aux-stride-y_tiled_gen12_mc_ccs +kms_ccs@pipe-F-bad-aux-stride-4_tiled_mtl_rc_ccs +kms_ccs@pipe-F-bad-aux-stride-4_tiled_mtl_mc_ccs +kms_ccs@pipe-F-bad-aux-stride-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-F-crc-sprite-planes-basic-y_tiled_ccs +kms_ccs@pipe-F-crc-sprite-planes-basic-yf_tiled_ccs +kms_ccs@pipe-F-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-F-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-F-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-F-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-F-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-F-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-F-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-F-crc-sprite-planes-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-F-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-G-bad-pixel-format-y_tiled_ccs +kms_ccs@pipe-G-bad-pixel-format-yf_tiled_ccs +kms_ccs@pipe-G-bad-pixel-format-y_tiled_gen12_rc_ccs +kms_ccs@pipe-G-bad-pixel-format-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-G-bad-pixel-format-y_tiled_gen12_mc_ccs +kms_ccs@pipe-G-bad-pixel-format-4_tiled_dg2_rc_ccs +kms_ccs@pipe-G-bad-pixel-format-4_tiled_dg2_mc_ccs +kms_ccs@pipe-G-bad-pixel-format-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-G-bad-pixel-format-4_tiled_mtl_rc_ccs +kms_ccs@pipe-G-bad-pixel-format-4_tiled_mtl_mc_ccs +kms_ccs@pipe-G-bad-pixel-format-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-G-bad-rotation-90-y_tiled_ccs +kms_ccs@pipe-G-bad-rotation-90-yf_tiled_ccs +kms_ccs@pipe-G-bad-rotation-90-y_tiled_gen12_rc_ccs +kms_ccs@pipe-G-bad-rotation-90-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-G-bad-rotation-90-y_tiled_gen12_mc_ccs +kms_ccs@pipe-G-bad-rotation-90-4_tiled_dg2_rc_ccs +kms_ccs@pipe-G-bad-rotation-90-4_tiled_dg2_mc_ccs +kms_ccs@pipe-G-bad-rotation-90-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-G-bad-rotation-90-4_tiled_mtl_rc_ccs +kms_ccs@pipe-G-bad-rotation-90-4_tiled_mtl_mc_ccs +kms_ccs@pipe-G-bad-rotation-90-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-G-crc-primary-basic-y_tiled_ccs +kms_ccs@pipe-G-crc-primary-basic-yf_tiled_ccs +kms_ccs@pipe-G-crc-primary-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-G-crc-primary-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-G-crc-primary-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-G-crc-primary-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-G-crc-primary-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-G-crc-primary-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-G-crc-primary-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-G-crc-primary-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-G-crc-primary-basic-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-G-crc-primary-rotation-180-y_tiled_ccs +kms_ccs@pipe-G-crc-primary-rotation-180-yf_tiled_ccs +kms_ccs@pipe-G-crc-primary-rotation-180-y_tiled_gen12_rc_ccs +kms_ccs@pipe-G-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-G-crc-primary-rotation-180-y_tiled_gen12_mc_ccs +kms_ccs@pipe-G-crc-primary-rotation-180-4_tiled_dg2_rc_ccs +kms_ccs@pipe-G-crc-primary-rotation-180-4_tiled_dg2_mc_ccs +kms_ccs@pipe-G-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-G-crc-primary-rotation-180-4_tiled_mtl_rc_ccs +kms_ccs@pipe-G-crc-primary-rotation-180-4_tiled_mtl_mc_ccs +kms_ccs@pipe-G-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-G-random-ccs-data-y_tiled_ccs +kms_ccs@pipe-G-random-ccs-data-yf_tiled_ccs +kms_ccs@pipe-G-random-ccs-data-y_tiled_gen12_rc_ccs +kms_ccs@pipe-G-random-ccs-data-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-G-random-ccs-data-y_tiled_gen12_mc_ccs +kms_ccs@pipe-G-random-ccs-data-4_tiled_dg2_rc_ccs +kms_ccs@pipe-G-random-ccs-data-4_tiled_dg2_mc_ccs +kms_ccs@pipe-G-random-ccs-data-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-G-random-ccs-data-4_tiled_mtl_rc_ccs +kms_ccs@pipe-G-random-ccs-data-4_tiled_mtl_mc_ccs +kms_ccs@pipe-G-random-ccs-data-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-G-missing-ccs-buffer-y_tiled_ccs +kms_ccs@pipe-G-missing-ccs-buffer-yf_tiled_ccs +kms_ccs@pipe-G-missing-ccs-buffer-y_tiled_gen12_rc_ccs +kms_ccs@pipe-G-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-G-missing-ccs-buffer-y_tiled_gen12_mc_ccs +kms_ccs@pipe-G-missing-ccs-buffer-4_tiled_mtl_rc_ccs +kms_ccs@pipe-G-missing-ccs-buffer-4_tiled_mtl_mc_ccs +kms_ccs@pipe-G-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-G-ccs-on-another-bo-y_tiled_ccs +kms_ccs@pipe-G-ccs-on-another-bo-yf_tiled_ccs +kms_ccs@pipe-G-ccs-on-another-bo-y_tiled_gen12_rc_ccs +kms_ccs@pipe-G-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-G-ccs-on-another-bo-y_tiled_gen12_mc_ccs +kms_ccs@pipe-G-ccs-on-another-bo-4_tiled_mtl_rc_ccs +kms_ccs@pipe-G-ccs-on-another-bo-4_tiled_mtl_mc_ccs +kms_ccs@pipe-G-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-G-bad-aux-stride-y_tiled_ccs +kms_ccs@pipe-G-bad-aux-stride-yf_tiled_ccs +kms_ccs@pipe-G-bad-aux-stride-y_tiled_gen12_rc_ccs +kms_ccs@pipe-G-bad-aux-stride-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-G-bad-aux-stride-y_tiled_gen12_mc_ccs +kms_ccs@pipe-G-bad-aux-stride-4_tiled_mtl_rc_ccs +kms_ccs@pipe-G-bad-aux-stride-4_tiled_mtl_mc_ccs +kms_ccs@pipe-G-bad-aux-stride-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-G-crc-sprite-planes-basic-y_tiled_ccs +kms_ccs@pipe-G-crc-sprite-planes-basic-yf_tiled_ccs +kms_ccs@pipe-G-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-G-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-G-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-G-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-G-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-G-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-G-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-G-crc-sprite-planes-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-G-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-H-bad-pixel-format-y_tiled_ccs +kms_ccs@pipe-H-bad-pixel-format-yf_tiled_ccs +kms_ccs@pipe-H-bad-pixel-format-y_tiled_gen12_rc_ccs +kms_ccs@pipe-H-bad-pixel-format-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-H-bad-pixel-format-y_tiled_gen12_mc_ccs +kms_ccs@pipe-H-bad-pixel-format-4_tiled_dg2_rc_ccs +kms_ccs@pipe-H-bad-pixel-format-4_tiled_dg2_mc_ccs +kms_ccs@pipe-H-bad-pixel-format-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-H-bad-pixel-format-4_tiled_mtl_rc_ccs +kms_ccs@pipe-H-bad-pixel-format-4_tiled_mtl_mc_ccs +kms_ccs@pipe-H-bad-pixel-format-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-H-bad-rotation-90-y_tiled_ccs +kms_ccs@pipe-H-bad-rotation-90-yf_tiled_ccs +kms_ccs@pipe-H-bad-rotation-90-y_tiled_gen12_rc_ccs +kms_ccs@pipe-H-bad-rotation-90-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-H-bad-rotation-90-y_tiled_gen12_mc_ccs +kms_ccs@pipe-H-bad-rotation-90-4_tiled_dg2_rc_ccs +kms_ccs@pipe-H-bad-rotation-90-4_tiled_dg2_mc_ccs +kms_ccs@pipe-H-bad-rotation-90-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-H-bad-rotation-90-4_tiled_mtl_rc_ccs +kms_ccs@pipe-H-bad-rotation-90-4_tiled_mtl_mc_ccs +kms_ccs@pipe-H-bad-rotation-90-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-H-crc-primary-basic-y_tiled_ccs +kms_ccs@pipe-H-crc-primary-basic-yf_tiled_ccs +kms_ccs@pipe-H-crc-primary-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-H-crc-primary-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-H-crc-primary-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-H-crc-primary-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-H-crc-primary-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-H-crc-primary-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-H-crc-primary-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-H-crc-primary-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-H-crc-primary-basic-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-H-crc-primary-rotation-180-y_tiled_ccs +kms_ccs@pipe-H-crc-primary-rotation-180-yf_tiled_ccs +kms_ccs@pipe-H-crc-primary-rotation-180-y_tiled_gen12_rc_ccs +kms_ccs@pipe-H-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-H-crc-primary-rotation-180-y_tiled_gen12_mc_ccs +kms_ccs@pipe-H-crc-primary-rotation-180-4_tiled_dg2_rc_ccs +kms_ccs@pipe-H-crc-primary-rotation-180-4_tiled_dg2_mc_ccs +kms_ccs@pipe-H-crc-primary-rotation-180-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-H-crc-primary-rotation-180-4_tiled_mtl_rc_ccs +kms_ccs@pipe-H-crc-primary-rotation-180-4_tiled_mtl_mc_ccs +kms_ccs@pipe-H-crc-primary-rotation-180-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-H-random-ccs-data-y_tiled_ccs +kms_ccs@pipe-H-random-ccs-data-yf_tiled_ccs +kms_ccs@pipe-H-random-ccs-data-y_tiled_gen12_rc_ccs +kms_ccs@pipe-H-random-ccs-data-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-H-random-ccs-data-y_tiled_gen12_mc_ccs +kms_ccs@pipe-H-random-ccs-data-4_tiled_dg2_rc_ccs +kms_ccs@pipe-H-random-ccs-data-4_tiled_dg2_mc_ccs +kms_ccs@pipe-H-random-ccs-data-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-H-random-ccs-data-4_tiled_mtl_rc_ccs +kms_ccs@pipe-H-random-ccs-data-4_tiled_mtl_mc_ccs +kms_ccs@pipe-H-random-ccs-data-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-H-missing-ccs-buffer-y_tiled_ccs +kms_ccs@pipe-H-missing-ccs-buffer-yf_tiled_ccs +kms_ccs@pipe-H-missing-ccs-buffer-y_tiled_gen12_rc_ccs +kms_ccs@pipe-H-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-H-missing-ccs-buffer-y_tiled_gen12_mc_ccs +kms_ccs@pipe-H-missing-ccs-buffer-4_tiled_mtl_rc_ccs +kms_ccs@pipe-H-missing-ccs-buffer-4_tiled_mtl_mc_ccs +kms_ccs@pipe-H-missing-ccs-buffer-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-H-ccs-on-another-bo-y_tiled_ccs +kms_ccs@pipe-H-ccs-on-another-bo-yf_tiled_ccs +kms_ccs@pipe-H-ccs-on-another-bo-y_tiled_gen12_rc_ccs +kms_ccs@pipe-H-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-H-ccs-on-another-bo-y_tiled_gen12_mc_ccs +kms_ccs@pipe-H-ccs-on-another-bo-4_tiled_mtl_rc_ccs +kms_ccs@pipe-H-ccs-on-another-bo-4_tiled_mtl_mc_ccs +kms_ccs@pipe-H-ccs-on-another-bo-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-H-bad-aux-stride-y_tiled_ccs +kms_ccs@pipe-H-bad-aux-stride-yf_tiled_ccs +kms_ccs@pipe-H-bad-aux-stride-y_tiled_gen12_rc_ccs +kms_ccs@pipe-H-bad-aux-stride-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-H-bad-aux-stride-y_tiled_gen12_mc_ccs +kms_ccs@pipe-H-bad-aux-stride-4_tiled_mtl_rc_ccs +kms_ccs@pipe-H-bad-aux-stride-4_tiled_mtl_mc_ccs +kms_ccs@pipe-H-bad-aux-stride-4_tiled_mtl_rc_ccs_cc +kms_ccs@pipe-H-crc-sprite-planes-basic-y_tiled_ccs +kms_ccs@pipe-H-crc-sprite-planes-basic-yf_tiled_ccs +kms_ccs@pipe-H-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs +kms_ccs@pipe-H-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc +kms_ccs@pipe-H-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs +kms_ccs@pipe-H-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs +kms_ccs@pipe-H-crc-sprite-planes-basic-4_tiled_dg2_mc_ccs +kms_ccs@pipe-H-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc +kms_ccs@pipe-H-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs +kms_ccs@pipe-H-crc-sprite-planes-basic-4_tiled_mtl_mc_ccs +kms_ccs@pipe-H-crc-sprite-planes-basic-4_tiled_mtl_rc_ccs_cc +kms_cdclk@plane-scaling +kms_cdclk@mode-transition +kms_cdclk@mode-transition-all-outputs +kms_color@degamma +kms_color@gamma +kms_color@legacy-gamma +kms_color@legacy-gamma-reset +kms_color@ctm-red-to-blue +kms_color@ctm-green-to-red +kms_color@ctm-blue-to-red +kms_color@ctm-max +kms_color@ctm-negative +kms_color@ctm-0-25 +kms_color@ctm-0-50 +kms_color@ctm-0-75 +kms_color@ctm-signed +kms_color@deep-color +kms_color@invalid-gamma-lut-sizes +kms_color@invalid-degamma-lut-sizes +kms_color@invalid-ctm-matrix-sizes +kms_concurrent@pipe-A +kms_concurrent@pipe-B +kms_concurrent@pipe-C +kms_concurrent@pipe-D +kms_concurrent@pipe-E +kms_concurrent@pipe-F +kms_concurrent@pipe-G +kms_concurrent@pipe-H +kms_content_protection@legacy +kms_content_protection@atomic +kms_content_protection@atomic-dpms +kms_content_protection@LIC +kms_content_protection@type1 +kms_content_protection@mei_interface +kms_content_protection@content_type_change +kms_content_protection@uevent +kms_content_protection@srm +kms_content_protection@dp-mst-type-0 +kms_content_protection@dp-mst-lic-type-0 +kms_content_protection@dp-mst-type-1 +kms_content_protection@dp-mst-lic-type-1 +kms_cursor_crc@cursor-size-change +kms_cursor_crc@cursor-alpha-opaque +kms_cursor_crc@cursor-alpha-transparent +kms_cursor_crc@cursor-dpms +kms_cursor_crc@cursor-suspend +kms_cursor_crc@cursor-onscreen-32x32 +kms_cursor_crc@cursor-offscreen-32x32 +kms_cursor_crc@cursor-sliding-32x32 +kms_cursor_crc@cursor-random-32x32 +kms_cursor_crc@cursor-rapid-movement-32x32 +kms_cursor_crc@cursor-onscreen-32x10 +kms_cursor_crc@cursor-offscreen-32x10 +kms_cursor_crc@cursor-sliding-32x10 +kms_cursor_crc@cursor-random-32x10 +kms_cursor_crc@cursor-rapid-movement-32x10 +kms_cursor_crc@cursor-onscreen-64x64 +kms_cursor_crc@cursor-offscreen-64x64 +kms_cursor_crc@cursor-sliding-64x64 +kms_cursor_crc@cursor-random-64x64 +kms_cursor_crc@cursor-rapid-movement-64x64 +kms_cursor_crc@cursor-onscreen-64x21 +kms_cursor_crc@cursor-offscreen-64x21 +kms_cursor_crc@cursor-sliding-64x21 +kms_cursor_crc@cursor-random-64x21 +kms_cursor_crc@cursor-rapid-movement-64x21 +kms_cursor_crc@cursor-onscreen-128x128 +kms_cursor_crc@cursor-offscreen-128x128 +kms_cursor_crc@cursor-sliding-128x128 +kms_cursor_crc@cursor-random-128x128 +kms_cursor_crc@cursor-rapid-movement-128x128 +kms_cursor_crc@cursor-onscreen-128x42 +kms_cursor_crc@cursor-offscreen-128x42 +kms_cursor_crc@cursor-sliding-128x42 +kms_cursor_crc@cursor-random-128x42 +kms_cursor_crc@cursor-rapid-movement-128x42 +kms_cursor_crc@cursor-onscreen-256x256 +kms_cursor_crc@cursor-offscreen-256x256 +kms_cursor_crc@cursor-sliding-256x256 +kms_cursor_crc@cursor-random-256x256 +kms_cursor_crc@cursor-rapid-movement-256x256 +kms_cursor_crc@cursor-onscreen-256x85 +kms_cursor_crc@cursor-offscreen-256x85 +kms_cursor_crc@cursor-sliding-256x85 +kms_cursor_crc@cursor-random-256x85 +kms_cursor_crc@cursor-rapid-movement-256x85 +kms_cursor_crc@cursor-onscreen-512x512 +kms_cursor_crc@cursor-offscreen-512x512 +kms_cursor_crc@cursor-sliding-512x512 +kms_cursor_crc@cursor-random-512x512 +kms_cursor_crc@cursor-rapid-movement-512x512 +kms_cursor_crc@cursor-onscreen-512x170 +kms_cursor_crc@cursor-offscreen-512x170 +kms_cursor_crc@cursor-sliding-512x170 +kms_cursor_crc@cursor-random-512x170 +kms_cursor_crc@cursor-rapid-movement-512x170 +kms_cursor_crc@cursor-onscreen-max-size +kms_cursor_crc@cursor-offscreen-max-size +kms_cursor_crc@cursor-sliding-max-size +kms_cursor_crc@cursor-random-max-size +kms_cursor_crc@cursor-rapid-movement-max-size +kms_cursor_legacy@single-bo +kms_cursor_legacy@single-move +kms_cursor_legacy@forked-bo +kms_cursor_legacy@forked-move +kms_cursor_legacy@torture-bo +kms_cursor_legacy@torture-move +kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic +kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic +kms_cursor_legacy@2x-flip-vs-cursor-legacy +kms_cursor_legacy@2x-flip-vs-cursor-atomic +kms_cursor_legacy@2x-long-flip-vs-cursor-legacy +kms_cursor_legacy@2x-long-flip-vs-cursor-atomic +kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic +kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic +kms_cursor_legacy@2x-cursor-vs-flip-legacy +kms_cursor_legacy@2x-long-cursor-vs-flip-legacy +kms_cursor_legacy@2x-cursor-vs-flip-atomic +kms_cursor_legacy@2x-long-cursor-vs-flip-atomic +kms_cursor_legacy@flip-vs-cursor-crc-legacy +kms_cursor_legacy@flip-vs-cursor-crc-atomic +kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy +kms_cursor_legacy@flip-vs-cursor-busy-crc-atomic +kms_cursor_legacy@basic-flip-before-cursor-legacy +kms_cursor_legacy@basic-busy-flip-before-cursor-legacy +kms_cursor_legacy@basic-flip-after-cursor-legacy +kms_cursor_legacy@basic-flip-before-cursor-varying-size +kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size +kms_cursor_legacy@basic-flip-after-cursor-varying-size +kms_cursor_legacy@short-flip-before-cursor-toggle +kms_cursor_legacy@short-busy-flip-before-cursor-toggle +kms_cursor_legacy@short-flip-after-cursor-toggle +kms_cursor_legacy@basic-flip-before-cursor-atomic +kms_cursor_legacy@basic-busy-flip-before-cursor-atomic +kms_cursor_legacy@basic-flip-after-cursor-atomic +kms_cursor_legacy@short-flip-before-cursor-atomic-transitions +kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions +kms_cursor_legacy@short-flip-after-cursor-atomic-transitions +kms_cursor_legacy@short-flip-before-cursor-atomic-transitions-varying-size +kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size +kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size +kms_cursor_legacy@cursor-vs-flip-legacy +kms_cursor_legacy@flip-vs-cursor-legacy +kms_cursor_legacy@cursorA-vs-flipA-legacy +kms_cursor_legacy@cursorA-vs-flipB-legacy +kms_cursor_legacy@cursorB-vs-flipA-legacy +kms_cursor_legacy@cursorB-vs-flipB-legacy +kms_cursor_legacy@cursor-vs-flip-varying-size +kms_cursor_legacy@flip-vs-cursor-varying-size +kms_cursor_legacy@cursorA-vs-flipA-varying-size +kms_cursor_legacy@cursorA-vs-flipB-varying-size +kms_cursor_legacy@cursorB-vs-flipA-varying-size +kms_cursor_legacy@cursorB-vs-flipB-varying-size +kms_cursor_legacy@cursor-vs-flip-toggle +kms_cursor_legacy@flip-vs-cursor-toggle +kms_cursor_legacy@cursorA-vs-flipA-toggle +kms_cursor_legacy@cursorA-vs-flipB-toggle +kms_cursor_legacy@cursorB-vs-flipA-toggle +kms_cursor_legacy@cursorB-vs-flipB-toggle +kms_cursor_legacy@cursor-vs-flip-atomic +kms_cursor_legacy@flip-vs-cursor-atomic +kms_cursor_legacy@cursorA-vs-flipA-atomic +kms_cursor_legacy@cursorA-vs-flipB-atomic +kms_cursor_legacy@cursorB-vs-flipA-atomic +kms_cursor_legacy@cursorB-vs-flipB-atomic +kms_cursor_legacy@cursor-vs-flip-atomic-transitions +kms_cursor_legacy@flip-vs-cursor-atomic-transitions +kms_cursor_legacy@cursorA-vs-flipA-atomic-transitions +kms_cursor_legacy@cursorA-vs-flipB-atomic-transitions +kms_cursor_legacy@cursorB-vs-flipA-atomic-transitions +kms_cursor_legacy@cursorB-vs-flipB-atomic-transitions +kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size +kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size +kms_cursor_legacy@cursorA-vs-flipA-atomic-transitions-varying-size +kms_cursor_legacy@cursorA-vs-flipB-atomic-transitions-varying-size +kms_cursor_legacy@cursorB-vs-flipA-atomic-transitions-varying-size +kms_cursor_legacy@cursorB-vs-flipB-atomic-transitions-varying-size +kms_dither@FB-8BPC-Vs-Panel-6BPC +kms_dither@FB-8BPC-Vs-Panel-8BPC +kms_dp_aux_dev +kms_tiled_display@basic-test-pattern +kms_tiled_display@basic-test-pattern-with-chamelium +kms_draw_crc@draw-method-mmap-cpu +kms_draw_crc@draw-method-mmap-gtt +kms_draw_crc@draw-method-mmap-wc +kms_draw_crc@draw-method-pwrite +kms_draw_crc@draw-method-blt +kms_draw_crc@draw-method-render +kms_draw_crc@fill-fb +kms_dsc@dsc-basic +kms_dsc@dsc-with-formats +kms_dsc@dsc-with-bpc +kms_dsc@dsc-with-bpc-formats +kms_dsc@dsc-with-output-formats +kms_fbcon_fbt@fbc +kms_fbcon_fbt@psr +kms_fbcon_fbt@fbc-suspend +kms_fbcon_fbt@psr-suspend +kms_fence_pin_leak +kms_flip@nonblocking-read +kms_flip@wf_vblank-ts-check +kms_flip@2x-wf_vblank-ts-check +kms_flip@blocking-wf_vblank +kms_flip@2x-blocking-wf_vblank +kms_flip@absolute-wf_vblank +kms_flip@2x-absolute-wf_vblank +kms_flip@blocking-absolute-wf_vblank +kms_flip@2x-blocking-absolute-wf_vblank +kms_flip@basic-plain-flip +kms_flip@2x-plain-flip +kms_flip@busy-flip +kms_flip@2x-busy-flip +kms_flip@flip-vs-fences +kms_flip@2x-flip-vs-fences +kms_flip@plain-flip-ts-check +kms_flip@2x-plain-flip-ts-check +kms_flip@plain-flip-fb-recreate +kms_flip@2x-plain-flip-fb-recreate +kms_flip@flip-vs-rmfb +kms_flip@2x-flip-vs-rmfb +kms_flip@basic-flip-vs-dpms +kms_flip@2x-flip-vs-dpms +kms_flip@flip-vs-panning +kms_flip@2x-flip-vs-panning +kms_flip@basic-flip-vs-modeset +kms_flip@2x-flip-vs-modeset +kms_flip@flip-vs-expired-vblank +kms_flip@2x-flip-vs-expired-vblank +kms_flip@flip-vs-absolute-wf_vblank +kms_flip@2x-flip-vs-absolute-wf_vblank +kms_flip@basic-flip-vs-wf_vblank +kms_flip@2x-flip-vs-wf_vblank +kms_flip@flip-vs-blocking-wf-vblank +kms_flip@2x-flip-vs-blocking-wf-vblank +kms_flip@flip-vs-modeset-vs-hang +kms_flip@2x-flip-vs-modeset-vs-hang +kms_flip@flip-vs-panning-vs-hang +kms_flip@2x-flip-vs-panning-vs-hang +kms_flip@flip-vs-dpms-off-vs-modeset +kms_flip@2x-flip-vs-dpms-off-vs-modeset +kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset +kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset +kms_flip@dpms-off-confusion +kms_flip@nonexisting-fb +kms_flip@2x-nonexisting-fb +kms_flip@dpms-vs-vblank-race +kms_flip@2x-dpms-vs-vblank-race +kms_flip@modeset-vs-vblank-race +kms_flip@2x-modeset-vs-vblank-race +kms_flip@bo-too-big +kms_flip@flip-vs-suspend +kms_flip@2x-flip-vs-suspend +kms_flip@wf_vblank-ts-check-interruptible +kms_flip@2x-wf_vblank-ts-check-interruptible +kms_flip@absolute-wf_vblank-interruptible +kms_flip@2x-absolute-wf_vblank-interruptible +kms_flip@blocking-absolute-wf_vblank-interruptible +kms_flip@2x-blocking-absolute-wf_vblank-interruptible +kms_flip@plain-flip-interruptible +kms_flip@2x-plain-flip-interruptible +kms_flip@flip-vs-fences-interruptible +kms_flip@2x-flip-vs-fences-interruptible +kms_flip@plain-flip-ts-check-interruptible +kms_flip@2x-plain-flip-ts-check-interruptible +kms_flip@plain-flip-fb-recreate-interruptible +kms_flip@2x-plain-flip-fb-recreate-interruptible +kms_flip@flip-vs-rmfb-interruptible +kms_flip@2x-flip-vs-rmfb-interruptible +kms_flip@flip-vs-panning-interruptible +kms_flip@2x-flip-vs-panning-interruptible +kms_flip@flip-vs-expired-vblank-interruptible +kms_flip@2x-flip-vs-expired-vblank-interruptible +kms_flip@flip-vs-absolute-wf_vblank-interruptible +kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible +kms_flip@flip-vs-wf_vblank-interruptible +kms_flip@2x-flip-vs-wf_vblank-interruptible +kms_flip@flip-vs-dpms-off-vs-modeset-interruptible +kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible +kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible +kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible +kms_flip@dpms-off-confusion-interruptible +kms_flip@nonexisting-fb-interruptible +kms_flip@2x-nonexisting-fb-interruptible +kms_flip@dpms-vs-vblank-race-interruptible +kms_flip@2x-dpms-vs-vblank-race-interruptible +kms_flip@modeset-vs-vblank-race-interruptible +kms_flip@2x-modeset-vs-vblank-race-interruptible +kms_flip@bo-too-big-interruptible +kms_flip@flip-vs-suspend-interruptible +kms_flip@2x-flip-vs-suspend-interruptible +kms_flip_event_leak@basic +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling +kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling +kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling +kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling +kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling +kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling +kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling +kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling +kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling +kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling +kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling +kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling +kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling +kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling +kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling +kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling +kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling +kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling +kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling +kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling +kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling +kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling +kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling +kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling +kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling +kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling +kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling +kms_force_connector_basic@force-load-detect +kms_force_connector_basic@force-connector-state +kms_force_connector_basic@force-edid +kms_force_connector_basic@prune-stale-modes +kms_frontbuffer_tracking@fbc-1p-rte +kms_frontbuffer_tracking@fbc-2p-rte +kms_frontbuffer_tracking@psr-1p-rte +kms_frontbuffer_tracking@psr-2p-rte +kms_frontbuffer_tracking@fbcpsr-1p-rte +kms_frontbuffer_tracking@fbcpsr-2p-rte +kms_frontbuffer_tracking@drrs-1p-rte +kms_frontbuffer_tracking@drrs-2p-rte +kms_frontbuffer_tracking@fbcdrrs-1p-rte +kms_frontbuffer_tracking@fbcdrrs-2p-rte +kms_frontbuffer_tracking@psrdrrs-1p-rte +kms_frontbuffer_tracking@psrdrrs-2p-rte +kms_frontbuffer_tracking@fbcpsrdrrs-1p-rte +kms_frontbuffer_tracking@fbcpsrdrrs-2p-rte +kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render +kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt +kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-render +kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt +kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-render +kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-render +kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt +kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-render +kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-blt +kms_frontbuffer_tracking@drrs-1p-offscren-pri-shrfb-draw-render +kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-indfb-draw-render +kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbcdrrs-1p-offscren-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-blt +kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-indfb-draw-render +kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-blt +kms_frontbuffer_tracking@psrdrrs-1p-offscren-pri-shrfb-draw-render +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-indfb-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-offscren-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-indfb-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-pri-shrfb-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-draw-render +kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt +kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-plflip-blt +kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt +kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt +kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt +kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt +kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt +kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt +kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@psr-2p-primscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt +kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt +kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt +kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt +kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-msflip-blt +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-plflip-blt +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-msflip-blt +kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-plflip-blt +kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@drrs-1p-primscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-msflip-blt +kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-plflip-blt +kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-msflip-blt +kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-plflip-blt +kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-plflip-blt +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-msflip-blt +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-plflip-blt +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-msflip-blt +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-plflip-blt +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-indfb-msflip-blt +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-indfb-plflip-blt +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-indfb-msflip-blt +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-indfb-plflip-blt +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-indfb-msflip-blt +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-indfb-plflip-blt +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-indfb-msflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-indfb-plflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-indfb-msflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-indfb-plflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-indfb-pgflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-indfb-msflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-indfb-plflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-shrfb-pgflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-shrfb-msflip-blt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-shrfb-plflip-blt +kms_frontbuffer_tracking@fbc-1p-indfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-1p-indfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-1p-shrfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-2p-indfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-2p-shrfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-indfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-1p-shrfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-indfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-2p-shrfb-fliptrack-mmap-gtt +kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move +kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff +kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move +kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff +kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move +kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff +kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move +kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff +kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-move +kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff +kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-move +kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff +kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move +kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff +kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move +kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff +kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move +kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff +kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move +kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff +kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-move +kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-onoff +kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-move +kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-onoff +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-onoff +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-move +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-onoff +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-move +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff +kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-move +kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-onoff +kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-move +kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff +kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-move +kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff +kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-move +kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-onoff +kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-move +kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff +kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-move +kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-onoff +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-move +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-onoff +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-move +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-move +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-onoff +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-move +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-onoff +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-move +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-onoff +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-move +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-onoff +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-move +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-cur-indfb-onoff +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-move +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-onoff +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-move +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-cur-indfb-onoff +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-move +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-onoff +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-move +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-cur-indfb-onoff +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-move +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-onoff +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-move +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-cur-indfb-onoff +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-move +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-onoff +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-move +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-cur-indfb-onoff +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-move +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-onoff +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-move +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-cur-indfb-onoff +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-move +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-onoff +kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@psrdrrs-1p-primscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@psrdrrs-2p-primscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@psrdrrs-2p-scndscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@fbcpsrdrrs-1p-primscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@fbcpsrdrrs-2p-primscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@fbcpsrdrrs-2p-scndscrn-spr-indfb-fullscreen +kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw +kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw +kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw +kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw +kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw +kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw +kms_frontbuffer_tracking@drrs-1p-pri-indfb-multidraw +kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw +kms_frontbuffer_tracking@fbcdrrs-1p-pri-indfb-multidraw +kms_frontbuffer_tracking@fbcdrrs-2p-pri-indfb-multidraw +kms_frontbuffer_tracking@psrdrrs-1p-pri-indfb-multidraw +kms_frontbuffer_tracking@psrdrrs-2p-pri-indfb-multidraw +kms_frontbuffer_tracking@fbcpsrdrrs-1p-pri-indfb-multidraw +kms_frontbuffer_tracking@fbcpsrdrrs-2p-pri-indfb-multidraw +kms_frontbuffer_tracking@fbc-farfromfence-mmap-gtt +kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-farfromfence-mmap-gtt +kms_frontbuffer_tracking@drrs-farfromfence-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-farfromfence-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-farfromfence-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-farfromfence-mmap-gtt +kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu +kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-gtt +kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-wc +kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc +kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite +kms_frontbuffer_tracking@fbc-rgb101010-draw-pwrite +kms_frontbuffer_tracking@fbc-rgb565-draw-blt +kms_frontbuffer_tracking@fbc-rgb101010-draw-blt +kms_frontbuffer_tracking@fbc-rgb565-draw-render +kms_frontbuffer_tracking@fbc-rgb101010-draw-render +kms_frontbuffer_tracking@psr-rgb565-draw-mmap-cpu +kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu +kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt +kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt +kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc +kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc +kms_frontbuffer_tracking@psr-rgb565-draw-pwrite +kms_frontbuffer_tracking@psr-rgb101010-draw-pwrite +kms_frontbuffer_tracking@psr-rgb565-draw-blt +kms_frontbuffer_tracking@psr-rgb101010-draw-blt +kms_frontbuffer_tracking@psr-rgb565-draw-render +kms_frontbuffer_tracking@psr-rgb101010-draw-render +kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsr-rgb565-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite +kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt +kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt +kms_frontbuffer_tracking@fbcpsr-rgb565-draw-render +kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render +kms_frontbuffer_tracking@drrs-rgb565-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-cpu +kms_frontbuffer_tracking@drrs-rgb565-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-gtt +kms_frontbuffer_tracking@drrs-rgb565-draw-mmap-wc +kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc +kms_frontbuffer_tracking@drrs-rgb565-draw-pwrite +kms_frontbuffer_tracking@drrs-rgb101010-draw-pwrite +kms_frontbuffer_tracking@drrs-rgb565-draw-blt +kms_frontbuffer_tracking@drrs-rgb101010-draw-blt +kms_frontbuffer_tracking@drrs-rgb565-draw-render +kms_frontbuffer_tracking@drrs-rgb101010-draw-render +kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-cpu +kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-gtt +kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc +kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-pwrite +kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-blt +kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-blt +kms_frontbuffer_tracking@fbcdrrs-rgb565-draw-render +kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-render +kms_frontbuffer_tracking@psrdrrs-rgb565-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-mmap-cpu +kms_frontbuffer_tracking@psrdrrs-rgb565-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-mmap-gtt +kms_frontbuffer_tracking@psrdrrs-rgb565-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-mmap-wc +kms_frontbuffer_tracking@psrdrrs-rgb565-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-pwrite +kms_frontbuffer_tracking@psrdrrs-rgb565-draw-blt +kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-blt +kms_frontbuffer_tracking@psrdrrs-rgb565-draw-render +kms_frontbuffer_tracking@psrdrrs-rgb101010-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-mmap-cpu +kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-mmap-gtt +kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-mmap-wc +kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-pwrite +kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-blt +kms_frontbuffer_tracking@fbcpsrdrrs-rgb565-draw-render +kms_frontbuffer_tracking@fbcpsrdrrs-rgb101010-draw-render +kms_frontbuffer_tracking@fbc-indfb-scaledprimary +kms_frontbuffer_tracking@fbc-shrfb-scaledprimary +kms_frontbuffer_tracking@psr-indfb-scaledprimary +kms_frontbuffer_tracking@psr-shrfb-scaledprimary +kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary +kms_frontbuffer_tracking@fbcpsr-shrfb-scaledprimary +kms_frontbuffer_tracking@drrs-indfb-scaledprimary +kms_frontbuffer_tracking@drrs-shrfb-scaledprimary +kms_frontbuffer_tracking@fbcdrrs-indfb-scaledprimary +kms_frontbuffer_tracking@fbcdrrs-shrfb-scaledprimary +kms_frontbuffer_tracking@psrdrrs-indfb-scaledprimary +kms_frontbuffer_tracking@psrdrrs-shrfb-scaledprimary +kms_frontbuffer_tracking@fbcpsrdrrs-indfb-scaledprimary +kms_frontbuffer_tracking@fbcpsrdrrs-shrfb-scaledprimary +kms_frontbuffer_tracking@fbc-modesetfrombusy +kms_frontbuffer_tracking@fbc-badstride +kms_frontbuffer_tracking@fbc-stridechange +kms_frontbuffer_tracking@fbc-tiling-linear +kms_frontbuffer_tracking@fbc-tiling-y +kms_frontbuffer_tracking@fbc-tiling-4 +kms_frontbuffer_tracking@fbc-suspend +kms_frontbuffer_tracking@psr-modesetfrombusy +kms_frontbuffer_tracking@psr-slowdraw +kms_frontbuffer_tracking@psr-suspend +kms_frontbuffer_tracking@fbcpsr-modesetfrombusy +kms_frontbuffer_tracking@fbcpsr-badstride +kms_frontbuffer_tracking@fbcpsr-stridechange +kms_frontbuffer_tracking@fbcpsr-tiling-linear +kms_frontbuffer_tracking@fbcpsr-tiling-y +kms_frontbuffer_tracking@fbcpsr-tiling-4 +kms_frontbuffer_tracking@fbcpsr-slowdraw +kms_frontbuffer_tracking@fbcpsr-suspend +kms_frontbuffer_tracking@drrs-modesetfrombusy +kms_frontbuffer_tracking@drrs-slowdraw +kms_frontbuffer_tracking@drrs-suspend +kms_frontbuffer_tracking@fbcdrrs-modesetfrombusy +kms_frontbuffer_tracking@fbcdrrs-badstride +kms_frontbuffer_tracking@fbcdrrs-stridechange +kms_frontbuffer_tracking@fbcdrrs-tiling-linear +kms_frontbuffer_tracking@fbcdrrs-tiling-y +kms_frontbuffer_tracking@fbcdrrs-tiling-4 +kms_frontbuffer_tracking@fbcdrrs-slowdraw +kms_frontbuffer_tracking@fbcdrrs-suspend +kms_frontbuffer_tracking@psrdrrs-modesetfrombusy +kms_frontbuffer_tracking@psrdrrs-slowdraw +kms_frontbuffer_tracking@psrdrrs-suspend +kms_frontbuffer_tracking@fbcpsrdrrs-modesetfrombusy +kms_frontbuffer_tracking@fbcpsrdrrs-badstride +kms_frontbuffer_tracking@fbcpsrdrrs-stridechange +kms_frontbuffer_tracking@fbcpsrdrrs-tiling-linear +kms_frontbuffer_tracking@fbcpsrdrrs-tiling-y +kms_frontbuffer_tracking@fbcpsrdrrs-tiling-4 +kms_frontbuffer_tracking@fbcpsrdrrs-slowdraw +kms_frontbuffer_tracking@fbcpsrdrrs-suspend +kms_frontbuffer_tracking@basic +kms_getfb@getfb-handle-zero +kms_getfb@getfb-handle-valid +kms_getfb@getfb-handle-closed +kms_getfb@getfb-handle-not-fb +kms_getfb@getfb-addfb-different-handles +kms_getfb@getfb-repeated-different-handles +kms_getfb@getfb-reject-ccs +kms_getfb@getfb2-handle-zero +kms_getfb@getfb2-handle-closed +kms_getfb@getfb2-handle-not-fb +kms_getfb@getfb2-accept-ccs +kms_getfb@getfb2-into-addfb2 +kms_getfb@getfb-handle-protection +kms_getfb@getfb2-handle-protection +kms_hdmi_inject@inject-4k +kms_hdmi_inject@inject-audio +kms_hdr@bpc-switch +kms_hdr@bpc-switch-dpms +kms_hdr@bpc-switch-suspend +kms_hdr@static-toggle +kms_hdr@static-toggle-dpms +kms_hdr@static-toggle-suspend +kms_hdr@static-swap +kms_hdr@invalid-metadata-sizes +kms_hdr@invalid-hdr +kms_invalid_mode@clock-too-high +kms_invalid_mode@zero-clock +kms_invalid_mode@int-max-clock +kms_invalid_mode@uint-max-clock +kms_invalid_mode@zero-hdisplay +kms_invalid_mode@zero-vdisplay +kms_invalid_mode@bad-hsync-start +kms_invalid_mode@bad-vsync-start +kms_invalid_mode@bad-hsync-end +kms_invalid_mode@bad-vsync-end +kms_invalid_mode@bad-htotal +kms_invalid_mode@bad-vtotal +kms_legacy_colorkey@basic +kms_legacy_colorkey@invalid-plane +kms_multipipe_modeset@basic-max-pipe-crc-check +kms_panel_fitting@legacy +kms_panel_fitting@atomic-fastset +kms_pipe_b_c_ivb@pipe-B-dpms-off-modeset-pipe-C +kms_pipe_b_c_ivb@pipe-B-double-modeset-then-modeset-pipe-C +kms_pipe_b_c_ivb@disable-pipe-B-enable-pipe-C +kms_pipe_b_c_ivb@from-pipe-C-to-B-with-3-lanes +kms_pipe_b_c_ivb@enable-pipe-C-while-B-has-3-lanes +kms_pipe_crc_basic@bad-source +kms_pipe_crc_basic@read-crc +kms_pipe_crc_basic@read-crc-frame-sequence +kms_pipe_crc_basic@nonblocking-crc +kms_pipe_crc_basic@nonblocking-crc-frame-sequence +kms_pipe_crc_basic@suspend-read-crc +kms_pipe_crc_basic@hang-read-crc +kms_pipe_crc_basic@disable-crc-after-crtc +kms_pipe_crc_basic@compare-crc-sanitycheck-xr24 +kms_pipe_crc_basic@compare-crc-sanitycheck-nv12 +kms_plane@pixel-format +kms_plane@pixel-format-source-clamping +kms_plane@plane-position-covered +kms_plane@plane-position-hole +kms_plane@plane-position-hole-dpms +kms_plane@plane-panning-top-left +kms_plane@plane-panning-bottom-right +kms_plane@plane-panning-bottom-right-suspend +kms_plane@invalid-pixel-format-settings +kms_plane_alpha_blend@alpha-basic +kms_plane_alpha_blend@alpha-7efc +kms_plane_alpha_blend@coverage-7efc +kms_plane_alpha_blend@coverage-vs-premult-vs-constant +kms_plane_alpha_blend@alpha-transparent-fb +kms_plane_alpha_blend@alpha-opaque-fb +kms_plane_alpha_blend@constant-alpha-min +kms_plane_alpha_blend@constant-alpha-mid +kms_plane_alpha_blend@constant-alpha-max +kms_plane_cursor@primary +kms_plane_cursor@overlay +kms_plane_cursor@viewport +kms_plane_lowres@tiling-none +kms_plane_lowres@tiling-x +kms_plane_lowres@tiling-y +kms_plane_lowres@tiling-yf +kms_plane_lowres@tiling-4 +kms_plane_multiple@tiling-none +kms_plane_multiple@tiling-x +kms_plane_multiple@tiling-y +kms_plane_multiple@tiling-yf +kms_plane_multiple@tiling-4 +kms_plane_scaling@plane-upscale-with-pixel-format-20x20 +kms_plane_scaling@plane-upscale-with-pixel-format-factor-0-25 +kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25 +kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5 +kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75 +kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling +kms_plane_scaling@plane-upscale-with-rotation-20x20 +kms_plane_scaling@plane-upscale-with-rotation-factor-0-25 +kms_plane_scaling@plane-downscale-with-rotation-factor-0-25 +kms_plane_scaling@plane-downscale-with-rotation-factor-0-5 +kms_plane_scaling@plane-downscale-with-rotation-factor-0-75 +kms_plane_scaling@plane-scaler-with-rotation-unity-scaling +kms_plane_scaling@plane-upscale-with-modifiers-20x20 +kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25 +kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25 +kms_plane_scaling@plane-downscale-with-modifiers-factor-0-5 +kms_plane_scaling@plane-downscale-with-modifiers-factor-0-75 +kms_plane_scaling@plane-scaler-with-modifiers-unity-scaling +kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats +kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation +kms_plane_scaling@plane-scaler-with-clipping-clamping-modifiers +kms_plane_scaling@planes-upscale-20x20 +kms_plane_scaling@planes-upscale-factor-0-25 +kms_plane_scaling@planes-scaler-unity-scaling +kms_plane_scaling@planes-downscale-factor-0-25 +kms_plane_scaling@planes-downscale-factor-0-5 +kms_plane_scaling@planes-downscale-factor-0-75 +kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25 +kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5 +kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75 +kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25 +kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5 +kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75 +kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25 +kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5 +kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75 +kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20 +kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25 +kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling +kms_plane_scaling@planes-downscale-factor-0-5-upscale-20x20 +kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25 +kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling +kms_plane_scaling@planes-downscale-factor-0-75-upscale-20x20 +kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25 +kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling +kms_plane_scaling@intel-max-src-size +kms_plane_scaling@invalid-num-scalers +kms_plane_scaling@invalid-parameters +kms_plane_scaling@2x-scaler-multi-pipe +kms_prime@basic-crc-hybrid +kms_prime@basic-modeset-hybrid +kms_prime@D3hot +kms_prime@basic-crc-vgem +kms_prop_blob@basic +kms_prop_blob@blob-prop-core +kms_prop_blob@blob-prop-validate +kms_prop_blob@blob-prop-lifetime +kms_prop_blob@blob-multiple +kms_prop_blob@invalid-get-prop-any +kms_prop_blob@invalid-get-prop +kms_prop_blob@invalid-set-prop-any +kms_prop_blob@invalid-set-prop +kms_properties@plane-properties-legacy +kms_properties@plane-properties-atomic +kms_properties@crtc-properties-legacy +kms_properties@crtc-properties-atomic +kms_properties@connector-properties-legacy +kms_properties@connector-properties-atomic +kms_properties@invalid-properties-legacy +kms_properties@invalid-properties-atomic +kms_properties@get_properties-sanity-atomic +kms_properties@get_properties-sanity-non-atomic +kms_psr@basic +kms_psr@no_drrs +kms_psr@primary_page_flip +kms_psr@primary_mmap_gtt +kms_psr@primary_mmap_cpu +kms_psr@primary_blt +kms_psr@primary_render +kms_psr@sprite_mmap_gtt +kms_psr@cursor_mmap_gtt +kms_psr@sprite_mmap_cpu +kms_psr@cursor_mmap_cpu +kms_psr@sprite_blt +kms_psr@cursor_blt +kms_psr@sprite_render +kms_psr@cursor_render +kms_psr@sprite_plane_move +kms_psr@cursor_plane_move +kms_psr@sprite_plane_onoff +kms_psr@cursor_plane_onoff +kms_psr@dpms +kms_psr@suspend +kms_psr@psr2_basic +kms_psr@psr2_no_drrs +kms_psr@psr2_primary_page_flip +kms_psr@psr2_primary_mmap_gtt +kms_psr@psr2_primary_mmap_cpu +kms_psr@psr2_primary_blt +kms_psr@psr2_primary_render +kms_psr@psr2_sprite_mmap_gtt +kms_psr@psr2_cursor_mmap_gtt +kms_psr@psr2_sprite_mmap_cpu +kms_psr@psr2_cursor_mmap_cpu +kms_psr@psr2_sprite_blt +kms_psr@psr2_cursor_blt +kms_psr@psr2_sprite_render +kms_psr@psr2_cursor_render +kms_psr@psr2_sprite_plane_move +kms_psr@psr2_cursor_plane_move +kms_psr@psr2_sprite_plane_onoff +kms_psr@psr2_cursor_plane_onoff +kms_psr@psr2_dpms +kms_psr@psr2_suspend +kms_psr2_sf@primary-plane-update-sf-dmg-area +kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb +kms_psr2_sf@overlay-plane-update-sf-dmg-area +kms_psr2_sf@cursor-plane-update-sf +kms_psr2_sf@cursor-plane-move-continuous-sf +kms_psr2_sf@cursor-plane-move-continuous-exceed-sf +kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf +kms_psr2_sf@plane-move-sf-dmg-area +kms_psr2_sf@overlay-plane-move-continuous-sf +kms_psr2_sf@overlay-plane-move-continuous-exceed-sf +kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf +kms_psr2_sf@overlay-primary-update-sf-dmg-area +kms_psr2_sf@overlay-plane-update-continuous-sf +kms_psr2_su@page_flip-XRGB8888 +kms_psr2_su@page_flip-NV12 +kms_psr2_su@page_flip-P010 +kms_psr2_su@frontbuffer-XRGB8888 +kms_pwrite_crc +kms_rmfb@rmfb-ioctl +kms_rmfb@close-fd +kms_rotation_crc@primary-rotation-90 +kms_rotation_crc@primary-rotation-180 +kms_rotation_crc@primary-rotation-270 +kms_rotation_crc@sprite-rotation-90 +kms_rotation_crc@sprite-rotation-180 +kms_rotation_crc@sprite-rotation-270 +kms_rotation_crc@cursor-rotation-180 +kms_rotation_crc@sprite-rotation-90-pos-100-0 +kms_rotation_crc@bad-pixel-format +kms_rotation_crc@bad-tiling +kms_rotation_crc@primary-x-tiled-reflect-x-0 +kms_rotation_crc@primary-x-tiled-reflect-x-180 +kms_rotation_crc@primary-y-tiled-reflect-x-0 +kms_rotation_crc@primary-y-tiled-reflect-x-90 +kms_rotation_crc@primary-y-tiled-reflect-x-180 +kms_rotation_crc@primary-y-tiled-reflect-x-270 +kms_rotation_crc@primary-yf-tiled-reflect-x-0 +kms_rotation_crc@primary-yf-tiled-reflect-x-90 +kms_rotation_crc@primary-yf-tiled-reflect-x-180 +kms_rotation_crc@primary-yf-tiled-reflect-x-270 +kms_rotation_crc@primary-4-tiled-reflect-x-0 +kms_rotation_crc@primary-4-tiled-reflect-x-180 +kms_rotation_crc@multiplane-rotation +kms_rotation_crc@multiplane-rotation-cropping-top +kms_rotation_crc@multiplane-rotation-cropping-bottom +kms_rotation_crc@exhaust-fences +kms_scaling_modes@scaling-mode-full +kms_scaling_modes@scaling-mode-center +kms_scaling_modes@scaling-mode-full-aspect +kms_scaling_modes@scaling-mode-none +kms_selftest@drm_cmdline +kms_selftest@drm_damage +kms_selftest@drm_dp_mst +kms_selftest@drm_format_helper +kms_selftest@drm_format +kms_selftest@framebuffer +kms_selftest@drm_plane +kms_setmode@basic +kms_setmode@basic-clone-single-crtc +kms_setmode@invalid-clone-single-crtc +kms_setmode@invalid-clone-exclusive-crtc +kms_setmode@clone-exclusive-crtc +kms_setmode@invalid-clone-single-crtc-stealing +kms_sysfs_edid_timing +kms_tv_load_detect@load-detect +kms_universal_plane@universal-plane-pipe-A-functional +kms_universal_plane@universal-plane-pipe-A-sanity +kms_universal_plane@disable-primary-vs-flip-pipe-A +kms_universal_plane@cursor-fb-leak-pipe-A +kms_universal_plane@universal-plane-pageflip-windowed-pipe-A +kms_universal_plane@universal-plane-pipe-B-functional +kms_universal_plane@universal-plane-pipe-B-sanity +kms_universal_plane@disable-primary-vs-flip-pipe-B +kms_universal_plane@cursor-fb-leak-pipe-B +kms_universal_plane@universal-plane-pageflip-windowed-pipe-B +kms_universal_plane@universal-plane-pipe-C-functional +kms_universal_plane@universal-plane-pipe-C-sanity +kms_universal_plane@disable-primary-vs-flip-pipe-C +kms_universal_plane@cursor-fb-leak-pipe-C +kms_universal_plane@universal-plane-pageflip-windowed-pipe-C +kms_universal_plane@universal-plane-pipe-D-functional +kms_universal_plane@universal-plane-pipe-D-sanity +kms_universal_plane@disable-primary-vs-flip-pipe-D +kms_universal_plane@cursor-fb-leak-pipe-D +kms_universal_plane@universal-plane-pageflip-windowed-pipe-D +kms_universal_plane@universal-plane-pipe-E-functional +kms_universal_plane@universal-plane-pipe-E-sanity +kms_universal_plane@disable-primary-vs-flip-pipe-E +kms_universal_plane@cursor-fb-leak-pipe-E +kms_universal_plane@universal-plane-pageflip-windowed-pipe-E +kms_universal_plane@universal-plane-pipe-F-functional +kms_universal_plane@universal-plane-pipe-F-sanity +kms_universal_plane@disable-primary-vs-flip-pipe-F +kms_universal_plane@cursor-fb-leak-pipe-F +kms_universal_plane@universal-plane-pageflip-windowed-pipe-F +kms_universal_plane@universal-plane-pipe-G-functional +kms_universal_plane@universal-plane-pipe-G-sanity +kms_universal_plane@disable-primary-vs-flip-pipe-G +kms_universal_plane@cursor-fb-leak-pipe-G +kms_universal_plane@universal-plane-pageflip-windowed-pipe-G +kms_universal_plane@universal-plane-pipe-H-functional +kms_universal_plane@universal-plane-pipe-H-sanity +kms_universal_plane@disable-primary-vs-flip-pipe-H +kms_universal_plane@cursor-fb-leak-pipe-H +kms_universal_plane@universal-plane-pageflip-windowed-pipe-H +kms_vblank@invalid +kms_vblank@crtc-id +kms_vblank@pipe-A-accuracy-idle +kms_vblank@pipe-A-query-idle +kms_vblank@pipe-A-query-idle-hang +kms_vblank@pipe-A-query-forked +kms_vblank@pipe-A-query-forked-hang +kms_vblank@pipe-A-query-busy +kms_vblank@pipe-A-query-busy-hang +kms_vblank@pipe-A-query-forked-busy +kms_vblank@pipe-A-query-forked-busy-hang +kms_vblank@pipe-A-wait-idle +kms_vblank@pipe-A-wait-idle-hang +kms_vblank@pipe-A-wait-forked +kms_vblank@pipe-A-wait-forked-hang +kms_vblank@pipe-A-wait-busy +kms_vblank@pipe-A-wait-busy-hang +kms_vblank@pipe-A-wait-forked-busy +kms_vblank@pipe-A-wait-forked-busy-hang +kms_vblank@pipe-A-ts-continuation-idle +kms_vblank@pipe-A-ts-continuation-idle-hang +kms_vblank@pipe-A-ts-continuation-dpms-rpm +kms_vblank@pipe-A-ts-continuation-dpms-suspend +kms_vblank@pipe-A-ts-continuation-suspend +kms_vblank@pipe-A-ts-continuation-modeset +kms_vblank@pipe-A-ts-continuation-modeset-hang +kms_vblank@pipe-A-ts-continuation-modeset-rpm +kms_vblank@pipe-B-accuracy-idle +kms_vblank@pipe-B-query-idle +kms_vblank@pipe-B-query-idle-hang +kms_vblank@pipe-B-query-forked +kms_vblank@pipe-B-query-forked-hang +kms_vblank@pipe-B-query-busy +kms_vblank@pipe-B-query-busy-hang +kms_vblank@pipe-B-query-forked-busy +kms_vblank@pipe-B-query-forked-busy-hang +kms_vblank@pipe-B-wait-idle +kms_vblank@pipe-B-wait-idle-hang +kms_vblank@pipe-B-wait-forked +kms_vblank@pipe-B-wait-forked-hang +kms_vblank@pipe-B-wait-busy +kms_vblank@pipe-B-wait-busy-hang +kms_vblank@pipe-B-wait-forked-busy +kms_vblank@pipe-B-wait-forked-busy-hang +kms_vblank@pipe-B-ts-continuation-idle +kms_vblank@pipe-B-ts-continuation-idle-hang +kms_vblank@pipe-B-ts-continuation-dpms-rpm +kms_vblank@pipe-B-ts-continuation-dpms-suspend +kms_vblank@pipe-B-ts-continuation-suspend +kms_vblank@pipe-B-ts-continuation-modeset +kms_vblank@pipe-B-ts-continuation-modeset-hang +kms_vblank@pipe-B-ts-continuation-modeset-rpm +kms_vblank@pipe-C-accuracy-idle +kms_vblank@pipe-C-query-idle +kms_vblank@pipe-C-query-idle-hang +kms_vblank@pipe-C-query-forked +kms_vblank@pipe-C-query-forked-hang +kms_vblank@pipe-C-query-busy +kms_vblank@pipe-C-query-busy-hang +kms_vblank@pipe-C-query-forked-busy +kms_vblank@pipe-C-query-forked-busy-hang +kms_vblank@pipe-C-wait-idle +kms_vblank@pipe-C-wait-idle-hang +kms_vblank@pipe-C-wait-forked +kms_vblank@pipe-C-wait-forked-hang +kms_vblank@pipe-C-wait-busy +kms_vblank@pipe-C-wait-busy-hang +kms_vblank@pipe-C-wait-forked-busy +kms_vblank@pipe-C-wait-forked-busy-hang +kms_vblank@pipe-C-ts-continuation-idle +kms_vblank@pipe-C-ts-continuation-idle-hang +kms_vblank@pipe-C-ts-continuation-dpms-rpm +kms_vblank@pipe-C-ts-continuation-dpms-suspend +kms_vblank@pipe-C-ts-continuation-suspend +kms_vblank@pipe-C-ts-continuation-modeset +kms_vblank@pipe-C-ts-continuation-modeset-hang +kms_vblank@pipe-C-ts-continuation-modeset-rpm +kms_vblank@pipe-D-accuracy-idle +kms_vblank@pipe-D-query-idle +kms_vblank@pipe-D-query-idle-hang +kms_vblank@pipe-D-query-forked +kms_vblank@pipe-D-query-forked-hang +kms_vblank@pipe-D-query-busy +kms_vblank@pipe-D-query-busy-hang +kms_vblank@pipe-D-query-forked-busy +kms_vblank@pipe-D-query-forked-busy-hang +kms_vblank@pipe-D-wait-idle +kms_vblank@pipe-D-wait-idle-hang +kms_vblank@pipe-D-wait-forked +kms_vblank@pipe-D-wait-forked-hang +kms_vblank@pipe-D-wait-busy +kms_vblank@pipe-D-wait-busy-hang +kms_vblank@pipe-D-wait-forked-busy +kms_vblank@pipe-D-wait-forked-busy-hang +kms_vblank@pipe-D-ts-continuation-idle +kms_vblank@pipe-D-ts-continuation-idle-hang +kms_vblank@pipe-D-ts-continuation-dpms-rpm +kms_vblank@pipe-D-ts-continuation-dpms-suspend +kms_vblank@pipe-D-ts-continuation-suspend +kms_vblank@pipe-D-ts-continuation-modeset +kms_vblank@pipe-D-ts-continuation-modeset-hang +kms_vblank@pipe-D-ts-continuation-modeset-rpm +kms_vblank@pipe-E-accuracy-idle +kms_vblank@pipe-E-query-idle +kms_vblank@pipe-E-query-idle-hang +kms_vblank@pipe-E-query-forked +kms_vblank@pipe-E-query-forked-hang +kms_vblank@pipe-E-query-busy +kms_vblank@pipe-E-query-busy-hang +kms_vblank@pipe-E-query-forked-busy +kms_vblank@pipe-E-query-forked-busy-hang +kms_vblank@pipe-E-wait-idle +kms_vblank@pipe-E-wait-idle-hang +kms_vblank@pipe-E-wait-forked +kms_vblank@pipe-E-wait-forked-hang +kms_vblank@pipe-E-wait-busy +kms_vblank@pipe-E-wait-busy-hang +kms_vblank@pipe-E-wait-forked-busy +kms_vblank@pipe-E-wait-forked-busy-hang +kms_vblank@pipe-E-ts-continuation-idle +kms_vblank@pipe-E-ts-continuation-idle-hang +kms_vblank@pipe-E-ts-continuation-dpms-rpm +kms_vblank@pipe-E-ts-continuation-dpms-suspend +kms_vblank@pipe-E-ts-continuation-suspend +kms_vblank@pipe-E-ts-continuation-modeset +kms_vblank@pipe-E-ts-continuation-modeset-hang +kms_vblank@pipe-E-ts-continuation-modeset-rpm +kms_vblank@pipe-F-accuracy-idle +kms_vblank@pipe-F-query-idle +kms_vblank@pipe-F-query-idle-hang +kms_vblank@pipe-F-query-forked +kms_vblank@pipe-F-query-forked-hang +kms_vblank@pipe-F-query-busy +kms_vblank@pipe-F-query-busy-hang +kms_vblank@pipe-F-query-forked-busy +kms_vblank@pipe-F-query-forked-busy-hang +kms_vblank@pipe-F-wait-idle +kms_vblank@pipe-F-wait-idle-hang +kms_vblank@pipe-F-wait-forked +kms_vblank@pipe-F-wait-forked-hang +kms_vblank@pipe-F-wait-busy +kms_vblank@pipe-F-wait-busy-hang +kms_vblank@pipe-F-wait-forked-busy +kms_vblank@pipe-F-wait-forked-busy-hang +kms_vblank@pipe-F-ts-continuation-idle +kms_vblank@pipe-F-ts-continuation-idle-hang +kms_vblank@pipe-F-ts-continuation-dpms-rpm +kms_vblank@pipe-F-ts-continuation-dpms-suspend +kms_vblank@pipe-F-ts-continuation-suspend +kms_vblank@pipe-F-ts-continuation-modeset +kms_vblank@pipe-F-ts-continuation-modeset-hang +kms_vblank@pipe-F-ts-continuation-modeset-rpm +kms_vblank@pipe-G-accuracy-idle +kms_vblank@pipe-G-query-idle +kms_vblank@pipe-G-query-idle-hang +kms_vblank@pipe-G-query-forked +kms_vblank@pipe-G-query-forked-hang +kms_vblank@pipe-G-query-busy +kms_vblank@pipe-G-query-busy-hang +kms_vblank@pipe-G-query-forked-busy +kms_vblank@pipe-G-query-forked-busy-hang +kms_vblank@pipe-G-wait-idle +kms_vblank@pipe-G-wait-idle-hang +kms_vblank@pipe-G-wait-forked +kms_vblank@pipe-G-wait-forked-hang +kms_vblank@pipe-G-wait-busy +kms_vblank@pipe-G-wait-busy-hang +kms_vblank@pipe-G-wait-forked-busy +kms_vblank@pipe-G-wait-forked-busy-hang +kms_vblank@pipe-G-ts-continuation-idle +kms_vblank@pipe-G-ts-continuation-idle-hang +kms_vblank@pipe-G-ts-continuation-dpms-rpm +kms_vblank@pipe-G-ts-continuation-dpms-suspend +kms_vblank@pipe-G-ts-continuation-suspend +kms_vblank@pipe-G-ts-continuation-modeset +kms_vblank@pipe-G-ts-continuation-modeset-hang +kms_vblank@pipe-G-ts-continuation-modeset-rpm +kms_vblank@pipe-H-accuracy-idle +kms_vblank@pipe-H-query-idle +kms_vblank@pipe-H-query-idle-hang +kms_vblank@pipe-H-query-forked +kms_vblank@pipe-H-query-forked-hang +kms_vblank@pipe-H-query-busy +kms_vblank@pipe-H-query-busy-hang +kms_vblank@pipe-H-query-forked-busy +kms_vblank@pipe-H-query-forked-busy-hang +kms_vblank@pipe-H-wait-idle +kms_vblank@pipe-H-wait-idle-hang +kms_vblank@pipe-H-wait-forked +kms_vblank@pipe-H-wait-forked-hang +kms_vblank@pipe-H-wait-busy +kms_vblank@pipe-H-wait-busy-hang +kms_vblank@pipe-H-wait-forked-busy +kms_vblank@pipe-H-wait-forked-busy-hang +kms_vblank@pipe-H-ts-continuation-idle +kms_vblank@pipe-H-ts-continuation-idle-hang +kms_vblank@pipe-H-ts-continuation-dpms-rpm +kms_vblank@pipe-H-ts-continuation-dpms-suspend +kms_vblank@pipe-H-ts-continuation-suspend +kms_vblank@pipe-H-ts-continuation-modeset +kms_vblank@pipe-H-ts-continuation-modeset-hang +kms_vblank@pipe-H-ts-continuation-modeset-rpm +kms_vrr@flip-basic +kms_vrr@flip-dpms +kms_vrr@flip-suspend +kms_vrr@flipline +kms_vrr@negative-basic +kms_writeback@writeback-pixel-formats +kms_writeback@writeback-invalid-parameters +kms_writeback@writeback-fb-id +kms_writeback@writeback-check-output +prime_mmap_kms@buffer-sharing diff --git a/drivers/gpu/drm/ci/x86_64.config b/drivers/gpu/drm/ci/x86_64.config new file mode 100644 index 000000000000..1cbd49a5b23a --- /dev/null +++ b/drivers/gpu/drm/ci/x86_64.config @@ -0,0 +1,111 @@ +CONFIG_LOCALVERSION_AUTO=y +CONFIG_DEBUG_KERNEL=y + +CONFIG_CRYPTO_ZSTD=y +CONFIG_ZRAM_MEMORY_TRACKING=y +CONFIG_ZRAM_WRITEBACK=y +CONFIG_ZRAM=y +CONFIG_ZSMALLOC_STAT=y + +CONFIG_PWM=y +CONFIG_PM_DEVFREQ=y +CONFIG_OF=y +CONFIG_CROS_EC=y + +# abootimg with a 'dummy' rootfs fails with root=/dev/nfs +CONFIG_BLK_DEV_INITRD=n + +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_DEVFREQ_GOV_PASSIVE=y + +CONFIG_DRM=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_PWM_CROS_EC=y +CONFIG_BACKLIGHT_PWM=y + +# Strip out some stuff we don't need for graphics testing, to reduce +# the build. +CONFIG_CAN=n +CONFIG_WIRELESS=n +CONFIG_RFKILL=n +CONFIG_WLAN=n + +CONFIG_REGULATOR_FAN53555=y +CONFIG_REGULATOR=y + +CONFIG_REGULATOR_VCTRL=y + +CONFIG_KASAN=n +CONFIG_KASAN_INLINE=n +CONFIG_STACKTRACE=n + +CONFIG_TMPFS=y + +CONFIG_PROVE_LOCKING=n +CONFIG_DEBUG_LOCKDEP=n +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y + +CONFIG_DETECT_HUNG_TASK=y + +CONFIG_USB_USBNET=y +CONFIG_NETDEVICES=y +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_RTL8152=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_ETH=y + +CONFIG_FW_LOADER_COMPRESS=y + +# options for AMD devices +CONFIG_X86_AMD_PLATFORM_DEVICE=y +CONFIG_ACPI_VIDEO=y +CONFIG_X86_AMD_FREQ_SENSITIVITY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AMD=y +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_USERPTR=y +CONFIG_DRM_AMD_ACP=n +CONFIG_ACPI_WMI=y +CONFIG_MXM_WMI=y +CONFIG_PARPORT=y +CONFIG_PARPORT_PC=y +CONFIG_PARPORT_SERIAL=y +CONFIG_SERIAL_8250_DW=y +CONFIG_CHROME_PLATFORMS=y +CONFIG_KVM_AMD=m + +#options for Intel devices +CONFIG_MFD_INTEL_LPSS_PCI=y +CONFIG_KVM_INTEL=m + +#options for KVM guests +CONFIG_FUSE_FS=y +CONFIG_HYPERVISOR_GUEST=y +CONFIG_KVM=y +CONFIG_KVM_GUEST=y +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRTIO_FS=y +CONFIG_DRM_VIRTIO_GPU=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_VIRTIO_NET=y +CONFIG_VIRTIO_CONSOLE=y +CONFIG_PARAVIRT=y +CONFIG_VIRTIO_BLK=y +CONFIG_VIRTUALIZATION=y +CONFIG_VIRTIO=y +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_CRYPTO_DEV_VIRTIO=y +CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_BLK_MQ_VIRTIO=y +CONFIG_TUN=y +CONFIG_VSOCKETS=y +CONFIG_VIRTIO_VSOCKETS=y +CONFIG_VHOST_VSOCK=m diff --git a/drivers/gpu/drm/ci/xfails/amdgpu-stoney-fails.txt b/drivers/gpu/drm/ci/xfails/amdgpu-stoney-fails.txt new file mode 100644 index 000000000000..bd9392536e7c --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/amdgpu-stoney-fails.txt @@ -0,0 +1,19 @@ +kms_addfb_basic@bad-pitch-65536,Fail +kms_addfb_basic@bo-too-small,Fail +kms_async_flips@invalid-async-flip,Fail +kms_atomic@plane-immutable-zpos,Fail +kms_atomic_transition@plane-toggle-modeset-transition,Fail +kms_bw@linear-tiling-1-displays-2560x1440p,Fail +kms_bw@linear-tiling-1-displays-3840x2160p,Fail +kms_bw@linear-tiling-2-displays-3840x2160p,Fail +kms_bw@linear-tiling-3-displays-1920x1080p,Fail +kms_color@degamma,Fail +kms_cursor_crc@cursor-size-change,Fail +kms_cursor_crc@pipe-A-cursor-size-change,Fail +kms_cursor_crc@pipe-B-cursor-size-change,Fail +kms_cursor_legacy@forked-move,Fail +kms_hdr@bpc-switch,Fail +kms_hdr@bpc-switch-dpms,Fail +kms_plane_multiple@atomic-pipe-A-tiling-none,Fail +kms_rmfb@close-fd,Fail +kms_rotation_crc@primary-rotation-180,Fail diff --git a/drivers/gpu/drm/ci/xfails/amdgpu-stoney-flakes.txt b/drivers/gpu/drm/ci/xfails/amdgpu-stoney-flakes.txt new file mode 100644 index 000000000000..f8defa0f9e67 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/amdgpu-stoney-flakes.txt @@ -0,0 +1,21 @@ +kms_addfb_basic@too-high +kms_async_flips@alternate-sync-async-flip +kms_async_flips@async-flip-with-page-flip-events +kms_async_flips@crc +kms_async_flips@test-cursor +kms_async_flips@test-time-stamp +kms_atomic_transition@plane-all-modeset-transition-internal-panels +kms_atomic_transition@plane-all-transition +kms_atomic_transition@plane-use-after-nonblocking-unbind +kms_bw@linear-tiling-1-displays-1920x1080p +kms_bw@linear-tiling-2-displays-1920x1080p +kms_bw@linear-tiling-2-displays-2560x1440p +kms_bw@linear-tiling-3-displays-2560x1440p +kms_bw@linear-tiling-3-displays-3840x2160p +kms_cursor_crc@pipe-A-cursor-alpha-opaque +kms_cursor_crc@pipe-B-cursor-alpha-opaque +kms_plane@pixel-format +kms_plane_multiple@atomic-pipe-B-tiling-none +kms_plane_scaling@downscale-with-rotation-factor-0-5 +kms_universal_plane@disable-primary-vs-flip-pipe-A +kms_universal_plane@disable-primary-vs-flip-pipe-B diff --git a/drivers/gpu/drm/ci/xfails/amdgpu-stoney-skips.txt b/drivers/gpu/drm/ci/xfails/amdgpu-stoney-skips.txt new file mode 100644 index 000000000000..e2c538a0f954 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/amdgpu-stoney-skips.txt @@ -0,0 +1,2 @@ +# Suspend to RAM seems to be broken on this machine +.*suspend.*
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/xfails/i915-amly-fails.txt b/drivers/gpu/drm/ci/xfails/i915-amly-fails.txt new file mode 100644 index 000000000000..5f513c638beb --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-amly-fails.txt @@ -0,0 +1,17 @@ +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail +kms_plane_alpha_blend@alpha-basic,Fail +kms_plane_alpha_blend@alpha-opaque-fb,Fail +kms_plane_alpha_blend@alpha-transparent-fb,Fail +kms_plane_alpha_blend@constant-alpha-max,Fail diff --git a/drivers/gpu/drm/ci/xfails/i915-amly-flakes.txt b/drivers/gpu/drm/ci/xfails/i915-amly-flakes.txt new file mode 100644 index 000000000000..d5000515a315 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-amly-flakes.txt @@ -0,0 +1,32 @@ +kms_bw@linear-tiling-2-displays-1920x1080p +kms_bw@linear-tiling-2-displays-2560x1440p +kms_bw@linear-tiling-2-displays-3840x2160p +kms_bw@linear-tiling-3-displays-1920x1080p +kms_bw@linear-tiling-3-displays-2560x1440p +kms_bw@linear-tiling-3-displays-3840x2160p +kms_bw@linear-tiling-4-displays-1920x1080p +kms_bw@linear-tiling-4-displays-2560x1440p +kms_bw@linear-tiling-4-displays-3840x2160p +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling +kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling +kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling +kms_plane_alpha_blend@pipe-A-alpha-basic +kms_plane_alpha_blend@pipe-A-alpha-opaque-fb +kms_plane_alpha_blend@pipe-A-alpha-transparent-fb +kms_plane_alpha_blend@pipe-A-constant-alpha-max +kms_plane_alpha_blend@pipe-B-alpha-basic +kms_plane_alpha_blend@pipe-B-alpha-opaque-fb +kms_plane_alpha_blend@pipe-B-alpha-transparent-fb +kms_plane_alpha_blend@pipe-B-constant-alpha-max +kms_plane_alpha_blend@pipe-C-alpha-basic +kms_plane_alpha_blend@pipe-C-alpha-opaque-fb +kms_plane_alpha_blend@pipe-C-alpha-transparent-fb +kms_plane_alpha_blend@pipe-C-constant-alpha-max +kms_sysfs_edid_timing diff --git a/drivers/gpu/drm/ci/xfails/i915-amly-skips.txt b/drivers/gpu/drm/ci/xfails/i915-amly-skips.txt new file mode 100644 index 000000000000..fe55540a3f9a --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-amly-skips.txt @@ -0,0 +1,4 @@ +# Suspend to RAM seems to be broken on this machine +.*suspend.* +# This is generating kernel oops with divide error +kms_plane_scaling@invalid-parameters
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/xfails/i915-apl-fails.txt b/drivers/gpu/drm/ci/xfails/i915-apl-fails.txt new file mode 100644 index 000000000000..46397ce38d5a --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-apl-fails.txt @@ -0,0 +1,58 @@ +kms_3d,Timeout +kms_bw@linear-tiling-2-displays-1920x1080p,Fail +kms_bw@linear-tiling-2-displays-2560x1440p,Fail +kms_bw@linear-tiling-2-displays-3840x2160p,Fail +kms_bw@linear-tiling-3-displays-1920x1080p,Fail +kms_bw@linear-tiling-3-displays-2560x1440p,Fail +kms_bw@linear-tiling-3-displays-3840x2160p,Fail +kms_bw@linear-tiling-4-displays-1920x1080p,Fail +kms_bw@linear-tiling-4-displays-2560x1440p,Fail +kms_bw@linear-tiling-4-displays-3840x2160p,Fail +kms_color@ctm-0-25,Fail +kms_color@ctm-0-50,Fail +kms_color@ctm-0-75,Fail +kms_color@ctm-max,Fail +kms_color@ctm-negative,Fail +kms_color@ctm-red-to-blue,Fail +kms_color@ctm-signed,Fail +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail +kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling,Fail +kms_hdmi_inject@inject-4k,Timeout +kms_plane@plane-position-hole,Timeout +kms_plane_alpha_blend@alpha-basic,Fail +kms_plane_alpha_blend@alpha-opaque-fb,Fail +kms_plane_alpha_blend@alpha-transparent-fb,Fail +kms_plane_alpha_blend@constant-alpha-max,Fail +kms_plane_alpha_blend@pipe-A-alpha-opaque-fb,Fail +kms_plane_alpha_blend@pipe-A-alpha-transparent-fb,Fail +kms_plane_alpha_blend@pipe-A-constant-alpha-max,Fail +kms_plane_alpha_blend@pipe-B-alpha-opaque-fb,Fail +kms_plane_alpha_blend@pipe-B-alpha-transparent-fb,Fail +kms_plane_alpha_blend@pipe-B-constant-alpha-max,Fail +kms_plane_alpha_blend@pipe-C-alpha-opaque-fb,Fail +kms_plane_alpha_blend@pipe-C-alpha-transparent-fb,Fail +kms_plane_alpha_blend@pipe-C-constant-alpha-max,Fail +kms_plane_multiple@tiling-y,Timeout +kms_pwrite_crc,Timeout +kms_sysfs_edid_timing,Fail diff --git a/drivers/gpu/drm/ci/xfails/i915-apl-flakes.txt b/drivers/gpu/drm/ci/xfails/i915-apl-flakes.txt new file mode 100644 index 000000000000..331c5841bb41 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-apl-flakes.txt @@ -0,0 +1 @@ +kms_frontbuffer_tracking@fbc-tiling-linear diff --git a/drivers/gpu/drm/ci/xfails/i915-apl-skips.txt b/drivers/gpu/drm/ci/xfails/i915-apl-skips.txt new file mode 100644 index 000000000000..3430b215c06e --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-apl-skips.txt @@ -0,0 +1,6 @@ +# Suspend to RAM seems to be broken on this machine +.*suspend.* +# This is generating kernel oops with divide error +kms_plane_scaling@invalid-parameters +# This is cascading issues +kms_3d
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/xfails/i915-cml-fails.txt b/drivers/gpu/drm/ci/xfails/i915-cml-fails.txt new file mode 100644 index 000000000000..6139b410e767 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-cml-fails.txt @@ -0,0 +1,18 @@ +kms_color@ctm-0-25,Fail +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail +kms_plane_alpha_blend@alpha-basic,Fail +kms_plane_alpha_blend@alpha-opaque-fb,Fail +kms_plane_alpha_blend@alpha-transparent-fb,Fail +kms_plane_alpha_blend@constant-alpha-max,Fail diff --git a/drivers/gpu/drm/ci/xfails/i915-cml-flakes.txt b/drivers/gpu/drm/ci/xfails/i915-cml-flakes.txt new file mode 100644 index 000000000000..0514a7b3fdb0 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-cml-flakes.txt @@ -0,0 +1,38 @@ +kms_bw@linear-tiling-2-displays-1920x1080p +kms_bw@linear-tiling-2-displays-2560x1440p +kms_bw@linear-tiling-2-displays-3840x2160p +kms_bw@linear-tiling-3-displays-1920x1080p +kms_bw@linear-tiling-3-displays-2560x1440p +kms_bw@linear-tiling-3-displays-3840x2160p +kms_bw@linear-tiling-4-displays-1920x1080p +kms_bw@linear-tiling-4-displays-2560x1440p +kms_bw@linear-tiling-4-displays-3840x2160p +kms_draw_crc@draw-method-xrgb8888-render-xtiled +kms_flip@flip-vs-suspend +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling +kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling +kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling +kms_hdr@bpc-switch-suspend +kms_plane_alpha_blend@constant-alpha-min +kms_plane_alpha_blend@pipe-A-alpha-basic +kms_plane_alpha_blend@pipe-A-alpha-opaque-fb +kms_plane_alpha_blend@pipe-A-alpha-transparent-fb +kms_plane_alpha_blend@pipe-A-constant-alpha-max +kms_plane_alpha_blend@pipe-B-alpha-basic +kms_plane_alpha_blend@pipe-B-alpha-opaque-fb +kms_plane_alpha_blend@pipe-B-alpha-transparent-fb +kms_plane_alpha_blend@pipe-B-constant-alpha-max +kms_plane_alpha_blend@pipe-C-alpha-basic +kms_plane_alpha_blend@pipe-C-alpha-opaque-fb +kms_plane_alpha_blend@pipe-C-alpha-transparent-fb +kms_plane_alpha_blend@pipe-C-constant-alpha-max +kms_psr2_su@page_flip-NV12 +kms_psr2_su@page_flip-P010 +kms_setmode@basic diff --git a/drivers/gpu/drm/ci/xfails/i915-cml-skips.txt b/drivers/gpu/drm/ci/xfails/i915-cml-skips.txt new file mode 100644 index 000000000000..6d3d7ddc377f --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-cml-skips.txt @@ -0,0 +1,2 @@ +# This is generating kernel oops with divide error +kms_plane_scaling@invalid-parameters diff --git a/drivers/gpu/drm/ci/xfails/i915-glk-fails.txt b/drivers/gpu/drm/ci/xfails/i915-glk-fails.txt new file mode 100644 index 000000000000..5bd432e78129 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-glk-fails.txt @@ -0,0 +1,19 @@ +kms_fbcon_fbt@fbc,Fail +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail +kms_frontbuffer_tracking@fbcdrrs-tiling-linear,Fail +kms_plane_alpha_blend@alpha-basic,Fail +kms_plane_alpha_blend@alpha-opaque-fb,Fail +kms_plane_alpha_blend@alpha-transparent-fb,Fail +kms_plane_alpha_blend@constant-alpha-max,Fail diff --git a/drivers/gpu/drm/ci/xfails/i915-glk-flakes.txt b/drivers/gpu/drm/ci/xfails/i915-glk-flakes.txt new file mode 100644 index 000000000000..fc41d13a2d56 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-glk-flakes.txt @@ -0,0 +1,41 @@ +kms_bw@linear-tiling-1-displays-3840x2160p +kms_bw@linear-tiling-2-displays-1920x1080p +kms_bw@linear-tiling-2-displays-2560x1440p +kms_bw@linear-tiling-2-displays-3840x2160p +kms_bw@linear-tiling-3-displays-1920x1080p +kms_bw@linear-tiling-3-displays-2560x1440p +kms_bw@linear-tiling-3-displays-3840x2160p +kms_bw@linear-tiling-4-displays-1920x1080p +kms_bw@linear-tiling-4-displays-2560x1440p +kms_bw@linear-tiling-4-displays-3840x2160p +kms_flip@blocking-wf_vblank +kms_flip@wf_vblank-ts-check +kms_flip@wf_vblank-ts-check-interruptible +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling +kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling +kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling +kms_frontbuffer_tracking@fbc-tiling-linear +kms_plane_alpha_blend@pipe-A-alpha-basic +kms_plane_alpha_blend@pipe-A-alpha-opaque-fb +kms_plane_alpha_blend@pipe-A-alpha-transparent-fb +kms_plane_alpha_blend@pipe-A-constant-alpha-max +kms_plane_alpha_blend@pipe-B-alpha-basic +kms_plane_alpha_blend@pipe-B-alpha-opaque-fb +kms_plane_alpha_blend@pipe-B-alpha-transparent-fb +kms_plane_alpha_blend@pipe-B-constant-alpha-max +kms_plane_alpha_blend@pipe-C-alpha-basic +kms_plane_alpha_blend@pipe-C-alpha-opaque-fb +kms_plane_alpha_blend@pipe-C-alpha-transparent-fb +kms_plane_alpha_blend@pipe-C-constant-alpha-max +kms_prop_blob@invalid-set-prop-any +kms_rotation_crc@multiplane-rotation +kms_rotation_crc@multiplane-rotation-cropping-bottom +kms_rotation_crc@multiplane-rotation-cropping-top +kms_setmode@basic diff --git a/drivers/gpu/drm/ci/xfails/i915-glk-skips.txt b/drivers/gpu/drm/ci/xfails/i915-glk-skips.txt new file mode 100644 index 000000000000..4c7d00ce14bc --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-glk-skips.txt @@ -0,0 +1,5 @@ +# Suspend to RAM seems to be broken on this machine +.*suspend.* + +# This is generating kernel oops with divide error +kms_plane_scaling@invalid-parameters
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/xfails/i915-kbl-fails.txt b/drivers/gpu/drm/ci/xfails/i915-kbl-fails.txt new file mode 100644 index 000000000000..56ec021a7679 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-kbl-fails.txt @@ -0,0 +1,25 @@ +kms_bw@linear-tiling-2-displays-2560x1440p,Fail +kms_bw@linear-tiling-4-displays-2560x1440p,Fail +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling,Fail +kms_plane_alpha_blend@alpha-basic,Fail +kms_plane_alpha_blend@alpha-opaque-fb,Fail +kms_plane_alpha_blend@alpha-transparent-fb,Fail +kms_plane_alpha_blend@constant-alpha-max,Fail +kms_plane_alpha_blend@pipe-A-constant-alpha-max,Fail +kms_plane_alpha_blend@pipe-B-alpha-opaque-fb,Fail +kms_plane_alpha_blend@pipe-C-constant-alpha-max,Fail diff --git a/drivers/gpu/drm/ci/xfails/i915-kbl-flakes.txt b/drivers/gpu/drm/ci/xfails/i915-kbl-flakes.txt new file mode 100644 index 000000000000..f3ba1c4c5d46 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-kbl-flakes.txt @@ -0,0 +1,26 @@ +kms_async_flips@crc +kms_bw@linear-tiling-2-displays-1920x1080p +kms_bw@linear-tiling-2-displays-3840x2160p +kms_bw@linear-tiling-3-displays-1920x1080p +kms_bw@linear-tiling-3-displays-2560x1440p +kms_bw@linear-tiling-3-displays-3840x2160p +kms_bw@linear-tiling-4-displays-1920x1080p +kms_bw@linear-tiling-4-displays-3840x2160p +kms_color@ctm-0-25 +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling +kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling +kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling +kms_plane_alpha_blend@pipe-A-alpha-basic +kms_plane_alpha_blend@pipe-A-alpha-opaque-fb +kms_plane_alpha_blend@pipe-A-alpha-transparent-fb +kms_plane_alpha_blend@pipe-B-alpha-basic +kms_plane_alpha_blend@pipe-B-alpha-transparent-fb +kms_plane_alpha_blend@pipe-B-constant-alpha-max +kms_plane_alpha_blend@pipe-C-alpha-basic +kms_plane_alpha_blend@pipe-C-alpha-opaque-fb +kms_plane_alpha_blend@pipe-C-alpha-transparent-fb +kms_sysfs_edid_timing diff --git a/drivers/gpu/drm/ci/xfails/i915-kbl-skips.txt b/drivers/gpu/drm/ci/xfails/i915-kbl-skips.txt new file mode 100644 index 000000000000..4c7d00ce14bc --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-kbl-skips.txt @@ -0,0 +1,5 @@ +# Suspend to RAM seems to be broken on this machine +.*suspend.* + +# This is generating kernel oops with divide error +kms_plane_scaling@invalid-parameters
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/xfails/i915-tgl-fails.txt b/drivers/gpu/drm/ci/xfails/i915-tgl-fails.txt new file mode 100644 index 000000000000..a6da5544e198 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-tgl-fails.txt @@ -0,0 +1,37 @@ +kms_bw@linear-tiling-2-displays-3840x2160p,Fail +kms_bw@linear-tiling-3-displays-1920x1080p,Fail +kms_bw@linear-tiling-3-displays-2560x1440p,Fail +kms_bw@linear-tiling-3-displays-3840x2160p,Fail +kms_bw@linear-tiling-4-displays-1920x1080p,Fail +kms_bw@linear-tiling-4-displays-2560x1440p,Fail +kms_bw@linear-tiling-4-displays-3840x2160p,Fail +kms_bw@linear-tiling-5-displays-1920x1080p,Fail +kms_bw@linear-tiling-5-displays-2560x1440p,Fail +kms_bw@linear-tiling-5-displays-3840x2160p,Fail +kms_color@ctm-0-25,Fail +kms_flip@flip-vs-panning-vs-hang,Timeout +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling,Fail +kms_rotation_crc@bad-pixel-format,Fail +kms_rotation_crc@multiplane-rotation,Fail +kms_rotation_crc@multiplane-rotation-cropping-bottom,Fail +kms_rotation_crc@multiplane-rotation-cropping-top,Fail diff --git a/drivers/gpu/drm/ci/xfails/i915-tgl-flakes.txt b/drivers/gpu/drm/ci/xfails/i915-tgl-flakes.txt new file mode 100644 index 000000000000..1cd910ee06df --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-tgl-flakes.txt @@ -0,0 +1,5 @@ +kms_draw_crc@.* +kms_flip@blocking-absolute-wf_vblank +kms_flip@bo-too-big-interruptible +kms_flip@busy-flip +kms_flip@flip-vs-rmfb-interruptible diff --git a/drivers/gpu/drm/ci/xfails/i915-tgl-skips.txt b/drivers/gpu/drm/ci/xfails/i915-tgl-skips.txt new file mode 100644 index 000000000000..1d0621750b14 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-tgl-skips.txt @@ -0,0 +1,11 @@ +# Suspend to RAM seems to be broken on this machine +.*suspend.* + +# GPU hangs, then the whole machine +gem_eio.* + +# Whole machine hangs +kms_flip@absolute-wf_vblank@a-edp1 + +# This is generating kernel oops with divide error +kms_plane_scaling@invalid-parameters
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/xfails/i915-whl-fails.txt b/drivers/gpu/drm/ci/xfails/i915-whl-fails.txt new file mode 100644 index 000000000000..967327ddc1ac --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-whl-fails.txt @@ -0,0 +1,48 @@ +kms_bw@linear-tiling-2-displays-1920x1080p,Fail +kms_bw@linear-tiling-2-displays-2560x1440p,Fail +kms_bw@linear-tiling-2-displays-3840x2160p,Fail +kms_bw@linear-tiling-3-displays-1920x1080p,Fail +kms_bw@linear-tiling-3-displays-2560x1440p,Fail +kms_bw@linear-tiling-3-displays-3840x2160p,Fail +kms_bw@linear-tiling-4-displays-1920x1080p,Fail +kms_bw@linear-tiling-4-displays-2560x1440p,Fail +kms_bw@linear-tiling-4-displays-3840x2160p,Fail +kms_fbcon_fbt@fbc,Fail +kms_fbcon_fbt@fbc-suspend,Fail +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling,Fail +kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling,Fail +kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling,Fail +kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-upscaling,Fail +kms_frontbuffer_tracking@fbc-tiling-linear,Fail +kms_plane_alpha_blend@alpha-basic,Fail +kms_plane_alpha_blend@alpha-opaque-fb,Fail +kms_plane_alpha_blend@alpha-transparent-fb,Fail +kms_plane_alpha_blend@constant-alpha-max,Fail +kms_plane_alpha_blend@pipe-A-alpha-opaque-fb,Fail +kms_plane_alpha_blend@pipe-A-alpha-transparent-fb,Fail +kms_plane_alpha_blend@pipe-A-constant-alpha-max,Fail +kms_plane_alpha_blend@pipe-B-alpha-opaque-fb,Fail +kms_plane_alpha_blend@pipe-B-alpha-transparent-fb,Fail +kms_plane_alpha_blend@pipe-B-constant-alpha-max,Fail +kms_plane_alpha_blend@pipe-C-alpha-opaque-fb,Fail +kms_plane_alpha_blend@pipe-C-alpha-transparent-fb,Fail +kms_plane_alpha_blend@pipe-C-constant-alpha-max,Fail diff --git a/drivers/gpu/drm/ci/xfails/i915-whl-flakes.txt b/drivers/gpu/drm/ci/xfails/i915-whl-flakes.txt new file mode 100644 index 000000000000..c33202e7e2a1 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-whl-flakes.txt @@ -0,0 +1 @@ +kms_flip@flip-vs-suspend diff --git a/drivers/gpu/drm/ci/xfails/i915-whl-skips.txt b/drivers/gpu/drm/ci/xfails/i915-whl-skips.txt new file mode 100644 index 000000000000..f3be0888a214 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/i915-whl-skips.txt @@ -0,0 +1,2 @@ +# This is generating kernel oops with divide error +kms_plane_scaling@invalid-parameters
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/xfails/mediatek-mt8173-fails.txt b/drivers/gpu/drm/ci/xfails/mediatek-mt8173-fails.txt new file mode 100644 index 000000000000..671916067dba --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/mediatek-mt8173-fails.txt @@ -0,0 +1,29 @@ +kms_3d,Fail +kms_addfb_basic@addfb25-bad-modifier,Fail +kms_bw@linear-tiling-1-displays-1920x1080p,Fail +kms_bw@linear-tiling-1-displays-2560x1440p,Fail +kms_bw@linear-tiling-1-displays-3840x2160p,Fail +kms_bw@linear-tiling-2-displays-1920x1080p,Fail +kms_bw@linear-tiling-2-displays-2560x1440p,Fail +kms_bw@linear-tiling-2-displays-3840x2160p,Fail +kms_bw@linear-tiling-3-displays-1920x1080p,Fail +kms_bw@linear-tiling-3-displays-2560x1440p,Fail +kms_bw@linear-tiling-3-displays-3840x2160p,Fail +kms_color@pipe-A-invalid-gamma-lut-sizes,Fail +kms_color@pipe-B-invalid-gamma-lut-sizes,Fail +kms_force_connector_basic@force-connector-state,Fail +kms_force_connector_basic@force-edid,Fail +kms_force_connector_basic@force-load-detect,Fail +kms_force_connector_basic@prune-stale-modes,Fail +kms_invalid_mode@int-max-clock,Fail +kms_plane_scaling@planes-upscale-20x20,Fail +kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25,Fail +kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5,Fail +kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75,Fail +kms_plane_scaling@upscale-with-modifier-20x20,Fail +kms_plane_scaling@upscale-with-pixel-format-20x20,Fail +kms_plane_scaling@upscale-with-rotation-20x20,Fail +kms_properties@get_properties-sanity-atomic,Fail +kms_properties@plane-properties-atomic,Fail +kms_properties@plane-properties-legacy,Fail +kms_rmfb@close-fd,Fail diff --git a/drivers/gpu/drm/ci/xfails/mediatek-mt8173-flakes.txt b/drivers/gpu/drm/ci/xfails/mediatek-mt8173-flakes.txt new file mode 100644 index 000000000000..e69de29bb2d1 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/mediatek-mt8173-flakes.txt diff --git a/drivers/gpu/drm/ci/xfails/mediatek-mt8183-fails.txt b/drivers/gpu/drm/ci/xfails/mediatek-mt8183-fails.txt new file mode 100644 index 000000000000..6ff81d00e84e --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/mediatek-mt8183-fails.txt @@ -0,0 +1,10 @@ +kms_addfb_basic@addfb25-bad-modifier,Fail +kms_bw@linear-tiling-1-displays-2560x1440p,Fail +kms_bw@linear-tiling-2-displays-1920x1080p,Fail +kms_bw@linear-tiling-2-displays-2560x1440p,Fail +kms_bw@linear-tiling-2-displays-3840x2160p,Fail +kms_bw@linear-tiling-3-displays-2560x1440p,Fail +kms_bw@linear-tiling-3-displays-3840x2160p,Fail +kms_color@pipe-A-invalid-gamma-lut-sizes,Fail +kms_plane_scaling@upscale-with-rotation-20x20,Fail +kms_rmfb@close-fd,Fail
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/xfails/mediatek-mt8183-flakes.txt b/drivers/gpu/drm/ci/xfails/mediatek-mt8183-flakes.txt new file mode 100644 index 000000000000..208890b79eb0 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/mediatek-mt8183-flakes.txt @@ -0,0 +1,14 @@ +core_setmaster_vs_auth +kms_bw@linear-tiling-1-displays-1920x1080p +kms_bw@linear-tiling-1-displays-3840x2160p +kms_bw@linear-tiling-3-displays-1920x1080p +kms_cursor_legacy@cursor-vs-flip-atomic +kms_plane_scaling@invalid-num-scalers +kms_plane_scaling@planes-upscale-20x20 +kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5 +kms_plane_scaling@upscale-with-modifier-20x20 +kms_plane_scaling@upscale-with-pixel-format-20x20 +kms_prop_blob@invalid-set-prop-any +kms_properties@get_properties-sanity-atomic +kms_properties@plane-properties-atomic +kms_properties@plane-properties-legacy
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/xfails/meson-g12b-fails.txt b/drivers/gpu/drm/ci/xfails/meson-g12b-fails.txt new file mode 100644 index 000000000000..860e702091e2 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/meson-g12b-fails.txt @@ -0,0 +1,12 @@ +kms_3d,Fail +kms_properties@connector-properties-atomic,Fail +kms_properties@get_properties-sanity-atomic,Fail +kms_properties@get_properties-sanity-non-atomic,Fail +kms_properties@connector-properties-legacy,Fail +kms_cursor_legacy@forked-bo,Fail +kms_cursor_legacy@forked-move,Fail +kms_cursor_legacy@single-bo,Fail +kms_cursor_legacy@single-move,Fail +kms_cursor_legacy@torture-bo,Fail +kms_cursor_legacy@torture-move,Fail +kms_hdmi_inject@inject-4k,Fail
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/xfails/meson-g12b-flakes.txt b/drivers/gpu/drm/ci/xfails/meson-g12b-flakes.txt new file mode 100644 index 000000000000..b63329d06767 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/meson-g12b-flakes.txt @@ -0,0 +1,4 @@ +kms_force_connector_basic@force-connector-state +kms_force_connector_basic@force-edid +kms_force_connector_basic@force-load-detect +kms_force_connector_basic@prune-stale-modes
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/xfails/msm-apq8016-fails.txt b/drivers/gpu/drm/ci/xfails/msm-apq8016-fails.txt new file mode 100644 index 000000000000..9981682feab2 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/msm-apq8016-fails.txt @@ -0,0 +1,15 @@ +kms_3d,Fail +kms_addfb_basic@addfb25-bad-modifier,Fail +kms_cursor_legacy@all-pipes-forked-bo,Fail +kms_cursor_legacy@all-pipes-forked-move,Fail +kms_cursor_legacy@all-pipes-single-bo,Fail +kms_cursor_legacy@all-pipes-single-move,Fail +kms_cursor_legacy@all-pipes-torture-bo,Fail +kms_cursor_legacy@all-pipes-torture-move,Fail +kms_cursor_legacy@pipe-A-forked-bo,Fail +kms_cursor_legacy@pipe-A-forked-move,Fail +kms_cursor_legacy@pipe-A-single-bo,Fail +kms_cursor_legacy@pipe-A-single-move,Fail +kms_cursor_legacy@pipe-A-torture-bo,Fail +kms_cursor_legacy@pipe-A-torture-move,Fail +kms_hdmi_inject@inject-4k,Fail diff --git a/drivers/gpu/drm/ci/xfails/msm-apq8016-flakes.txt b/drivers/gpu/drm/ci/xfails/msm-apq8016-flakes.txt new file mode 100644 index 000000000000..0e3b60d3fade --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/msm-apq8016-flakes.txt @@ -0,0 +1,4 @@ +kms_force_connector_basic@force-connector-state +kms_force_connector_basic@force-edid +kms_force_connector_basic@force-load-detect +kms_force_connector_basic@prune-stale-modes diff --git a/drivers/gpu/drm/ci/xfails/msm-apq8096-fails.txt b/drivers/gpu/drm/ci/xfails/msm-apq8096-fails.txt new file mode 100644 index 000000000000..88a1fc0a3b0d --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/msm-apq8096-fails.txt @@ -0,0 +1,2 @@ +kms_3d,Fail +kms_addfb_basic@addfb25-bad-modifier,Fail diff --git a/drivers/gpu/drm/ci/xfails/msm-apq8096-flakes.txt b/drivers/gpu/drm/ci/xfails/msm-apq8096-flakes.txt new file mode 100644 index 000000000000..0e3b60d3fade --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/msm-apq8096-flakes.txt @@ -0,0 +1,4 @@ +kms_force_connector_basic@force-connector-state +kms_force_connector_basic@force-edid +kms_force_connector_basic@force-load-detect +kms_force_connector_basic@prune-stale-modes diff --git a/drivers/gpu/drm/ci/xfails/msm-apq8096-skips.txt b/drivers/gpu/drm/ci/xfails/msm-apq8096-skips.txt new file mode 100644 index 000000000000..cd49c8ce2059 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/msm-apq8096-skips.txt @@ -0,0 +1,2 @@ +# Whole machine hangs +kms_cursor_legacy@all-pipes-torture-move
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/xfails/msm-sc7180-fails.txt b/drivers/gpu/drm/ci/xfails/msm-sc7180-fails.txt new file mode 100644 index 000000000000..14adeba3b62d --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/msm-sc7180-fails.txt @@ -0,0 +1,25 @@ +kms_cursor_legacy@cursor-vs-flip-toggle,Fail +kms_cursor_legacy@cursor-vs-flip-varying-size,Fail +kms_cursor_legacy@cursorA-vs-flipA-atomic-transitions,Crash +kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail +kms_plane@pixel-format,Fail +kms_plane@pixel-format-source-clamping,Fail +kms_plane@plane-position-covered,Fail +kms_plane@plane-position-hole,Fail +kms_plane@plane-position-hole-dpms,Fail +kms_plane_alpha_blend@alpha-7efc,Fail +kms_plane_alpha_blend@coverage-7efc,Fail +kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail +kms_plane_alpha_blend@pipe-A-alpha-7efc,Fail +kms_plane_alpha_blend@pipe-A-coverage-7efc,Fail +kms_plane_alpha_blend@pipe-A-coverage-vs-premult-vs-constant,Fail +kms_plane_alpha_blend@pipe-B-alpha-7efc,Fail +kms_plane_alpha_blend@pipe-B-alpha-basic,Fail +kms_plane_alpha_blend@pipe-B-alpha-opaque-fb,Fail +kms_plane_alpha_blend@pipe-B-constant-alpha-max,Fail +kms_plane_alpha_blend@pipe-B-constant-alpha-mid,Fail +kms_plane_alpha_blend@pipe-B-coverage-7efc,Fail +kms_plane_alpha_blend@pipe-B-coverage-vs-premult-vs-constant,Fail +kms_rmfb@close-fd,Fail +kms_universal_plane@disable-primary-vs-flip-pipe-b,Fail +kms_universal_plane@universal-plane-pipe-B-sanity,Fail diff --git a/drivers/gpu/drm/ci/xfails/msm-sc7180-flakes.txt b/drivers/gpu/drm/ci/xfails/msm-sc7180-flakes.txt new file mode 100644 index 000000000000..636563d3e59a --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/msm-sc7180-flakes.txt @@ -0,0 +1,7 @@ + +# Test ends up reading CRC from frame before cursor update +# bug +# sometimes.. tbd if this is a kernel CRC bug or a test +kms_cursor_crc@.* +kms_plane_multiple@atomic-pipe-A-tiling-none +kms_atomic_transition@modeset-transition-nonblocking-fencing,Fail
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/xfails/msm-sc7180-skips.txt b/drivers/gpu/drm/ci/xfails/msm-sc7180-skips.txt new file mode 100644 index 000000000000..410e0eeb3161 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/msm-sc7180-skips.txt @@ -0,0 +1,23 @@ +# Suspend to RAM seems to be broken on this machine +.*suspend.* + +# Test incorrectly assumes that CTM support implies gamma/degamma +# LUT support. None of the subtests handle the case of only having +# CTM support +kms_color.* + +# 4k@60 is not supported on this hw, but driver doesn't handle it +# too gracefully.. https://gitlab.freedesktop.org/drm/msm/-/issues/15 +kms_bw@linear-tiling-.*-displays-3840x2160p + +# Until igt fix lands: https://patchwork.freedesktop.org/patch/493175/ +kms_bw@linear-tiling-2.* +kms_bw@linear-tiling-3.* +kms_bw@linear-tiling-4.* +kms_bw@linear-tiling-5.* +kms_bw@linear-tiling-6.* + +# igt fix posted: https://patchwork.freedesktop.org/patch/499926/ +# failure mode is flakey due to randomization but fails frequently +# enough to be detected as a Crash or occasionally UnexpectedPass. +kms_plane_multiple@atomic-pipe-A-tiling-none diff --git a/drivers/gpu/drm/ci/xfails/msm-sdm845-fails.txt b/drivers/gpu/drm/ci/xfails/msm-sdm845-fails.txt new file mode 100644 index 000000000000..09c0c623cd75 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/msm-sdm845-fails.txt @@ -0,0 +1,68 @@ +kms_color@ctm-0-25,Fail +kms_color@ctm-0-50,Fail +kms_color@ctm-0-75,Fail +kms_color@ctm-blue-to-red,Fail +kms_color@ctm-green-to-red,Fail +kms_color@ctm-negative,Fail +kms_color@ctm-red-to-blue,Fail +kms_color@ctm-signed,Fail +kms_color@pipe-A-ctm-0-25,Fail +kms_color@pipe-A-ctm-0-5,Fail +kms_color@pipe-A-ctm-0-75,Fail +kms_color@pipe-A-ctm-blue-to-red,Fail +kms_color@pipe-A-ctm-green-to-red,Fail +kms_color@pipe-A-ctm-max,Fail +kms_color@pipe-A-ctm-negative,Fail +kms_color@pipe-A-ctm-red-to-blue,Fail +kms_color@pipe-A-legacy-gamma,Fail +kms_cursor_legacy@basic-flip-after-cursor-atomic,Fail +kms_cursor_legacy@basic-flip-after-cursor-legacy,Fail +kms_cursor_legacy@basic-flip-after-cursor-varying-size,Fail +kms_cursor_legacy@basic-flip-before-cursor-atomic,Fail +kms_cursor_legacy@basic-flip-before-cursor-legacy,Fail +kms_cursor_legacy@basic-flip-before-cursor-varying-size,Fail +kms_cursor_legacy@cursor-vs-flip-atomic,Fail +kms_cursor_legacy@cursor-vs-flip-atomic-transitions,Fail +kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size,Fail +kms_cursor_legacy@cursor-vs-flip-legacy,Fail +kms_cursor_legacy@cursor-vs-flip-toggle,Fail +kms_cursor_legacy@cursor-vs-flip-varying-size,Fail +kms_cursor_legacy@cursorA-vs-flipA-toggle,Fail +kms_cursor_legacy@flip-vs-cursor-atomic,Fail +kms_cursor_legacy@flip-vs-cursor-crc-atomic,Fail +kms_cursor_legacy@flip-vs-cursor-crc-legacy,Fail +kms_cursor_legacy@flip-vs-cursor-legacy,Fail +kms_cursor_legacy@short-flip-after-cursor-atomic-transitions,Fail +kms_cursor_legacy@short-flip-after-cursor-atomic-transitions-varying-size,Fail +kms_cursor_legacy@short-flip-after-cursor-toggle,Fail +kms_cursor_legacy@short-flip-before-cursor-atomic-transitions,Fail +kms_cursor_legacy@short-flip-before-cursor-atomic-transitions-varying-size,Fail +kms_pipe_crc_basic@compare-crc-sanitycheck-nv12,Fail +kms_plane@pixel-format,Fail +kms_plane@pixel-format-source-clamping,Fail +kms_plane_alpha_blend@alpha-7efc,Fail +kms_plane_alpha_blend@coverage-7efc,Fail +kms_plane_alpha_blend@coverage-vs-premult-vs-constant,Fail +kms_plane_alpha_blend@pipe-A-alpha-7efc,Fail +kms_plane_alpha_blend@pipe-A-coverage-7efc,Fail +kms_plane_alpha_blend@pipe-A-coverage-vs-premult-vs-constant,Fail +kms_plane_cursor@overlay,Fail +kms_plane_cursor@pipe-A-overlay-size-128,Fail +kms_plane_cursor@pipe-A-overlay-size-256,Fail +kms_plane_cursor@pipe-A-overlay-size-64,Fail +kms_plane_cursor@pipe-A-viewport-size-128,Fail +kms_plane_cursor@pipe-A-viewport-size-256,Fail +kms_plane_cursor@pipe-A-viewport-size-64,Fail +kms_plane_cursor@viewport,Fail +kms_plane_scaling@downscale-with-pixel-format-factor-0-25,Timeout +kms_plane_scaling@downscale-with-pixel-format-factor-0-5,Timeout +kms_plane_scaling@downscale-with-pixel-format-factor-0-75,Timeout +kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25,Timeout +kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5,Timeout +kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-75,Timeout +kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats,Timeout +kms_plane_scaling@plane-scaler-with-pixel-format-unity-scaling,Timeout +kms_plane_scaling@planes-downscale-factor-0-25,Fail +kms_plane_scaling@scaler-with-clipping-clamping,Timeout +kms_plane_scaling@scaler-with-pixel-format-unity-scaling,Timeout +kms_rmfb@close-fd,Fail diff --git a/drivers/gpu/drm/ci/xfails/msm-sdm845-flakes.txt b/drivers/gpu/drm/ci/xfails/msm-sdm845-flakes.txt new file mode 100644 index 000000000000..5b3aaab7ac3f --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/msm-sdm845-flakes.txt @@ -0,0 +1,11 @@ + + +# Test ends up reading CRC from frame before cursor update +# bug +# sometimes.. tbd if this is a kernel CRC bug or a test +kms_cursor_crc@.* +kms_cursor_legacy@flip-vs-cursor-toggle +kms_cursor_legacy@pipe-A-forked-bo +kms_cursor_legacy@pipe-A-forked-move +kms_cursor_legacy@short-flip-before-cursor-toggle +kms_flip@dpms-vs-vblank-race-interruptible diff --git a/drivers/gpu/drm/ci/xfails/msm-sdm845-skips.txt b/drivers/gpu/drm/ci/xfails/msm-sdm845-skips.txt new file mode 100644 index 000000000000..42675f1c6d76 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/msm-sdm845-skips.txt @@ -0,0 +1,2 @@ +# Hangs machine +kms_bw.*
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/xfails/rockchip-rk3288-fails.txt b/drivers/gpu/drm/ci/xfails/rockchip-rk3288-fails.txt new file mode 100644 index 000000000000..2a1baa948e12 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/rockchip-rk3288-fails.txt @@ -0,0 +1,48 @@ +kms_3d,Crash +kms_bw@linear-tiling-2-displays-1920x1080p,Fail +kms_bw@linear-tiling-2-displays-2560x1440p,Fail +kms_bw@linear-tiling-2-displays-3840x2160p,Fail +kms_bw@linear-tiling-3-displays-1920x1080p,Fail +kms_bw@linear-tiling-3-displays-2560x1440p,Fail +kms_bw@linear-tiling-3-displays-3840x2160p,Fail +kms_force_connector_basic@force-load-detect,Fail +kms_invalid_mode@int-max-clock,Crash +kms_plane@pixel-format,Crash +kms_plane@pixel-format-source-clamping,Crash +kms_plane@plane-position-hole,Crash +kms_plane@plane-position-hole-dpms,Crash +kms_plane_cursor@overlay,Crash +kms_plane_cursor@pipe-A-overlay-size-128,Fail +kms_plane_cursor@pipe-A-overlay-size-256,Fail +kms_plane_cursor@pipe-A-overlay-size-64,Fail +kms_plane_cursor@pipe-A-primary-size-128,Fail +kms_plane_cursor@pipe-A-primary-size-256,Fail +kms_plane_cursor@pipe-A-primary-size-64,Fail +kms_plane_cursor@pipe-A-viewport-size-128,Fail +kms_plane_cursor@pipe-A-viewport-size-256,Fail +kms_plane_cursor@pipe-A-viewport-size-64,Fail +kms_plane_cursor@pipe-B-overlay-size-128,Fail +kms_plane_cursor@pipe-B-overlay-size-256,Fail +kms_plane_cursor@pipe-B-overlay-size-64,Fail +kms_plane_cursor@pipe-B-primary-size-128,Fail +kms_plane_cursor@pipe-B-primary-size-256,Fail +kms_plane_cursor@pipe-B-primary-size-64,Fail +kms_plane_cursor@pipe-B-viewport-size-128,Fail +kms_plane_cursor@pipe-B-viewport-size-256,Fail +kms_plane_cursor@pipe-B-viewport-size-64,Fail +kms_plane_cursor@primary,Crash +kms_plane_cursor@viewport,Crash +kms_plane_lowres@tiling-none,Fail +kms_plane_scaling@downscale-with-modifier-factor-0-25,Fail +kms_plane_scaling@downscale-with-rotation-factor-0-25,Fail +kms_plane_scaling@upscale-with-modifier-20x20,Fail +kms_plane_scaling@upscale-with-modifier-factor-0-25,Fail +kms_plane_scaling@upscale-with-pixel-format-20x20,Fail +kms_plane_scaling@upscale-with-pixel-format-factor-0-25,Fail +kms_plane_scaling@upscale-with-rotation-20x20,Fail +kms_prime@basic-crc,Fail +kms_properties@connector-properties-atomic,Crash +kms_properties@connector-properties-legacy,Crash +kms_properties@get_properties-sanity-atomic,Crash +kms_properties@get_properties-sanity-non-atomic,Crash +kms_setmode@invalid-clone-single-crtc,Crash diff --git a/drivers/gpu/drm/ci/xfails/rockchip-rk3288-flakes.txt b/drivers/gpu/drm/ci/xfails/rockchip-rk3288-flakes.txt new file mode 100644 index 000000000000..45c54c75c899 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/rockchip-rk3288-flakes.txt @@ -0,0 +1,9 @@ +kms_addfb_basic@addfb25-bad-modifier +kms_cursor_crc@.* +kms_flip@basic-flip-vs-wf_vblank +kms_invalid_mode@int-max-clock,Crash +kms_pipe_crc_basic@.* +kms_properties@connector-properties-atomic,Crash +kms_properties@get_properties-sanity-atomic,Crash +kms_properties@get_properties-sanity-non-atomic,Crash +kms_rmfb@close-fd diff --git a/drivers/gpu/drm/ci/xfails/rockchip-rk3288-skips.txt b/drivers/gpu/drm/ci/xfails/rockchip-rk3288-skips.txt new file mode 100644 index 000000000000..f20c3574b75a --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/rockchip-rk3288-skips.txt @@ -0,0 +1,52 @@ +# Suspend to RAM seems to be broken on this machine +.*suspend.* + +# Too unstable, machine ends up hanging after lots of Oopses +kms_cursor_legacy.* + +# Started hanging the machine on Linux 5.19-rc2: +# +# [IGT] kms_plane_lowres: executing +# [IGT] kms_plane_lowres: starting subtest pipe-F-tiling-y +# [IGT] kms_plane_lowres: exiting, ret=77 +# Console: switching to colour frame buffer device 170x48 +# rockchip-drm display-subsystem: [drm] *ERROR* flip_done timed out +# rockchip-drm display-subsystem: [drm] *ERROR* [CRTC:35:crtc-0] commit wait timed out +# BUG: spinlock bad magic on CPU#3, kms_plane_lowre/482 +# 8<--- cut here --- +# Unable to handle kernel paging request at virtual address 7812078e +# [7812078e] *pgd=00000000 +# Internal error: Oops: 5 [#1] SMP ARM +# Modules linked in: +# CPU: 3 PID: 482 Comm: kms_plane_lowre Tainted: G W 5.19.0-rc2-323596-g00535de92171 #1 +# Hardware name: Rockchip (Device Tree) +# Process kms_plane_lowre (pid: 482, stack limit = 0x1193ac2b) +# spin_dump from do_raw_spin_lock+0xa4/0xe8 +# do_raw_spin_lock from wait_for_completion_timeout+0x2c/0x120 +# wait_for_completion_timeout from drm_crtc_commit_wait+0x18/0x7c +# drm_crtc_commit_wait from drm_atomic_helper_wait_for_dependencies+0x44/0x168 +# drm_atomic_helper_wait_for_dependencies from commit_tail+0x34/0x180 +# commit_tail from drm_atomic_helper_commit+0x164/0x18c +# drm_atomic_helper_commit from drm_atomic_commit+0xac/0xe4 +# drm_atomic_commit from drm_client_modeset_commit_atomic+0x23c/0x284 +# drm_client_modeset_commit_atomic from drm_client_modeset_commit_locked+0x60/0x1c8 +# drm_client_modeset_commit_locked from drm_client_modeset_commit+0x24/0x40 +# drm_client_modeset_commit from drm_fbdev_client_restore+0x58/0x94 +# drm_fbdev_client_restore from drm_client_dev_restore+0x70/0xbc +# drm_client_dev_restore from drm_release+0xf4/0x114 +# drm_release from __fput+0x74/0x240 +# __fput from task_work_run+0x84/0xb4 +# task_work_run from do_exit+0x34c/0xa20 +# do_exit from do_group_exit+0x34/0x98 +# do_group_exit from __wake_up_parent+0x0/0x18 +# Code: e595c008 12843d19 03e00000 03093168 (15940508) +# ---[ end trace 0000000000000000 ]--- +# note: kms_plane_lowre[482] exited with preempt_count 1 +# Fixing recursive fault but reboot is needed! +kms_plane_lowres@pipe-F-tiling-y + +# Take too long, we have only two machines, and these are very flaky +kms_cursor_crc.* + +# Machine is hanging in this test, so skip it +kms_pipe_crc_basic@disable-crc-after-crtc
\ No newline at end of file diff --git a/drivers/gpu/drm/ci/xfails/rockchip-rk3399-fails.txt b/drivers/gpu/drm/ci/xfails/rockchip-rk3399-fails.txt new file mode 100644 index 000000000000..6db08ba6b008 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/rockchip-rk3399-fails.txt @@ -0,0 +1,37 @@ +kms_color@legacy-gamma,Fail +kms_color@pipe-A-legacy-gamma,Fail +kms_color@pipe-B-legacy-gamma,Fail +kms_flip@basic-flip-vs-wf_vblank,Fail +kms_flip@blocking-wf_vblank,Fail +kms_flip@dpms-vs-vblank-race,Fail +kms_flip@flip-vs-absolute-wf_vblank,Fail +kms_flip@flip-vs-absolute-wf_vblank-interruptible,Fail +kms_flip@flip-vs-blocking-wf-vblank,Fail +kms_flip@flip-vs-panning,Fail +kms_flip@flip-vs-panning-interruptible,Fail +kms_flip@flip-vs-wf_vblank-interruptible,Fail +kms_flip@plain-flip-fb-recreate,Fail +kms_flip@plain-flip-fb-recreate-interruptible,Fail +kms_flip@plain-flip-ts-check,Fail +kms_flip@plain-flip-ts-check-interruptible,Fail +kms_flip@wf_vblank-ts-check,Fail +kms_flip@wf_vblank-ts-check-interruptible,Fail +kms_invalid_mode@int-max-clock,Fail +kms_plane@pixel-format,Fail +kms_plane@pixel-format-source-clamping,Fail +kms_plane@plane-panning-bottom-right,Fail +kms_plane@plane-panning-top-left,Fail +kms_plane@plane-position-covered,Fail +kms_plane_cursor@pipe-B-overlay-size-128,Fail +kms_plane_cursor@pipe-B-overlay-size-256,Fail +kms_plane_cursor@pipe-B-overlay-size-64,Fail +kms_plane_cursor@pipe-B-primary-size-128,Fail +kms_plane_cursor@pipe-B-primary-size-256,Fail +kms_plane_cursor@pipe-B-primary-size-64,Fail +kms_plane_cursor@pipe-B-viewport-size-128,Fail +kms_plane_cursor@pipe-B-viewport-size-256,Fail +kms_plane_cursor@pipe-B-viewport-size-64,Fail +kms_plane_multiple@atomic-pipe-B-tiling-none,Fail +kms_plane_multiple@tiling-none,Fail +kms_prime@basic-crc,Fail +kms_rmfb@close-fd,Fail diff --git a/drivers/gpu/drm/ci/xfails/rockchip-rk3399-flakes.txt b/drivers/gpu/drm/ci/xfails/rockchip-rk3399-flakes.txt new file mode 100644 index 000000000000..4c0539b4beaf --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/rockchip-rk3399-flakes.txt @@ -0,0 +1,23 @@ + +kms_cursor_crc@.* +kms_flip@dpms-vs-vblank-race-interruptible +kms_flip@flip-vs-expired-vblank +kms_flip@modeset-vs-vblank-race-interruptible +kms_pipe_crc_basic@.* +kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-A +kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-B +kms_plane@plane-position-hole +kms_plane_multiple@atomic-pipe-A-tiling-none +kms_plane_multiple@atomic-pipe-B-tiling-none +kms_sequence@get-forked +kms_sequence@get-forked-busy +kms_setmode@basic +kms_universal_plane@universal-plane-pipe-B-functional,UnexpectedPass +kms_vblank@pipe-A-accuracy-idle +kms_vblank@pipe-A-query-busy +kms_vblank@pipe-A-query-forked-busy +kms_vblank@pipe-A-wait-idle +kms_vblank@pipe-B-accuracy-idle +kms_vblank@pipe-B-query-busy +kms_vblank@pipe-B-query-forked-busy +kms_vblank@pipe-B-wait-idle diff --git a/drivers/gpu/drm/ci/xfails/rockchip-rk3399-skips.txt b/drivers/gpu/drm/ci/xfails/rockchip-rk3399-skips.txt new file mode 100644 index 000000000000..10c3d81a919a --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/rockchip-rk3399-skips.txt @@ -0,0 +1,5 @@ +# Suspend to RAM seems to be broken on this machine +.*suspend.* + +# Too unstable, machine ends up hanging after lots of Oopses +kms_cursor_legacy.* diff --git a/drivers/gpu/drm/ci/xfails/virtio_gpu-none-fails.txt b/drivers/gpu/drm/ci/xfails/virtio_gpu-none-fails.txt new file mode 100644 index 000000000000..9586b2339f6f --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/virtio_gpu-none-fails.txt @@ -0,0 +1,38 @@ +kms_addfb_basic@addfb25-bad-modifier,Fail +kms_addfb_basic@bad-pitch-65536,Fail +kms_addfb_basic@bo-too-small,Fail +kms_addfb_basic@size-max,Fail +kms_addfb_basic@too-high,Fail +kms_atomic_transition@plane-primary-toggle-with-vblank-wait,Fail +kms_bw@linear-tiling-1-displays-1920x1080p,Fail +kms_bw@linear-tiling-1-displays-2560x1440p,Fail +kms_bw@linear-tiling-1-displays-3840x2160p,Fail +kms_bw@linear-tiling-2-displays-1920x1080p,Fail +kms_bw@linear-tiling-2-displays-2560x1440p,Fail +kms_bw@linear-tiling-2-displays-3840x2160p,Fail +kms_invalid_mode@int-max-clock,Fail +kms_plane_scaling@downscale-with-modifier-factor-0-25,Fail +kms_plane_scaling@downscale-with-rotation-factor-0-25,Fail +kms_plane_scaling@planes-upscale-20x20,Fail +kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25,Fail +kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5,Fail +kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75,Fail +kms_plane_scaling@upscale-with-modifier-20x20,Fail +kms_plane_scaling@upscale-with-modifier-factor-0-25,Fail +kms_plane_scaling@upscale-with-pixel-format-20x20,Fail +kms_plane_scaling@upscale-with-pixel-format-factor-0-25,Fail +kms_plane_scaling@upscale-with-rotation-20x20,Fail +kms_vblank@crtc-id,Fail +kms_vblank@invalid,Fail +kms_vblank@pipe-A-accuracy-idle,Fail +kms_vblank@pipe-A-query-busy,Fail +kms_vblank@pipe-A-query-forked,Fail +kms_vblank@pipe-A-query-forked-busy,Fail +kms_vblank@pipe-A-query-idle,Fail +kms_vblank@pipe-A-ts-continuation-idle,Fail +kms_vblank@pipe-A-ts-continuation-modeset,Fail +kms_vblank@pipe-A-ts-continuation-suspend,Fail +kms_vblank@pipe-A-wait-busy,Fail +kms_vblank@pipe-A-wait-forked,Fail +kms_vblank@pipe-A-wait-forked-busy,Fail +kms_vblank@pipe-A-wait-idle,Fail diff --git a/drivers/gpu/drm/ci/xfails/virtio_gpu-none-flakes.txt b/drivers/gpu/drm/ci/xfails/virtio_gpu-none-flakes.txt new file mode 100644 index 000000000000..e69de29bb2d1 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/virtio_gpu-none-flakes.txt diff --git a/drivers/gpu/drm/ci/xfails/virtio_gpu-none-skips.txt b/drivers/gpu/drm/ci/xfails/virtio_gpu-none-skips.txt new file mode 100644 index 000000000000..78be18174012 --- /dev/null +++ b/drivers/gpu/drm/ci/xfails/virtio_gpu-none-skips.txt @@ -0,0 +1,6 @@ +# Hits a "refcount_t: underflow; use-after-free" in virtio_gpu_fence_event_process +# When run in a particular order with other tests +kms_cursor_legacy.* + +# Job just hangs without any output +kms_flip@flip-vs-suspend.*
\ No newline at end of file diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index bf8371dc2a61..c44d5bcf1284 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -2203,6 +2203,7 @@ static int drm_mode_create_colorspace_property(struct drm_connector *connector, /** * drm_mode_create_hdmi_colorspace_property - create hdmi colorspace property * @connector: connector to create the Colorspace property on. + * @supported_colorspaces: bitmap of supported color spaces * * Called by a driver the first time it's needed, must be attached to desired * HDMI connectors. @@ -2227,6 +2228,7 @@ EXPORT_SYMBOL(drm_mode_create_hdmi_colorspace_property); /** * drm_mode_create_dp_colorspace_property - create dp colorspace property * @connector: connector to create the Colorspace property on. + * @supported_colorspaces: bitmap of supported color spaces * * Called by a driver the first time it's needed, must be attached to desired * DP connectors. diff --git a/drivers/gpu/drm/drm_exec.c b/drivers/gpu/drm/drm_exec.c index ff69cf0fb42a..5d2809de4517 100644 --- a/drivers/gpu/drm/drm_exec.c +++ b/drivers/gpu/drm/drm_exec.c @@ -56,7 +56,7 @@ static void drm_exec_unlock_all(struct drm_exec *exec) struct drm_gem_object *obj; unsigned long index; - drm_exec_for_each_locked_object(exec, index, obj) { + drm_exec_for_each_locked_object_reverse(exec, index, obj) { dma_resv_unlock(obj->resv); drm_gem_object_put(obj); } diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c index 0cb646cb04ee..d5c15292ae93 100644 --- a/drivers/gpu/drm/drm_panel_orientation_quirks.c +++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c @@ -38,6 +38,14 @@ static const struct drm_dmi_panel_orientation_data gpd_micropc = { .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, }; +static const struct drm_dmi_panel_orientation_data gpd_onemix2s = { + .width = 1200, + .height = 1920, + .bios_dates = (const char * const []){ "05/21/2018", "10/26/2018", + "03/04/2019", NULL }, + .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, +}; + static const struct drm_dmi_panel_orientation_data gpd_pocket = { .width = 1200, .height = 1920, @@ -401,6 +409,14 @@ static const struct dmi_system_id orientation_data[] = { DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "LTH17"), }, .driver_data = (void *)&lcd800x1280_rightside_up, + }, { /* One Mix 2S (generic strings, also match on bios date) */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Default string"), + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Default string"), + DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Default string"), + DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"), + }, + .driver_data = (void *)&gpd_onemix2s, }, {} }; diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 858c959f7bab..f735b035436c 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -3540,6 +3540,27 @@ enum aux_ch intel_bios_dp_aux_ch(const struct intel_bios_encoder_data *devdata) return map_aux_ch(devdata->i915, devdata->child.aux_channel); } +bool intel_bios_dp_has_shared_aux_ch(const struct intel_bios_encoder_data *devdata) +{ + struct drm_i915_private *i915; + u8 aux_channel; + int count = 0; + + if (!devdata || !devdata->child.aux_channel) + return false; + + i915 = devdata->i915; + aux_channel = devdata->child.aux_channel; + + list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { + if (intel_bios_encoder_supports_dp(devdata) && + aux_channel == devdata->child.aux_channel) + count++; + } + + return count > 1; +} + int intel_bios_dp_boost_level(const struct intel_bios_encoder_data *devdata) { if (!devdata || devdata->i915->display.vbt.version < 196 || !devdata->child.iboost) diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h index 9680e3e92bb5..49e24b7cf675 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.h +++ b/drivers/gpu/drm/i915/display/intel_bios.h @@ -273,6 +273,7 @@ enum aux_ch intel_bios_dp_aux_ch(const struct intel_bios_encoder_data *devdata); int intel_bios_dp_boost_level(const struct intel_bios_encoder_data *devdata); int intel_bios_dp_max_lane_count(const struct intel_bios_encoder_data *devdata); int intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *devdata); +bool intel_bios_dp_has_shared_aux_ch(const struct intel_bios_encoder_data *devdata); int intel_bios_hdmi_boost_level(const struct intel_bios_encoder_data *devdata); int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata); int intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *devdata); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 12bd2f322e62..e0e4cb529284 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5512,8 +5512,13 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, /* * VBT and straps are liars. Also check HPD as that seems * to be the most reliable piece of information available. + * + * ... expect on devices that forgot to hook HPD up for eDP + * (eg. Acer Chromebook C710), so we'll check it only if multiple + * ports are attempting to use the same AUX CH, according to VBT. */ - if (!intel_digital_port_connected(encoder)) { + if (intel_bios_dp_has_shared_aux_ch(encoder->devdata) && + !intel_digital_port_connected(encoder)) { /* * If this fails, presume the DPCD answer came * from some other port using the same AUX CH. diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c index 6b6d22c19411..0ba955611dfb 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c @@ -198,7 +198,7 @@ static void flush_tlb_invalidate(struct drm_i915_gem_object *obj) for_each_gt(gt, i915, id) { if (!obj->mm.tlb[id]) - return; + continue; intel_gt_invalidate_tlb_full(gt, obj->mm.tlb[id]); obj->mm.tlb[id] = 0; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c index 8f1633c3fb93..73a4a4eb29e0 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c @@ -100,6 +100,7 @@ int shmem_sg_alloc_table(struct drm_i915_private *i915, struct sg_table *st, st->nents = 0; for (i = 0; i < page_count; i++) { struct folio *folio; + unsigned long nr_pages; const unsigned int shrink[] = { I915_SHRINK_BOUND | I915_SHRINK_UNBOUND, 0, @@ -150,6 +151,8 @@ int shmem_sg_alloc_table(struct drm_i915_private *i915, struct sg_table *st, } } while (1); + nr_pages = min_t(unsigned long, + folio_nr_pages(folio), page_count - i); if (!i || sg->length >= max_segment || folio_pfn(folio) != next_pfn) { @@ -157,13 +160,13 @@ int shmem_sg_alloc_table(struct drm_i915_private *i915, struct sg_table *st, sg = sg_next(sg); st->nents++; - sg_set_folio(sg, folio, folio_size(folio), 0); + sg_set_folio(sg, folio, nr_pages * PAGE_SIZE, 0); } else { /* XXX: could overflow? */ - sg->length += folio_size(folio); + sg->length += nr_pages * PAGE_SIZE; } - next_pfn = folio_pfn(folio) + folio_nr_pages(folio); - i += folio_nr_pages(folio) - 1; + next_pfn = folio_pfn(folio) + nr_pages; + i += nr_pages - 1; /* Check that the i965g/gm workaround works. */ GEM_BUG_ON(gfp & __GFP_DMA32 && next_pfn >= 0x00100000UL); diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index a4ff55aa5e55..7ad36198aab2 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -271,8 +271,17 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70)) bit_group_0 |= PIPE_CONTROL_CCS_FLUSH; + /* + * L3 fabric flush is needed for AUX CCS invalidation + * which happens as part of pipe-control so we can + * ignore PIPE_CONTROL_FLUSH_L3. Also PIPE_CONTROL_FLUSH_L3 + * deals with Protected Memory which is not needed for + * AUX CCS invalidation and lead to unwanted side effects. + */ + if (mode & EMIT_FLUSH) + bit_group_1 |= PIPE_CONTROL_FLUSH_L3; + bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH; - bit_group_1 |= PIPE_CONTROL_FLUSH_L3; bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; /* Wa_1409600907:tgl,adl-p */ diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index ee15486fed0d..e85d70a62123 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -558,7 +558,6 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id, DRIVER_CAPS(i915)->has_logical_contexts = true; ewma__engine_latency_init(&engine->latency); - seqcount_init(&engine->stats.execlists.lock); ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index e99a6fa03d45..a7e677598004 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -58,6 +58,7 @@ struct i915_perf_group; typedef u32 intel_engine_mask_t; #define ALL_ENGINES ((intel_engine_mask_t)~0ul) +#define VIRTUAL_ENGINES BIT(BITS_PER_TYPE(intel_engine_mask_t) - 1) struct intel_hw_status_page { struct list_head timelines; diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c index 8a641bcf777c..3292524469d5 100644 --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c @@ -3550,6 +3550,8 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine) logical_ring_default_vfuncs(engine); logical_ring_default_irqs(engine); + seqcount_init(&engine->stats.execlists.lock); + if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) rcs_submission_override(engine); diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index dd0ed941441a..da21f2786b5d 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -511,20 +511,31 @@ void intel_ggtt_unbind_vma(struct i915_address_space *vm, vm->clear_range(vm, vma_res->start, vma_res->vma_size); } +/* + * Reserve the top of the GuC address space for firmware images. Addresses + * beyond GUC_GGTT_TOP in the GuC address space are inaccessible by GuC, + * which makes for a suitable range to hold GuC/HuC firmware images if the + * size of the GGTT is 4G. However, on a 32-bit platform the size of the GGTT + * is limited to 2G, which is less than GUC_GGTT_TOP, but we reserve a chunk + * of the same size anyway, which is far more than needed, to keep the logic + * in uc_fw_ggtt_offset() simple. + */ +#define GUC_TOP_RESERVE_SIZE (SZ_4G - GUC_GGTT_TOP) + static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt) { - u64 size; + u64 offset; int ret; if (!intel_uc_uses_guc(&ggtt->vm.gt->uc)) return 0; - GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP); - size = ggtt->vm.total - GUC_GGTT_TOP; + GEM_BUG_ON(ggtt->vm.total <= GUC_TOP_RESERVE_SIZE); + offset = ggtt->vm.total - GUC_TOP_RESERVE_SIZE; - ret = i915_gem_gtt_reserve(&ggtt->vm, NULL, &ggtt->uc_fw, size, - GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE, - PIN_NOEVICT); + ret = i915_gem_gtt_reserve(&ggtt->vm, NULL, &ggtt->uc_fw, + GUC_TOP_RESERVE_SIZE, offset, + I915_COLOR_UNEVICTABLE, PIN_NOEVICT); if (ret) drm_dbg(&ggtt->vm.i915->drm, "Failed to reserve top of GGTT for GuC\n"); diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 957d0aeb0c02..c378cc7c953c 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1094,6 +1094,9 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine) I915_BO_ALLOC_PM_VOLATILE); if (IS_ERR(obj)) { obj = i915_gem_object_create_shmem(engine->i915, context_size); + if (IS_ERR(obj)) + return ERR_CAST(obj); + /* * Wa_22016122933: For Media version 13.0, all Media GT shared * memory needs to be mapped as WC on CPU side and UC (PAT @@ -1102,8 +1105,6 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine) if (intel_gt_needs_wa_22016122933(engine->gt)) i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE); } - if (IS_ERR(obj)) - return ERR_CAST(obj); vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); if (IS_ERR(vma)) { diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index a0e3ef1c65d2..dc7b40e06e38 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c @@ -1433,6 +1433,36 @@ static void guc_timestamp_ping(struct work_struct *wrk) int srcu, ret; /* + * Ideally the busyness worker should take a gt pm wakeref because the + * worker only needs to be active while gt is awake. However, the + * gt_park path cancels the worker synchronously and this complicates + * the flow if the worker is also running at the same time. The cancel + * waits for the worker and when the worker releases the wakeref, that + * would call gt_park and would lead to a deadlock. + * + * The resolution is to take the global pm wakeref if runtime pm is + * already active. If not, we don't need to update the busyness stats as + * the stats would already be updated when the gt was parked. + * + * Note: + * - We do not requeue the worker if we cannot take a reference to runtime + * pm since intel_guc_busyness_unpark would requeue the worker in the + * resume path. + * + * - If the gt was parked longer than time taken for GT timestamp to roll + * over, we ignore those rollovers since we don't care about tracking + * the exact GT time. We only care about roll overs when the gt is + * active and running workloads. + * + * - There is a window of time between gt_park and runtime suspend, + * where the worker may run. This is acceptable since the worker will + * not find any new data to update busyness. + */ + wakeref = intel_runtime_pm_get_if_active(>->i915->runtime_pm); + if (!wakeref) + return; + + /* * Synchronize with gt reset to make sure the worker does not * corrupt the engine/guc stats. NB: can't actually block waiting * for a reset to complete as the reset requires flushing out @@ -1440,10 +1470,9 @@ static void guc_timestamp_ping(struct work_struct *wrk) */ ret = intel_gt_reset_trylock(gt, &srcu); if (ret) - return; + goto err_trylock; - with_intel_runtime_pm(>->i915->runtime_pm, wakeref) - __update_guc_busyness_stats(guc); + __update_guc_busyness_stats(guc); /* adjust context stats for overflow */ xa_for_each(&guc->context_lookup, index, ce) @@ -1452,6 +1481,9 @@ static void guc_timestamp_ping(struct work_struct *wrk) intel_gt_reset_unlock(gt, srcu); guc_enable_busyness_worker(guc); + +err_trylock: + intel_runtime_pm_put(>->i915->runtime_pm, wakeref); } static int guc_action_enable_usage_stats(struct intel_guc *guc) @@ -5470,6 +5502,9 @@ guc_create_virtual(struct intel_engine_cs **siblings, unsigned int count, ve->base.flags = I915_ENGINE_IS_VIRTUAL; + BUILD_BUG_ON(ilog2(VIRTUAL_ENGINES) < I915_NUM_ENGINES); + ve->base.mask = VIRTUAL_ENGINES; + intel_context_init(&ve->context, &ve->base); for (n = 0; n < count; n++) { diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index 4ec85308379a..094fca9b0e73 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -49,22 +49,6 @@ static bool enable_out_of_sync = false; static int preallocated_oos_pages = 8192; -static bool intel_gvt_is_valid_gfn(struct intel_vgpu *vgpu, unsigned long gfn) -{ - struct kvm *kvm = vgpu->vfio_device.kvm; - int idx; - bool ret; - - if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status)) - return false; - - idx = srcu_read_lock(&kvm->srcu); - ret = kvm_is_visible_gfn(kvm, gfn); - srcu_read_unlock(&kvm->srcu, idx); - - return ret; -} - /* * validate a gm address and related range size, * translate it to host gm address @@ -1161,31 +1145,6 @@ static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se, ops->set_pfn(se, s->shadow_page.mfn); } -/* - * Check if can do 2M page - * @vgpu: target vgpu - * @entry: target pfn's gtt entry - * - * Return 1 if 2MB huge gtt shadowing is possible, 0 if miscondition, - * negative if found err. - */ -static int is_2MB_gtt_possible(struct intel_vgpu *vgpu, - struct intel_gvt_gtt_entry *entry) -{ - const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops; - kvm_pfn_t pfn; - - if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M)) - return 0; - - if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status)) - return -EINVAL; - pfn = gfn_to_pfn(vgpu->vfio_device.kvm, ops->get_pfn(entry)); - if (is_error_noslot_pfn(pfn)) - return -EINVAL; - return PageTransHuge(pfn_to_page(pfn)); -} - static int split_2MB_gtt_entry(struct intel_vgpu *vgpu, struct intel_vgpu_ppgtt_spt *spt, unsigned long index, struct intel_gvt_gtt_entry *se) @@ -1279,7 +1238,7 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu, { const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops; struct intel_gvt_gtt_entry se = *ge; - unsigned long gfn, page_size = PAGE_SIZE; + unsigned long gfn; dma_addr_t dma_addr; int ret; @@ -1291,6 +1250,9 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu, switch (ge->type) { case GTT_TYPE_PPGTT_PTE_4K_ENTRY: gvt_vdbg_mm("shadow 4K gtt entry\n"); + ret = intel_gvt_dma_map_guest_page(vgpu, gfn, PAGE_SIZE, &dma_addr); + if (ret) + return -ENXIO; break; case GTT_TYPE_PPGTT_PTE_64K_ENTRY: gvt_vdbg_mm("shadow 64K gtt entry\n"); @@ -1302,25 +1264,20 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu, return split_64KB_gtt_entry(vgpu, spt, index, &se); case GTT_TYPE_PPGTT_PTE_2M_ENTRY: gvt_vdbg_mm("shadow 2M gtt entry\n"); - ret = is_2MB_gtt_possible(vgpu, ge); - if (ret == 0) + if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M) || + intel_gvt_dma_map_guest_page(vgpu, gfn, + I915_GTT_PAGE_SIZE_2M, &dma_addr)) return split_2MB_gtt_entry(vgpu, spt, index, &se); - else if (ret < 0) - return ret; - page_size = I915_GTT_PAGE_SIZE_2M; break; case GTT_TYPE_PPGTT_PTE_1G_ENTRY: gvt_vgpu_err("GVT doesn't support 1GB entry\n"); return -EINVAL; default: GEM_BUG_ON(1); + return -EINVAL; } - /* direct shadow */ - ret = intel_gvt_dma_map_guest_page(vgpu, gfn, page_size, &dma_addr); - if (ret) - return -ENXIO; - + /* Successfully shadowed a 4K or 2M page (without splitting). */ pte_ops->set_pfn(&se, dma_addr >> PAGE_SHIFT); ppgtt_set_shadow_entry(spt, &se, index); return 0; @@ -1329,11 +1286,9 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu, static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt) { struct intel_vgpu *vgpu = spt->vgpu; - struct intel_gvt *gvt = vgpu->gvt; - const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops; struct intel_vgpu_ppgtt_spt *s; struct intel_gvt_gtt_entry se, ge; - unsigned long gfn, i; + unsigned long i; int ret; trace_spt_change(spt->vgpu->id, "born", spt, @@ -1350,13 +1305,6 @@ static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt) ppgtt_generate_shadow_entry(&se, s, &ge); ppgtt_set_shadow_entry(spt, &se, i); } else { - gfn = ops->get_pfn(&ge); - if (!intel_gvt_is_valid_gfn(vgpu, gfn)) { - ops->set_pfn(&se, gvt->gtt.scratch_mfn); - ppgtt_set_shadow_entry(spt, &se, i); - continue; - } - ret = ppgtt_populate_shadow_entry(vgpu, spt, i, &ge); if (ret) goto fail; @@ -1845,6 +1793,9 @@ static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm) if (mm->ppgtt_mm.shadowed) return 0; + if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status)) + return -EINVAL; + mm->ppgtt_mm.shadowed = true; for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.guest_pdps); index++) { @@ -2331,14 +2282,6 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off, m.val64 = e.val64; m.type = e.type; - /* one PTE update may be issued in multiple writes and the - * first write may not construct a valid gfn - */ - if (!intel_gvt_is_valid_gfn(vgpu, gfn)) { - ops->set_pfn(&m, gvt->gtt.scratch_mfn); - goto out; - } - ret = intel_gvt_dma_map_guest_page(vgpu, gfn, PAGE_SIZE, &dma_addr); if (ret) { @@ -2355,7 +2298,6 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off, ops->clear_present(&m); } -out: ggtt_set_guest_entry(ggtt_mm, &e, g_gtt_index); ggtt_get_host_entry(ggtt_mm, &e, g_gtt_index); @@ -2876,24 +2818,6 @@ void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old) } /** - * intel_vgpu_reset_gtt - reset the all GTT related status - * @vgpu: a vGPU - * - * This function is called from vfio core to reset reset all - * GTT related status, including GGTT, PPGTT, scratch page. - * - */ -void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu) -{ - /* Shadow pages are only created when there is no page - * table tracking data, so remove page tracking data after - * removing the shadow pages. - */ - intel_vgpu_destroy_all_ppgtt_mm(vgpu); - intel_vgpu_reset_ggtt(vgpu, true); -} - -/** * intel_gvt_restore_ggtt - restore all vGPU's ggtt entries * @gvt: intel gvt device * diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h index a3b0f59ec8bd..4cb183e06e95 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.h +++ b/drivers/gpu/drm/i915/gvt/gtt.h @@ -224,7 +224,6 @@ void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old); void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu); int intel_gvt_init_gtt(struct intel_gvt *gvt); -void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu); void intel_gvt_clean_gtt(struct intel_gvt *gvt); struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu, diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h index 2d65800d8e93..53a0a42a50db 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.h +++ b/drivers/gpu/drm/i915/gvt/gvt.h @@ -34,10 +34,11 @@ #define _GVT_H_ #include <uapi/linux/pci_regs.h> -#include <linux/kvm_host.h> #include <linux/vfio.h> #include <linux/mdev.h> +#include <asm/kvm_page_track.h> + #include "i915_drv.h" #include "intel_gvt.h" diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c index 9cd9e9da60dd..42ce20e72db7 100644 --- a/drivers/gpu/drm/i915/gvt/kvmgt.c +++ b/drivers/gpu/drm/i915/gvt/kvmgt.c @@ -106,12 +106,10 @@ struct gvt_dma { #define vfio_dev_to_vgpu(vfio_dev) \ container_of((vfio_dev), struct intel_vgpu, vfio_device) -static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, - const u8 *val, int len, - struct kvm_page_track_notifier_node *node); -static void kvmgt_page_track_flush_slot(struct kvm *kvm, - struct kvm_memory_slot *slot, - struct kvm_page_track_notifier_node *node); +static void kvmgt_page_track_write(gpa_t gpa, const u8 *val, int len, + struct kvm_page_track_notifier_node *node); +static void kvmgt_page_track_remove_region(gfn_t gfn, unsigned long nr_pages, + struct kvm_page_track_notifier_node *node); static ssize_t intel_vgpu_show_description(struct mdev_type *mtype, char *buf) { @@ -161,8 +159,7 @@ static int gvt_pin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, if (npage == 0) base_page = cur_page; - else if (base_page + npage != cur_page) { - gvt_vgpu_err("The pages are not continuous\n"); + else if (page_to_pfn(base_page) + npage != page_to_pfn(cur_page)) { ret = -EINVAL; npage++; goto err; @@ -172,7 +169,8 @@ static int gvt_pin_guest_page(struct intel_vgpu *vgpu, unsigned long gfn, *page = base_page; return 0; err: - gvt_unpin_guest_page(vgpu, gfn, npage * PAGE_SIZE); + if (npage) + gvt_unpin_guest_page(vgpu, gfn, npage * PAGE_SIZE); return ret; } @@ -352,6 +350,8 @@ __kvmgt_protect_table_find(struct intel_vgpu *info, gfn_t gfn) { struct kvmgt_pgfn *p, *res = NULL; + lockdep_assert_held(&info->vgpu_lock); + hash_for_each_possible(info->ptable, p, hnode, gfn) { if (gfn == p->gfn) { res = p; @@ -654,21 +654,19 @@ out: static int intel_vgpu_open_device(struct vfio_device *vfio_dev) { struct intel_vgpu *vgpu = vfio_dev_to_vgpu(vfio_dev); - - if (!vgpu->vfio_device.kvm || - vgpu->vfio_device.kvm->mm != current->mm) { - gvt_vgpu_err("KVM is required to use Intel vGPU\n"); - return -ESRCH; - } + int ret; if (__kvmgt_vgpu_exist(vgpu)) return -EEXIST; vgpu->track_node.track_write = kvmgt_page_track_write; - vgpu->track_node.track_flush_slot = kvmgt_page_track_flush_slot; - kvm_get_kvm(vgpu->vfio_device.kvm); - kvm_page_track_register_notifier(vgpu->vfio_device.kvm, - &vgpu->track_node); + vgpu->track_node.track_remove_region = kvmgt_page_track_remove_region; + ret = kvm_page_track_register_notifier(vgpu->vfio_device.kvm, + &vgpu->track_node); + if (ret) { + gvt_vgpu_err("KVM is required to use Intel vGPU\n"); + return ret; + } set_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status); @@ -703,7 +701,6 @@ static void intel_vgpu_close_device(struct vfio_device *vfio_dev) kvm_page_track_unregister_notifier(vgpu->vfio_device.kvm, &vgpu->track_node); - kvm_put_kvm(vgpu->vfio_device.kvm); kvmgt_protect_table_destroy(vgpu); gvt_cache_destroy(vgpu); @@ -1547,95 +1544,70 @@ static struct mdev_driver intel_vgpu_mdev_driver = { int intel_gvt_page_track_add(struct intel_vgpu *info, u64 gfn) { - struct kvm *kvm = info->vfio_device.kvm; - struct kvm_memory_slot *slot; - int idx; + int r; if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, info->status)) return -ESRCH; - idx = srcu_read_lock(&kvm->srcu); - slot = gfn_to_memslot(kvm, gfn); - if (!slot) { - srcu_read_unlock(&kvm->srcu, idx); - return -EINVAL; - } - - write_lock(&kvm->mmu_lock); - if (kvmgt_gfn_is_write_protected(info, gfn)) - goto out; + return 0; - kvm_slot_page_track_add_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE); - kvmgt_protect_table_add(info, gfn); + r = kvm_write_track_add_gfn(info->vfio_device.kvm, gfn); + if (r) + return r; -out: - write_unlock(&kvm->mmu_lock); - srcu_read_unlock(&kvm->srcu, idx); + kvmgt_protect_table_add(info, gfn); return 0; } int intel_gvt_page_track_remove(struct intel_vgpu *info, u64 gfn) { - struct kvm *kvm = info->vfio_device.kvm; - struct kvm_memory_slot *slot; - int idx; + int r; if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, info->status)) return -ESRCH; - idx = srcu_read_lock(&kvm->srcu); - slot = gfn_to_memslot(kvm, gfn); - if (!slot) { - srcu_read_unlock(&kvm->srcu, idx); - return -EINVAL; - } - - write_lock(&kvm->mmu_lock); - if (!kvmgt_gfn_is_write_protected(info, gfn)) - goto out; + return 0; - kvm_slot_page_track_remove_page(kvm, slot, gfn, KVM_PAGE_TRACK_WRITE); - kvmgt_protect_table_del(info, gfn); + r = kvm_write_track_remove_gfn(info->vfio_device.kvm, gfn); + if (r) + return r; -out: - write_unlock(&kvm->mmu_lock); - srcu_read_unlock(&kvm->srcu, idx); + kvmgt_protect_table_del(info, gfn); return 0; } -static void kvmgt_page_track_write(struct kvm_vcpu *vcpu, gpa_t gpa, - const u8 *val, int len, - struct kvm_page_track_notifier_node *node) +static void kvmgt_page_track_write(gpa_t gpa, const u8 *val, int len, + struct kvm_page_track_notifier_node *node) { struct intel_vgpu *info = container_of(node, struct intel_vgpu, track_node); - if (kvmgt_gfn_is_write_protected(info, gpa_to_gfn(gpa))) + mutex_lock(&info->vgpu_lock); + + if (kvmgt_gfn_is_write_protected(info, gpa >> PAGE_SHIFT)) intel_vgpu_page_track_handler(info, gpa, (void *)val, len); + + mutex_unlock(&info->vgpu_lock); } -static void kvmgt_page_track_flush_slot(struct kvm *kvm, - struct kvm_memory_slot *slot, - struct kvm_page_track_notifier_node *node) +static void kvmgt_page_track_remove_region(gfn_t gfn, unsigned long nr_pages, + struct kvm_page_track_notifier_node *node) { - int i; - gfn_t gfn; + unsigned long i; struct intel_vgpu *info = container_of(node, struct intel_vgpu, track_node); - write_lock(&kvm->mmu_lock); - for (i = 0; i < slot->npages; i++) { - gfn = slot->base_gfn + i; - if (kvmgt_gfn_is_write_protected(info, gfn)) { - kvm_slot_page_track_remove_page(kvm, slot, gfn, - KVM_PAGE_TRACK_WRITE); - kvmgt_protect_table_del(info, gfn); - } + mutex_lock(&info->vgpu_lock); + + for (i = 0; i < nr_pages; i++) { + if (kvmgt_gfn_is_write_protected(info, gfn + i)) + kvmgt_protect_table_del(info, gfn + i); } - write_unlock(&kvm->mmu_lock); + + mutex_unlock(&info->vgpu_lock); } void intel_vgpu_detach_regions(struct intel_vgpu *vgpu) diff --git a/drivers/gpu/drm/i915/gvt/page_track.c b/drivers/gpu/drm/i915/gvt/page_track.c index df34e73cba41..60a65435556d 100644 --- a/drivers/gpu/drm/i915/gvt/page_track.c +++ b/drivers/gpu/drm/i915/gvt/page_track.c @@ -162,13 +162,9 @@ int intel_vgpu_page_track_handler(struct intel_vgpu *vgpu, u64 gpa, struct intel_vgpu_page_track *page_track; int ret = 0; - mutex_lock(&vgpu->vgpu_lock); - page_track = intel_vgpu_find_page_track(vgpu, gpa >> PAGE_SHIFT); - if (!page_track) { - ret = -ENXIO; - goto out; - } + if (!page_track) + return -ENXIO; if (unlikely(vgpu->failsafe)) { /* Remove write protection to prevent furture traps. */ @@ -179,7 +175,5 @@ int intel_vgpu_page_track_handler(struct intel_vgpu *vgpu, u64 gpa, gvt_err("guest page write error, gpa %llx\n", gpa); } -out: - mutex_unlock(&vgpu->vgpu_lock); return ret; } diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 1f65bb33dd21..a8551ce322de 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1199,6 +1199,13 @@ int i915_gem_init(struct drm_i915_private *dev_priv) goto err_unlock; } + /* + * Register engines early to ensure the engine list is in its final + * rb-tree form, lowering the amount of code that has to deal with + * the intermediate llist state. + */ + intel_engines_driver_register(dev_priv); + return 0; /* @@ -1246,8 +1253,6 @@ err_unlock: void i915_gem_driver_register(struct drm_i915_private *i915) { i915_gem_driver_register__shrinker(i915); - - intel_engines_driver_register(i915); } void i915_gem_driver_unregister(struct drm_i915_private *i915) diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 7c7da284990d..f59081066a19 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -134,9 +134,7 @@ static void i915_fence_release(struct dma_fence *fence) i915_sw_fence_fini(&rq->semaphore); /* - * Keep one request on each engine for reserved use under mempressure - * do not use with virtual engines as this really is only needed for - * kernel contexts. + * Keep one request on each engine for reserved use under mempressure. * * We do not hold a reference to the engine here and so have to be * very careful in what rq->engine we poke. The virtual engine is @@ -166,8 +164,7 @@ static void i915_fence_release(struct dma_fence *fence) * know that if the rq->execution_mask is a single bit, rq->engine * can be a physical engine with the exact corresponding mask. */ - if (!intel_engine_is_virtual(rq->engine) && - is_power_of_2(rq->execution_mask) && + if (is_power_of_2(rq->execution_mask) && !cmpxchg(&rq->engine->request_pool, NULL, rq)) return; diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c index 9913971fa5d2..25ea76558690 100644 --- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c +++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c @@ -334,6 +334,8 @@ static void meson_encoder_hdmi_hpd_notify(struct drm_bridge *bridge, return; cec_notifier_set_phys_addr_from_edid(encoder_hdmi->cec_notifier, edid); + + kfree(edid); } else cec_notifier_phys_addr_invalidate(encoder_hdmi->cec_notifier); } diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index a34924523133..a34917b048f9 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -1122,18 +1122,11 @@ nv04_page_flip_emit(struct nouveau_channel *chan, PUSH_NVSQ(push, NV_SW, NV_SW_PAGE_FLIP, 0x00000000); PUSH_KICK(push); - ret = nouveau_fence_new(pfence); + ret = nouveau_fence_new(pfence, chan); if (ret) goto fail; - ret = nouveau_fence_emit(*pfence, chan); - if (ret) - goto fail_fence_unref; - return 0; - -fail_fence_unref: - nouveau_fence_unref(pfence); fail: spin_lock_irqsave(&dev->event_lock, flags); list_del(&s->head); diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index 30afbec9e3b1..2edd7bb13fae 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -31,6 +31,7 @@ #include "nouveau_drv.h" #include "nouveau_dma.h" +#include "nouveau_exec.h" #include "nouveau_gem.h" #include "nouveau_chan.h" #include "nouveau_abi16.h" @@ -183,6 +184,20 @@ nouveau_abi16_fini(struct nouveau_abi16 *abi16) cli->abi16 = NULL; } +static inline int +getparam_dma_ib_max(struct nvif_device *device) +{ + const struct nvif_mclass dmas[] = { + { NV03_CHANNEL_DMA, 0 }, + { NV10_CHANNEL_DMA, 0 }, + { NV17_CHANNEL_DMA, 0 }, + { NV40_CHANNEL_DMA, 0 }, + {} + }; + + return nvif_mclass(&device->object, dmas) < 0 ? NV50_DMA_IB_MAX : 0; +} + int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) { @@ -247,6 +262,12 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) case NOUVEAU_GETPARAM_GRAPH_UNITS: getparam->value = nvkm_gr_units(gr); break; + case NOUVEAU_GETPARAM_EXEC_PUSH_MAX: { + int ib_max = getparam_dma_ib_max(device); + + getparam->value = nouveau_exec_push_max_from_ib_max(ib_max); + break; + } default: NV_PRINTK(dbg, cli, "unknown parameter %lld\n", getparam->param); return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 19cab37ac69c..0f3bd187ede6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -875,16 +875,10 @@ nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, if (ret) goto out_unlock; - ret = nouveau_fence_new(&fence); + ret = nouveau_fence_new(&fence, chan); if (ret) goto out_unlock; - ret = nouveau_fence_emit(fence, chan); - if (ret) { - nouveau_fence_unref(&fence); - goto out_unlock; - } - /* TODO: figure out a better solution here * * wait on the fence here explicitly as going through diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index 1fd5ccf41128..7c97b2886807 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -70,11 +70,9 @@ nouveau_channel_idle(struct nouveau_channel *chan) struct nouveau_fence *fence = NULL; int ret; - ret = nouveau_fence_new(&fence); + ret = nouveau_fence_new(&fence, chan); if (!ret) { - ret = nouveau_fence_emit(fence, chan); - if (!ret) - ret = nouveau_fence_wait(fence, false, false); + ret = nouveau_fence_wait(fence, false, false); nouveau_fence_unref(&fence); } @@ -259,10 +257,7 @@ static int nouveau_channel_ctor(struct nouveau_drm *drm, struct nvif_device *device, bool priv, u64 runm, struct nouveau_channel **pchan) { - static const struct { - s32 oclass; - int version; - } hosts[] = { + const struct nvif_mclass hosts[] = { { AMPERE_CHANNEL_GPFIFO_B, 0 }, { AMPERE_CHANNEL_GPFIFO_A, 0 }, { TURING_CHANNEL_GPFIFO_A, 0 }, @@ -445,9 +440,11 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) } /* initialise dma tracking parameters */ - switch (chan->user.oclass & 0x00ff) { - case 0x006b: - case 0x006e: + switch (chan->user.oclass) { + case NV03_CHANNEL_DMA: + case NV10_CHANNEL_DMA: + case NV17_CHANNEL_DMA: + case NV40_CHANNEL_DMA: chan->user_put = 0x40; chan->user_get = 0x44; chan->dma.max = (0x10000 / 4) - 2; @@ -457,7 +454,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) chan->user_get = 0x44; chan->user_get_hi = 0x60; chan->dma.ib_base = 0x10000 / 4; - chan->dma.ib_max = (0x02000 / 8) - 1; + chan->dma.ib_max = NV50_DMA_IB_MAX; chan->dma.ib_put = 0; chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; chan->dma.max = chan->dma.ib_base; diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h index 1744d95b233e..c52cda82353e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.h +++ b/drivers/gpu/drm/nouveau/nouveau_dma.h @@ -49,6 +49,9 @@ void nv50_dma_push(struct nouveau_channel *, u64 addr, u32 length, /* Maximum push buffer size. */ #define NV50_DMA_PUSH_MAX_LENGTH 0x7fffff +/* Maximum IBs per ring. */ +#define NV50_DMA_IB_MAX ((0x02000 / 8) - 1) + /* Object handles - for stuff that's doesn't use handle == oclass. */ enum { NvDmaFB = 0x80000002, diff --git a/drivers/gpu/drm/nouveau/nouveau_dmem.c b/drivers/gpu/drm/nouveau/nouveau_dmem.c index 61e84562094a..12feecf71e75 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dmem.c +++ b/drivers/gpu/drm/nouveau/nouveau_dmem.c @@ -209,8 +209,7 @@ static vm_fault_t nouveau_dmem_migrate_to_ram(struct vm_fault *vmf) goto done; } - if (!nouveau_fence_new(&fence)) - nouveau_fence_emit(fence, dmem->migrate.chan); + nouveau_fence_new(&fence, dmem->migrate.chan); migrate_vma_pages(&args); nouveau_dmem_fence_done(&fence); dma_unmap_page(drm->dev->dev, dma_addr, PAGE_SIZE, DMA_BIDIRECTIONAL); @@ -403,8 +402,7 @@ nouveau_dmem_evict_chunk(struct nouveau_dmem_chunk *chunk) } } - if (!nouveau_fence_new(&fence)) - nouveau_fence_emit(fence, chunk->drm->dmem->migrate.chan); + nouveau_fence_new(&fence, chunk->drm->dmem->migrate.chan); migrate_device_pages(src_pfns, dst_pfns, npages); nouveau_dmem_fence_done(&fence); migrate_device_finalize(src_pfns, dst_pfns, npages); @@ -677,8 +675,7 @@ static void nouveau_dmem_migrate_chunk(struct nouveau_drm *drm, addr += PAGE_SIZE; } - if (!nouveau_fence_new(&fence)) - nouveau_fence_emit(fence, drm->dmem->migrate.chan); + nouveau_fence_new(&fence, drm->dmem->migrate.chan); migrate_vma_pages(args); nouveau_dmem_fence_done(&fence); nouveau_pfns_map(svmm, args->vma->vm_mm, args->start, pfns, i); diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 1fe17ff95f5e..e73a233c6572 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -189,21 +189,12 @@ u_free(void *addr) static inline void * u_memcpya(uint64_t user, unsigned int nmemb, unsigned int size) { - void *mem; - void __user *userptr = (void __force __user *)(uintptr_t)user; + void __user *userptr = u64_to_user_ptr(user); + size_t bytes; - size *= nmemb; - - mem = kvmalloc(size, GFP_KERNEL); - if (!mem) - return ERR_PTR(-ENOMEM); - - if (copy_from_user(mem, userptr, size)) { - u_free(mem); - return ERR_PTR(-EFAULT); - } - - return mem; + if (unlikely(check_mul_overflow(nmemb, size, &bytes))) + return ERR_PTR(-EOVERFLOW); + return vmemdup_user(userptr, bytes); } #include <nvif/object.h> diff --git a/drivers/gpu/drm/nouveau/nouveau_exec.c b/drivers/gpu/drm/nouveau/nouveau_exec.c index a90c4cd8cbb2..c1837ba95fb5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_exec.c +++ b/drivers/gpu/drm/nouveau/nouveau_exec.c @@ -96,7 +96,8 @@ nouveau_exec_job_submit(struct nouveau_job *job) unsigned long index; int ret; - ret = nouveau_fence_new(&exec_job->fence); + /* Create a new fence, but do not emit yet. */ + ret = nouveau_fence_create(&exec_job->fence, exec_job->chan); if (ret) return ret; @@ -170,13 +171,17 @@ nouveau_exec_job_run(struct nouveau_job *job) nv50_dma_push(chan, p->va, p->va_len, no_prefetch); } - ret = nouveau_fence_emit(fence, chan); + ret = nouveau_fence_emit(fence); if (ret) { + nouveau_fence_unref(&exec_job->fence); NV_PRINTK(err, job->cli, "error fencing pushbuf: %d\n", ret); WIND_RING(chan); return ERR_PTR(ret); } + /* The fence was emitted successfully, set the job's fence pointer to + * NULL in order to avoid freeing it up when the job is cleaned up. + */ exec_job->fence = NULL; return &fence->base; @@ -189,7 +194,7 @@ nouveau_exec_job_free(struct nouveau_job *job) nouveau_job_free(job); - nouveau_fence_unref(&exec_job->fence); + kfree(exec_job->fence); kfree(exec_job->push.s); kfree(exec_job); } @@ -208,7 +213,7 @@ nouveau_exec_job_timeout(struct nouveau_job *job) nouveau_sched_entity_fini(job->entity); - return DRM_GPU_SCHED_STAT_ENODEV; + return DRM_GPU_SCHED_STAT_NOMINAL; } static struct nouveau_job_ops nouveau_exec_job_ops = { @@ -374,7 +379,7 @@ nouveau_exec_ioctl_exec(struct drm_device *dev, struct nouveau_channel *chan = NULL; struct nouveau_exec_job_args args = {}; struct drm_nouveau_exec *req = data; - int ret = 0; + int push_max, ret = 0; if (unlikely(!abi16)) return -ENOMEM; @@ -399,9 +404,10 @@ nouveau_exec_ioctl_exec(struct drm_device *dev, if (!chan->dma.ib_max) return nouveau_abi16_put(abi16, -ENOSYS); - if (unlikely(req->push_count > NOUVEAU_GEM_MAX_PUSH)) { + push_max = nouveau_exec_push_max_from_ib_max(chan->dma.ib_max); + if (unlikely(req->push_count > push_max)) { NV_PRINTK(err, cli, "pushbuf push count exceeds limit: %d max %d\n", - req->push_count, NOUVEAU_GEM_MAX_PUSH); + req->push_count, push_max); return nouveau_abi16_put(abi16, -EINVAL); } diff --git a/drivers/gpu/drm/nouveau/nouveau_exec.h b/drivers/gpu/drm/nouveau/nouveau_exec.h index 778cacd90f65..5488d337bcc0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_exec.h +++ b/drivers/gpu/drm/nouveau/nouveau_exec.h @@ -51,4 +51,14 @@ int nouveau_exec_job_init(struct nouveau_exec_job **job, int nouveau_exec_ioctl_exec(struct drm_device *dev, void *data, struct drm_file *file_priv); +static inline unsigned int +nouveau_exec_push_max_from_ib_max(int ib_max) +{ + /* Limit the number of IBs per job to half the size of the ring in order + * to avoid the ring running dry between submissions and preserve one + * more slot for the job's HW fence. + */ + return ib_max > 1 ? ib_max / 2 - 1 : 0; +} + #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c index 77c739a55b19..ca762ea55413 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fence.c +++ b/drivers/gpu/drm/nouveau/nouveau_fence.c @@ -205,16 +205,13 @@ nouveau_fence_context_new(struct nouveau_channel *chan, struct nouveau_fence_cha } int -nouveau_fence_emit(struct nouveau_fence *fence, struct nouveau_channel *chan) +nouveau_fence_emit(struct nouveau_fence *fence) { + struct nouveau_channel *chan = unrcu_pointer(fence->channel); struct nouveau_fence_chan *fctx = chan->fence; struct nouveau_fence_priv *priv = (void*)chan->drm->fence; int ret; - if (unlikely(!chan->fence)) - return -ENODEV; - - fence->channel = chan; fence->timeout = jiffies + (15 * HZ); if (priv->uevent) @@ -406,18 +403,41 @@ nouveau_fence_unref(struct nouveau_fence **pfence) } int -nouveau_fence_new(struct nouveau_fence **pfence) +nouveau_fence_create(struct nouveau_fence **pfence, + struct nouveau_channel *chan) { struct nouveau_fence *fence; + if (unlikely(!chan->fence)) + return -ENODEV; + fence = kzalloc(sizeof(*fence), GFP_KERNEL); if (!fence) return -ENOMEM; + fence->channel = chan; + *pfence = fence; return 0; } +int +nouveau_fence_new(struct nouveau_fence **pfence, + struct nouveau_channel *chan) +{ + int ret = 0; + + ret = nouveau_fence_create(pfence, chan); + if (ret) + return ret; + + ret = nouveau_fence_emit(*pfence); + if (ret) + nouveau_fence_unref(pfence); + + return ret; +} + static const char *nouveau_fence_get_get_driver_name(struct dma_fence *fence) { return "nouveau"; diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.h b/drivers/gpu/drm/nouveau/nouveau_fence.h index 2c72d96ef17d..64d33ae7f356 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fence.h +++ b/drivers/gpu/drm/nouveau/nouveau_fence.h @@ -17,10 +17,11 @@ struct nouveau_fence { unsigned long timeout; }; -int nouveau_fence_new(struct nouveau_fence **); +int nouveau_fence_create(struct nouveau_fence **, struct nouveau_channel *); +int nouveau_fence_new(struct nouveau_fence **, struct nouveau_channel *); void nouveau_fence_unref(struct nouveau_fence **); -int nouveau_fence_emit(struct nouveau_fence *, struct nouveau_channel *); +int nouveau_fence_emit(struct nouveau_fence *); bool nouveau_fence_done(struct nouveau_fence *); int nouveau_fence_wait(struct nouveau_fence *, bool lazy, bool intr); int nouveau_fence_sync(struct nouveau_bo *, struct nouveau_channel *, bool exclusive, bool intr); diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index c0b10d8d3d03..a0d303e5ce3d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -914,11 +914,8 @@ revalidate: } } - ret = nouveau_fence_new(&fence); - if (!ret) - ret = nouveau_fence_emit(fence, chan); + ret = nouveau_fence_new(&fence, chan); if (ret) { - nouveau_fence_unref(&fence); NV_PRINTK(err, cli, "error fencing pushbuf: %d\n", ret); WIND_RING(chan); goto out; diff --git a/drivers/gpu/drm/nouveau/nouveau_sched.c b/drivers/gpu/drm/nouveau/nouveau_sched.c index 88217185e0f3..3b7ea5221226 100644 --- a/drivers/gpu/drm/nouveau/nouveau_sched.c +++ b/drivers/gpu/drm/nouveau/nouveau_sched.c @@ -375,14 +375,20 @@ nouveau_sched_run_job(struct drm_sched_job *sched_job) static enum drm_gpu_sched_stat nouveau_sched_timedout_job(struct drm_sched_job *sched_job) { + struct drm_gpu_scheduler *sched = sched_job->sched; struct nouveau_job *job = to_nouveau_job(sched_job); + enum drm_gpu_sched_stat stat = DRM_GPU_SCHED_STAT_NOMINAL; - NV_PRINTK(warn, job->cli, "Job timed out.\n"); + drm_sched_stop(sched, sched_job); if (job->ops->timeout) - return job->ops->timeout(job); + stat = job->ops->timeout(job); + else + NV_PRINTK(warn, job->cli, "Generic job timeout.\n"); + + drm_sched_start(sched, true); - return DRM_GPU_SCHED_STAT_ENODEV; + return stat; } static void diff --git a/drivers/gpu/drm/radeon/radeon_sa.c b/drivers/gpu/drm/radeon/radeon_sa.c index c87a57c9c592..22dd8b445685 100644 --- a/drivers/gpu/drm/radeon/radeon_sa.c +++ b/drivers/gpu/drm/radeon/radeon_sa.c @@ -123,7 +123,7 @@ int radeon_sa_bo_new(struct radeon_sa_manager *sa_manager, unsigned int size, unsigned int align) { struct drm_suballoc *sa = drm_suballoc_new(&sa_manager->base, size, - GFP_KERNEL, true, align); + GFP_KERNEL, false, align); if (IS_ERR(sa)) { *sa_bo = NULL; diff --git a/drivers/gpu/drm/tests/drm_kunit_helpers.c b/drivers/gpu/drm/tests/drm_kunit_helpers.c index c1dfbfcaa000..bccb33b900f3 100644 --- a/drivers/gpu/drm/tests/drm_kunit_helpers.c +++ b/drivers/gpu/drm/tests/drm_kunit_helpers.c @@ -118,7 +118,7 @@ void drm_kunit_helper_free_device(struct kunit *test, struct device *dev) kunit_release_action(test, kunit_action_platform_driver_unregister, - pdev); + &fake_platform_driver); } EXPORT_SYMBOL_GPL(drm_kunit_helper_free_device); diff --git a/drivers/gpu/drm/tests/drm_mm_test.c b/drivers/gpu/drm/tests/drm_mm_test.c index 186b28dc7038..05d5e7af6d25 100644 --- a/drivers/gpu/drm/tests/drm_mm_test.c +++ b/drivers/gpu/drm/tests/drm_mm_test.c @@ -939,7 +939,7 @@ static void drm_test_mm_insert_range(struct kunit *test) KUNIT_ASSERT_FALSE(test, __drm_test_mm_insert_range(test, count, size, 0, max - 1)); KUNIT_ASSERT_FALSE(test, __drm_test_mm_insert_range(test, count, size, 0, max / 2)); KUNIT_ASSERT_FALSE(test, __drm_test_mm_insert_range(test, count, size, - max / 2, max / 2)); + max / 2, max)); KUNIT_ASSERT_FALSE(test, __drm_test_mm_insert_range(test, count, size, max / 4 + 1, 3 * max / 4 - 1)); diff --git a/drivers/gpu/drm/tiny/gm12u320.c b/drivers/gpu/drm/tiny/gm12u320.c index c5bb683e440c..0187539ff5ea 100644 --- a/drivers/gpu/drm/tiny/gm12u320.c +++ b/drivers/gpu/drm/tiny/gm12u320.c @@ -70,10 +70,10 @@ MODULE_PARM_DESC(eco_mode, "Turn on Eco mode (less bright, more silent)"); #define READ_STATUS_SIZE 13 #define MISC_VALUE_SIZE 4 -#define CMD_TIMEOUT msecs_to_jiffies(200) -#define DATA_TIMEOUT msecs_to_jiffies(1000) -#define IDLE_TIMEOUT msecs_to_jiffies(2000) -#define FIRST_FRAME_TIMEOUT msecs_to_jiffies(2000) +#define CMD_TIMEOUT 200 +#define DATA_TIMEOUT 1000 +#define IDLE_TIMEOUT 2000 +#define FIRST_FRAME_TIMEOUT 2000 #define MISC_REQ_GET_SET_ECO_A 0xff #define MISC_REQ_GET_SET_ECO_B 0x35 @@ -389,7 +389,7 @@ static void gm12u320_fb_update_work(struct work_struct *work) * switches back to showing its logo. */ queue_delayed_work(system_long_wq, &gm12u320->fb_update.work, - IDLE_TIMEOUT); + msecs_to_jiffies(IDLE_TIMEOUT)); return; err: diff --git a/drivers/gpu/drm/virtio/virtgpu_submit.c b/drivers/gpu/drm/virtio/virtgpu_submit.c index 3c00135ead45..5c514946bbad 100644 --- a/drivers/gpu/drm/virtio/virtgpu_submit.c +++ b/drivers/gpu/drm/virtio/virtgpu_submit.c @@ -361,7 +361,6 @@ static void virtio_gpu_complete_submit(struct virtio_gpu_submit *submit) submit->buf = NULL; submit->buflist = NULL; submit->sync_file = NULL; - submit->out_fence = NULL; submit->out_fence_fd = -1; } diff --git a/drivers/gpu/drm/vkms/vkms_composer.c b/drivers/gpu/drm/vkms/vkms_composer.c index d5d4f642d367..3c99fb8b54e2 100644 --- a/drivers/gpu/drm/vkms/vkms_composer.c +++ b/drivers/gpu/drm/vkms/vkms_composer.c @@ -408,15 +408,10 @@ void vkms_set_composer(struct vkms_output *out, bool enabled) if (enabled) drm_crtc_vblank_get(&out->crtc); - mutex_lock(&out->enabled_lock); + spin_lock_irq(&out->lock); old_enabled = out->composer_enabled; out->composer_enabled = enabled; - - /* the composition wasn't enabled, so unlock the lock to make sure the lock - * will be balanced even if we have a failed commit - */ - if (!out->composer_enabled) - mutex_unlock(&out->enabled_lock); + spin_unlock_irq(&out->lock); if (old_enabled) drm_crtc_vblank_put(&out->crtc); diff --git a/drivers/gpu/drm/vkms/vkms_crtc.c b/drivers/gpu/drm/vkms/vkms_crtc.c index 3c5ebf106b66..61e500b8c9da 100644 --- a/drivers/gpu/drm/vkms/vkms_crtc.c +++ b/drivers/gpu/drm/vkms/vkms_crtc.c @@ -16,7 +16,7 @@ static enum hrtimer_restart vkms_vblank_simulate(struct hrtimer *timer) struct drm_crtc *crtc = &output->crtc; struct vkms_crtc_state *state; u64 ret_overrun; - bool ret, fence_cookie, composer_enabled; + bool ret, fence_cookie; fence_cookie = dma_fence_begin_signalling(); @@ -25,15 +25,15 @@ static enum hrtimer_restart vkms_vblank_simulate(struct hrtimer *timer) if (ret_overrun != 1) pr_warn("%s: vblank timer overrun\n", __func__); + spin_lock(&output->lock); ret = drm_crtc_handle_vblank(crtc); if (!ret) DRM_ERROR("vkms failure on handling vblank"); state = output->composer_state; - composer_enabled = output->composer_enabled; - mutex_unlock(&output->enabled_lock); + spin_unlock(&output->lock); - if (state && composer_enabled) { + if (state && output->composer_enabled) { u64 frame = drm_crtc_accurate_vblank_count(crtc); /* update frame_start only if a queued vkms_composer_worker() @@ -295,7 +295,6 @@ int vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, spin_lock_init(&vkms_out->lock); spin_lock_init(&vkms_out->composer_lock); - mutex_init(&vkms_out->enabled_lock); vkms_out->composer_workq = alloc_ordered_workqueue("vkms_composer", 0); if (!vkms_out->composer_workq) diff --git a/drivers/gpu/drm/vkms/vkms_drv.h b/drivers/gpu/drm/vkms/vkms_drv.h index c7ae6c2ba1df..8f5710debb1e 100644 --- a/drivers/gpu/drm/vkms/vkms_drv.h +++ b/drivers/gpu/drm/vkms/vkms_drv.h @@ -108,10 +108,8 @@ struct vkms_output { struct workqueue_struct *composer_workq; /* protects concurrent access to composer */ spinlock_t lock; - /* guarantees that if the composer is enabled, a job will be queued */ - struct mutex enabled_lock; - /* protected by @enabled_lock */ + /* protected by @lock */ bool composer_enabled; struct vkms_crtc_state *composer_state; |