diff options
Diffstat (limited to 'drivers/media/i2c/ccs-pll.h')
| -rw-r--r-- | drivers/media/i2c/ccs-pll.h | 86 |
1 files changed, 43 insertions, 43 deletions
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index b97d7ff50ea5..6eb1b1c68e1e 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -44,10 +44,10 @@ * @pll_op_clk_freq_hz: PLL output clock frequency */ struct ccs_pll_branch_fr { - uint16_t pre_pll_clk_div; - uint16_t pll_multiplier; - uint32_t pll_ip_clk_freq_hz; - uint32_t pll_op_clk_freq_hz; + u16 pre_pll_clk_div; + u16 pll_multiplier; + u32 pll_ip_clk_freq_hz; + u32 pll_op_clk_freq_hz; }; /** @@ -61,10 +61,10 @@ struct ccs_pll_branch_fr { * @pix_clk_freq_hz: Pixel clock frequency */ struct ccs_pll_branch_bk { - uint16_t sys_clk_div; - uint16_t pix_clk_div; - uint32_t sys_clk_freq_hz; - uint32_t pix_clk_freq_hz; + u16 sys_clk_div; + u16 pix_clk_div; + u32 sys_clk_freq_hz; + u32 pix_clk_freq_hz; }; /** @@ -97,21 +97,21 @@ struct ccs_pll_branch_bk { */ struct ccs_pll { /* input values */ - uint8_t bus_type; - uint8_t op_lanes; - uint8_t vt_lanes; + u8 bus_type; + u8 op_lanes; + u8 vt_lanes; struct { - uint8_t lanes; + u8 lanes; } csi2; - uint8_t binning_horizontal; - uint8_t binning_vertical; - uint8_t scale_m; - uint8_t scale_n; - uint8_t bits_per_pixel; - uint8_t op_bits_per_lane; - uint16_t flags; - uint32_t link_freq; - uint32_t ext_clk_freq_hz; + u8 binning_horizontal; + u8 binning_vertical; + u8 scale_m; + u8 scale_n; + u8 bits_per_pixel; + u8 op_bits_per_lane; + u16 flags; + u32 link_freq; + u32 ext_clk_freq_hz; /* output values */ struct ccs_pll_branch_fr vt_fr; @@ -119,8 +119,8 @@ struct ccs_pll { struct ccs_pll_branch_fr op_fr; struct ccs_pll_branch_bk op_bk; - uint32_t pixel_rate_csi; - uint32_t pixel_rate_pixel_array; + u32 pixel_rate_csi; + u32 pixel_rate_pixel_array; }; /** @@ -136,14 +136,14 @@ struct ccs_pll { * @max_pll_op_clk_freq_hz: Maximum PLL output clock frequency */ struct ccs_pll_branch_limits_fr { - uint16_t min_pre_pll_clk_div; - uint16_t max_pre_pll_clk_div; - uint32_t min_pll_ip_clk_freq_hz; - uint32_t max_pll_ip_clk_freq_hz; - uint16_t min_pll_multiplier; - uint16_t max_pll_multiplier; - uint32_t min_pll_op_clk_freq_hz; - uint32_t max_pll_op_clk_freq_hz; + u16 min_pre_pll_clk_div; + u16 max_pre_pll_clk_div; + u32 min_pll_ip_clk_freq_hz; + u32 max_pll_ip_clk_freq_hz; + u16 min_pll_multiplier; + u16 max_pll_multiplier; + u32 min_pll_op_clk_freq_hz; + u32 max_pll_op_clk_freq_hz; }; /** @@ -159,14 +159,14 @@ struct ccs_pll_branch_limits_fr { * @max_pix_clk_freq_hz: Maximum pixel clock frequency */ struct ccs_pll_branch_limits_bk { - uint16_t min_sys_clk_div; - uint16_t max_sys_clk_div; - uint32_t min_sys_clk_freq_hz; - uint32_t max_sys_clk_freq_hz; - uint16_t min_pix_clk_div; - uint16_t max_pix_clk_div; - uint32_t min_pix_clk_freq_hz; - uint32_t max_pix_clk_freq_hz; + u16 min_sys_clk_div; + u16 max_sys_clk_div; + u32 min_sys_clk_freq_hz; + u32 max_sys_clk_freq_hz; + u16 min_pix_clk_div; + u16 max_pix_clk_div; + u32 min_pix_clk_freq_hz; + u32 max_pix_clk_freq_hz; }; /** @@ -183,8 +183,8 @@ struct ccs_pll_branch_limits_bk { */ struct ccs_pll_limits { /* Strict PLL limits */ - uint32_t min_ext_clk_freq_hz; - uint32_t max_ext_clk_freq_hz; + u32 min_ext_clk_freq_hz; + u32 max_ext_clk_freq_hz; struct ccs_pll_branch_limits_fr vt_fr; struct ccs_pll_branch_limits_bk vt_bk; @@ -192,8 +192,8 @@ struct ccs_pll_limits { struct ccs_pll_branch_limits_bk op_bk; /* Other relevant limits */ - uint32_t min_line_length_pck_bin; - uint32_t min_line_length_pck; + u32 min_line_length_pck_bin; + u32 min_line_length_pck; }; struct device; |