diff options
Diffstat (limited to 'drivers/media/pci/cx18')
| -rw-r--r-- | drivers/media/pci/cx18/cx18-av-audio.c | 2 | ||||
| -rw-r--r-- | drivers/media/pci/cx18/cx18-av-core.c | 4 | ||||
| -rw-r--r-- | drivers/media/pci/cx18/cx18-firmware.c | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/drivers/media/pci/cx18/cx18-av-audio.c b/drivers/media/pci/cx18/cx18-av-audio.c index ee2b802d2895..833baa934448 100644 --- a/drivers/media/pci/cx18/cx18-av-audio.c +++ b/drivers/media/pci/cx18/cx18-av-audio.c @@ -46,7 +46,7 @@ static int set_audclk_freq(struct cx18 *cx, u32 freq) * an error of less than 0.13 ppm which is way, way better than any off * the shelf crystal will have for accuracy anyway. * - * Below I aim to run the PLLs' VCOs near 400 MHz to minimze error. + * Below I aim to run the PLLs' VCOs near 400 MHz to minimize error. * * Many thanks to Jeff Campbell and Mike Bradley for their extensive * investigation, experimentation, testing, and suggested solutions of diff --git a/drivers/media/pci/cx18/cx18-av-core.c b/drivers/media/pci/cx18/cx18-av-core.c index b33eb08631b1..11cfe35fd730 100644 --- a/drivers/media/pci/cx18/cx18-av-core.c +++ b/drivers/media/pci/cx18/cx18-av-core.c @@ -89,7 +89,7 @@ static void cx18_av_init(struct cx18 *cx) /* * The crystal freq used in calculations in this driver will be * 28.636360 MHz. - * Aim to run the PLLs' VCOs near 400 MHz to minimze errors. + * Aim to run the PLLs' VCOs near 400 MHz to minimize errors. */ /* @@ -122,7 +122,7 @@ static void cx18_av_initialize(struct v4l2_subdev *sd) cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000, 0x03000000, 0x13000000); - /* initallize the PLL by toggling sleep bit */ + /* initialize the PLL by toggling sleep bit */ v = cx18_av_read4(cx, CXADEC_HOST_REG1); /* enable sleep mode - register appears to be read only... */ cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe); diff --git a/drivers/media/pci/cx18/cx18-firmware.c b/drivers/media/pci/cx18/cx18-firmware.c index 876b96c11290..fdac310d7477 100644 --- a/drivers/media/pci/cx18/cx18-firmware.c +++ b/drivers/media/pci/cx18/cx18-firmware.c @@ -244,7 +244,7 @@ void cx18_init_power(struct cx18 *cx, int lowpwr) * an error of less than 0.13 ppm which is way, way better than any off * the shelf crystal will have for accuracy anyway. * - * Below I aim to run the PLLs' VCOs near 400 MHz to minimze errors. + * Below I aim to run the PLLs' VCOs near 400 MHz to minimize errors. * * Many thanks to Jeff Campbell and Mike Bradley for their extensive * investigation, experimentation, testing, and suggested solutions of |