diff options
Diffstat (limited to 'drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h')
-rw-r--r-- | drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h new file mode 100644 index 000000000000..2e4ff06e4858 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_tensor_0_regs.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_TENSOR_0_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_QM_TENSOR_0_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_QM_TENSOR_0 + * (Prototype: TPC_TENSOR) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0x400B5DC + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0x400B5E0 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_PADDING_VALUE 0x400B5E4 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG 0x400B5E8 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE 0x400B5EC + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE 0x400B5F0 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE 0x400B5F4 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE 0x400B5F8 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE 0x400B5FC + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE 0x400B600 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE 0x400B604 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE 0x400B608 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE 0x400B60C + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE 0x400B610 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_PREF_STRIDE 0x400B614 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH 0x400B618 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH 0x400B61C + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH 0x400B620 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH 0x400B624 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH 0x400B628 + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_QM_TENSOR_0_REGS_H_ */ |