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path: root/drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c
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Diffstat (limited to 'drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c')
-rw-r--r--drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c27
1 files changed, 13 insertions, 14 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c
index 0f0064392468..3cea9ee5910d 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum_ipip.c
@@ -181,21 +181,21 @@ mlxsw_sp_ipip_fib_entry_op_gre4_rtdp(struct mlxsw_sp *mlxsw_sp,
}
static int
-mlxsw_sp_ipip_fib_entry_op_gre4_ralue(struct mlxsw_sp *mlxsw_sp,
- struct mlxsw_sp_fib_entry_op_ctx *op_ctx,
- u32 dip, u8 prefix_len, u16 ul_vr_id,
- enum mlxsw_sp_fib_entry_op op,
- u32 tunnel_index)
+mlxsw_sp_ipip_fib_entry_op_gre4_do(struct mlxsw_sp *mlxsw_sp,
+ const struct mlxsw_sp_router_ll_ops *ll_ops,
+ struct mlxsw_sp_fib_entry_op_ctx *op_ctx,
+ u32 dip, u8 prefix_len, u16 ul_vr_id,
+ enum mlxsw_sp_fib_entry_op op,
+ u32 tunnel_index)
{
- char *ralue_pl = op_ctx->ralue_pl;
-
- mlxsw_sp_fib_entry_ralue_pack(ralue_pl, MLXSW_SP_L3_PROTO_IPV4, op,
- ul_vr_id, prefix_len, (unsigned char *) &dip);
- mlxsw_reg_ralue_act_ip2me_tun_pack(ralue_pl, tunnel_index);
- return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ralue), ralue_pl);
+ ll_ops->fib_entry_pack(op_ctx, MLXSW_SP_L3_PROTO_IPV4, op, ul_vr_id,
+ prefix_len, (unsigned char *) &dip);
+ ll_ops->fib_entry_act_ip2me_tun_pack(op_ctx, tunnel_index);
+ return ll_ops->fib_entry_commit(mlxsw_sp, op_ctx);
}
static int mlxsw_sp_ipip_fib_entry_op_gre4(struct mlxsw_sp *mlxsw_sp,
+ const struct mlxsw_sp_router_ll_ops *ll_ops,
struct mlxsw_sp_fib_entry_op_ctx *op_ctx,
struct mlxsw_sp_ipip_entry *ipip_entry,
enum mlxsw_sp_fib_entry_op op, u32 tunnel_index)
@@ -211,9 +211,8 @@ static int mlxsw_sp_ipip_fib_entry_op_gre4(struct mlxsw_sp *mlxsw_sp,
dip = mlxsw_sp_ipip_netdev_saddr(MLXSW_SP_L3_PROTO_IPV4,
ipip_entry->ol_dev).addr4;
- return mlxsw_sp_ipip_fib_entry_op_gre4_ralue(mlxsw_sp, op_ctx, be32_to_cpu(dip),
- 32, ul_vr_id, op,
- tunnel_index);
+ return mlxsw_sp_ipip_fib_entry_op_gre4_do(mlxsw_sp, ll_ops, op_ctx, be32_to_cpu(dip),
+ 32, ul_vr_id, op, tunnel_index);
}
static bool mlxsw_sp_ipip_tunnel_complete(enum mlxsw_sp_l3proto proto,