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-rw-r--r--drivers/net/ipa/Kconfig2
-rw-r--r--drivers/net/ipa/gsi.c38
-rw-r--r--drivers/net/ipa/gsi.h4
-rw-r--r--drivers/net/ipa/ipa_cmd.c76
-rw-r--r--drivers/net/ipa/ipa_data-sc7180.c41
-rw-r--r--drivers/net/ipa/ipa_data-sdm845.c34
-rw-r--r--drivers/net/ipa/ipa_data.h56
-rw-r--r--drivers/net/ipa/ipa_endpoint.c56
-rw-r--r--drivers/net/ipa/ipa_endpoint.h1
-rw-r--r--drivers/net/ipa/ipa_main.c108
-rw-r--r--drivers/net/ipa/ipa_mem.c6
-rw-r--r--drivers/net/ipa/ipa_mem.h10
-rw-r--r--drivers/net/ipa/ipa_qmi.c6
-rw-r--r--drivers/net/ipa/ipa_qmi_msg.c78
-rw-r--r--drivers/net/ipa/ipa_qmi_msg.h6
-rw-r--r--drivers/net/ipa/ipa_reg.h86
-rw-r--r--drivers/net/ipa/ipa_table.c42
-rw-r--r--drivers/net/ipa/ipa_table.h5
-rw-r--r--drivers/net/ipa/ipa_version.h29
19 files changed, 440 insertions, 244 deletions
diff --git a/drivers/net/ipa/Kconfig b/drivers/net/ipa/Kconfig
index b68f1289b89e..90a90262e0d0 100644
--- a/drivers/net/ipa/Kconfig
+++ b/drivers/net/ipa/Kconfig
@@ -1,6 +1,6 @@
config QCOM_IPA
tristate "Qualcomm IPA support"
- depends on 64BIT && NET && QCOM_SMEM
+ depends on NET && QCOM_SMEM
depends on ARCH_QCOM || COMPILE_TEST
depends on QCOM_RPROC_COMMON || (QCOM_RPROC_COMMON=n && COMPILE_TEST)
select QCOM_MDT_LOADER if ARCH_QCOM
diff --git a/drivers/net/ipa/gsi.c b/drivers/net/ipa/gsi.c
index 390d3403386a..7f2a8fce5e0d 100644
--- a/drivers/net/ipa/gsi.c
+++ b/drivers/net/ipa/gsi.c
@@ -351,7 +351,7 @@ void *gsi_ring_virt(struct gsi_ring *ring, u32 index)
/* Return the 32-bit DMA address associated with a ring index */
static u32 gsi_ring_addr(struct gsi_ring *ring, u32 index)
{
- return (ring->addr & GENMASK(31, 0)) + index * GSI_RING_ELEMENT_SIZE;
+ return lower_32_bits(ring->addr) + index * GSI_RING_ELEMENT_SIZE;
}
/* Return the ring index of a 32-bit ring offset */
@@ -708,10 +708,9 @@ static void gsi_evt_ring_program(struct gsi *gsi, u32 evt_ring_id)
* high-order 32 bits of the address of the event ring,
* respectively.
*/
- val = evt_ring->ring.addr & GENMASK(31, 0);
+ val = lower_32_bits(evt_ring->ring.addr);
iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_2_OFFSET(evt_ring_id));
-
- val = evt_ring->ring.addr >> 32;
+ val = upper_32_bits(evt_ring->ring.addr);
iowrite32(val, gsi->virt + GSI_EV_CH_E_CNTXT_3_OFFSET(evt_ring_id));
/* Enable interrupt moderation by setting the moderation delay */
@@ -816,10 +815,9 @@ static void gsi_channel_program(struct gsi_channel *channel, bool doorbell)
* high-order 32 bits of the address of the channel ring,
* respectively.
*/
- val = channel->tre_ring.addr & GENMASK(31, 0);
+ val = lower_32_bits(channel->tre_ring.addr);
iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_2_OFFSET(channel_id));
-
- val = channel->tre_ring.addr >> 32;
+ val = upper_32_bits(channel->tre_ring.addr);
iowrite32(val, gsi->virt + GSI_CH_C_CNTXT_3_OFFSET(channel_id));
/* Command channel gets low weighted round-robin priority */
@@ -829,14 +827,14 @@ static void gsi_channel_program(struct gsi_channel *channel, bool doorbell)
/* Max prefetch is 1 segment (do not set MAX_PREFETCH_FMASK) */
- /* We enable the doorbell engine for IPA v3.5.1 */
- if (gsi->version == IPA_VERSION_3_5_1 && doorbell)
+ /* No need to use the doorbell engine starting at IPA v4.0 */
+ if (gsi->version < IPA_VERSION_4_0 && doorbell)
val |= USE_DB_ENG_FMASK;
/* v4.0 introduces an escape buffer for prefetch. We use it
* on all but the AP command channel.
*/
- if (gsi->version != IPA_VERSION_3_5_1 && !channel->command) {
+ if (gsi->version >= IPA_VERSION_4_0 && !channel->command) {
/* If not otherwise set, prefetch buffers are used */
if (gsi->version < IPA_VERSION_4_5)
val |= USE_ESCAPE_BUF_ONLY_FMASK;
@@ -975,7 +973,7 @@ void gsi_channel_reset(struct gsi *gsi, u32 channel_id, bool doorbell)
gsi_channel_reset_command(channel);
/* Due to a hardware quirk we may need to reset RX channels twice. */
- if (gsi->version == IPA_VERSION_3_5_1 && !channel->toward_ipa)
+ if (gsi->version < IPA_VERSION_4_0 && !channel->toward_ipa)
gsi_channel_reset_command(channel);
gsi_channel_program(channel, doorbell);
@@ -1337,10 +1335,9 @@ static int gsi_irq_init(struct gsi *gsi, struct platform_device *pdev)
int ret;
ret = platform_get_irq_byname(pdev, "gsi");
- if (ret <= 0) {
- dev_err(dev, "DT error %d getting \"gsi\" IRQ property\n", ret);
+ if (ret <= 0)
return ret ? : -EINVAL;
- }
+
irq = ret;
ret = request_irq(irq, gsi_isr, 0, "gsi", gsi);
@@ -1366,7 +1363,7 @@ static struct gsi_trans *gsi_event_trans(struct gsi_channel *channel,
u32 tre_index;
/* Event xfer_ptr records the TRE it's associated with */
- tre_offset = le64_to_cpu(event->xfer_ptr) & GENMASK(31, 0);
+ tre_offset = lower_32_bits(le64_to_cpu(event->xfer_ptr));
tre_index = gsi_ring_index(&channel->tre_ring, tre_offset);
return gsi_channel_trans_mapped(channel, tre_index);
@@ -1439,15 +1436,18 @@ static void gsi_evt_ring_rx_update(struct gsi_evt_ring *evt_ring, u32 index)
/* Initialize a ring, including allocating DMA memory for its entries */
static int gsi_ring_alloc(struct gsi *gsi, struct gsi_ring *ring, u32 count)
{
- size_t size = count * GSI_RING_ELEMENT_SIZE;
+ u32 size = count * GSI_RING_ELEMENT_SIZE;
struct device *dev = gsi->dev;
dma_addr_t addr;
- /* Hardware requires a 2^n ring size, with alignment equal to size */
+ /* Hardware requires a 2^n ring size, with alignment equal to size.
+ * The size is a power of 2, so we can check alignment using just
+ * the bottom 32 bits for a DMA address of any size.
+ */
ring->virt = dma_alloc_coherent(dev, size, &addr, GFP_KERNEL);
- if (ring->virt && addr % size) {
+ if (ring->virt && lower_32_bits(addr) % size) {
dma_free_coherent(dev, size, ring->virt, addr);
- dev_err(dev, "unable to alloc 0x%zx-aligned ring buffer\n",
+ dev_err(dev, "unable to alloc 0x%x-aligned ring buffer\n",
size);
return -EINVAL; /* Not a good error value, but distinct */
} else if (!ring->virt) {
diff --git a/drivers/net/ipa/gsi.h b/drivers/net/ipa/gsi.h
index efc980f96109..d5996bdb20ef 100644
--- a/drivers/net/ipa/gsi.h
+++ b/drivers/net/ipa/gsi.h
@@ -16,8 +16,8 @@
#include "ipa_version.h"
/* Maximum number of channels and event rings supported by the driver */
-#define GSI_CHANNEL_COUNT_MAX 17
-#define GSI_EVT_RING_COUNT_MAX 13
+#define GSI_CHANNEL_COUNT_MAX 23
+#define GSI_EVT_RING_COUNT_MAX 20
/* Maximum TLV FIFO size for a channel; 64 here is arbitrary (and high) */
#define GSI_TLV_MAX 64
diff --git a/drivers/net/ipa/ipa_cmd.c b/drivers/net/ipa/ipa_cmd.c
index 35e35852c25c..2ac6dd8413de 100644
--- a/drivers/net/ipa/ipa_cmd.c
+++ b/drivers/net/ipa/ipa_cmd.c
@@ -71,13 +71,12 @@ struct ipa_cmd_hw_hdr_init_local {
/* IPA_CMD_REGISTER_WRITE */
-/* For IPA v4.0+, this opcode gets modified with pipeline clear options */
-
+/* For IPA v4.0+, the pipeline clear options are encoded in the opcode */
#define REGISTER_WRITE_OPCODE_SKIP_CLEAR_FMASK GENMASK(8, 8)
#define REGISTER_WRITE_OPCODE_CLEAR_OPTION_FMASK GENMASK(10, 9)
struct ipa_cmd_register_write {
- __le16 flags; /* Unused/reserved for IPA v3.5.1 */
+ __le16 flags; /* Unused/reserved prior to IPA v4.0 */
__le16 offset;
__le32 value;
__le32 value_mask;
@@ -85,12 +84,12 @@ struct ipa_cmd_register_write {
};
/* Field masks for ipa_cmd_register_write structure fields */
-/* The next field is present for IPA v4.0 and above */
+/* The next field is present for IPA v4.0+ */
#define REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK GENMASK(14, 11)
-/* The next field is present for IPA v3.5.1 only */
+/* The next field is not present for IPA v4.0+ */
#define REGISTER_WRITE_FLAGS_SKIP_CLEAR_FMASK GENMASK(15, 15)
-/* The next field and its values are present for IPA v3.5.1 only */
+/* The next field and its values are not present for IPA v4.0+ */
#define REGISTER_WRITE_CLEAR_OPTIONS_FMASK GENMASK(1, 0)
/* IPA_CMD_IP_PACKET_INIT */
@@ -123,7 +122,7 @@ struct ipa_cmd_hw_dma_mem_mem {
/* Field masks for ipa_cmd_hw_dma_mem_mem structure fields */
#define DMA_SHARED_MEM_FLAGS_DIRECTION_FMASK GENMASK(0, 0)
-/* The next two fields are present for IPA v3.5.1 only. */
+/* The next two fields are not present for IPA v4.0+ */
#define DMA_SHARED_MEM_FLAGS_SKIP_CLEAR_FMASK GENMASK(1, 1)
#define DMA_SHARED_MEM_FLAGS_CLEAR_OPTIONS_FMASK GENMASK(3, 2)
@@ -175,21 +174,23 @@ bool ipa_cmd_table_valid(struct ipa *ipa, const struct ipa_mem *mem,
: field_max(IP_FLTRT_FLAGS_NHASH_ADDR_FMASK);
if (mem->offset > offset_max ||
ipa->mem_offset > offset_max - mem->offset) {
- dev_err(dev, "IPv%c %s%s table region offset too large "
- "(0x%04x + 0x%04x > 0x%04x)\n",
- ipv6 ? '6' : '4', hashed ? "hashed " : "",
- route ? "route" : "filter",
- ipa->mem_offset, mem->offset, offset_max);
+ dev_err(dev, "IPv%c %s%s table region offset too large\n",
+ ipv6 ? '6' : '4', hashed ? "hashed " : "",
+ route ? "route" : "filter");
+ dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
+ ipa->mem_offset, mem->offset, offset_max);
+
return false;
}
if (mem->offset > ipa->mem_size ||
mem->size > ipa->mem_size - mem->offset) {
- dev_err(dev, "IPv%c %s%s table region out of range "
- "(0x%04x + 0x%04x > 0x%04x)\n",
- ipv6 ? '6' : '4', hashed ? "hashed " : "",
- route ? "route" : "filter",
- mem->offset, mem->size, ipa->mem_size);
+ dev_err(dev, "IPv%c %s%s table region out of range\n",
+ ipv6 ? '6' : '4', hashed ? "hashed " : "",
+ route ? "route" : "filter");
+ dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
+ mem->offset, mem->size, ipa->mem_size);
+
return false;
}
@@ -205,22 +206,36 @@ static bool ipa_cmd_header_valid(struct ipa *ipa)
u32 size_max;
u32 size;
+ /* In ipa_cmd_hdr_init_local_add() we record the offset and size
+ * of the header table memory area. Make sure the offset and size
+ * fit in the fields that need to hold them, and that the entire
+ * range is within the overall IPA memory range.
+ */
offset_max = field_max(HDR_INIT_LOCAL_FLAGS_HDR_ADDR_FMASK);
if (mem->offset > offset_max ||
ipa->mem_offset > offset_max - mem->offset) {
- dev_err(dev, "header table region offset too large "
- "(0x%04x + 0x%04x > 0x%04x)\n",
- ipa->mem_offset + mem->offset, offset_max);
+ dev_err(dev, "header table region offset too large\n");
+ dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
+ ipa->mem_offset, mem->offset, offset_max);
+
return false;
}
size_max = field_max(HDR_INIT_LOCAL_FLAGS_TABLE_SIZE_FMASK);
size = ipa->mem[IPA_MEM_MODEM_HEADER].size;
size += ipa->mem[IPA_MEM_AP_HEADER].size;
- if (mem->offset > ipa->mem_size || size > ipa->mem_size - mem->offset) {
- dev_err(dev, "header table region out of range "
- "(0x%04x + 0x%04x > 0x%04x)\n",
- mem->offset, size, ipa->mem_size);
+
+ if (size > size_max) {
+ dev_err(dev, "header table region size too large\n");
+ dev_err(dev, " (0x%04x > 0x%08x)\n", size, size_max);
+
+ return false;
+ }
+ if (size > ipa->mem_size || mem->offset > ipa->mem_size - size) {
+ dev_err(dev, "header table region out of range\n");
+ dev_err(dev, " (0x%04x + 0x%04x > 0x%04x)\n",
+ mem->offset, size, ipa->mem_size);
+
return false;
}
@@ -237,11 +252,12 @@ static bool ipa_cmd_register_write_offset_valid(struct ipa *ipa,
u32 bit_count;
/* The maximum offset in a register_write immediate command depends
- * on the version of IPA. IPA v3.5.1 supports a 16 bit offset, but
- * newer versions allow some additional high-order bits.
+ * on the version of IPA. A 16 bit offset is always supported,
+ * but starting with IPA v4.0 some additional high-order bits are
+ * allowed.
*/
bit_count = BITS_PER_BYTE * sizeof(payload->offset);
- if (ipa->version != IPA_VERSION_3_5_1)
+ if (ipa->version >= IPA_VERSION_4_0)
bit_count += hweight32(REGISTER_WRITE_FLAGS_OFFSET_HIGH_FMASK);
BUILD_BUG_ON(bit_count > 32);
offset_max = ~0U >> (32 - bit_count);
@@ -440,7 +456,11 @@ void ipa_cmd_register_write_add(struct gsi_trans *trans, u32 offset, u32 value,
/* pipeline_clear_src_grp is not used */
clear_option = clear_full ? pipeline_clear_full : pipeline_clear_hps;
- if (ipa->version != IPA_VERSION_3_5_1) {
+ /* IPA v4.0+ represents the pipeline clear options in the opcode. It
+ * also supports a larger offset by encoding additional high-order
+ * bits in the payload flags field.
+ */
+ if (ipa->version >= IPA_VERSION_4_0) {
u16 offset_high;
u32 val;
diff --git a/drivers/net/ipa/ipa_data-sc7180.c b/drivers/net/ipa/ipa_data-sc7180.c
index 997b51ceb7d7..621ad15c9e67 100644
--- a/drivers/net/ipa/ipa_data-sc7180.c
+++ b/drivers/net/ipa/ipa_data-sc7180.c
@@ -9,6 +9,15 @@
#include "ipa_endpoint.h"
#include "ipa_mem.h"
+/* QSB configuration for the SC7180 SoC. */
+static const struct ipa_qsb_data ipa_qsb_data[] = {
+ [IPA_QSB_MASTER_DDR] = {
+ .max_writes = 8,
+ .max_reads = 12,
+ /* no outstanding read byte (beat) limit */
+ },
+};
+
/* Endpoint configuration for the SC7180 SoC. */
static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
[IPA_ENDPOINT_AP_COMMAND_TX] = {
@@ -22,11 +31,13 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
.tlv_count = 20,
},
.endpoint = {
- .seq_type = IPA_SEQ_DMA_ONLY,
.config = {
.resource_group = 0,
.dma_mode = true,
.dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
+ .tx = {
+ .seq_type = IPA_SEQ_DMA,
+ },
},
},
},
@@ -41,7 +52,6 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
.tlv_count = 6,
},
.endpoint = {
- .seq_type = IPA_SEQ_INVALID,
.config = {
.resource_group = 0,
.aggregation = true,
@@ -64,14 +74,14 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
},
.endpoint = {
.filter_support = true,
- .seq_type =
- IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP,
.config = {
.resource_group = 0,
.checksum = true,
.qmap = true,
.status_enable = true,
.tx = {
+ .seq_type = IPA_SEQ_1_PASS_SKIP_LAST_UC,
+ .seq_rep_type = IPA_SEQ_REP_DMA_PARSER,
.status_endpoint =
IPA_ENDPOINT_MODEM_AP_RX,
},
@@ -89,7 +99,6 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
.tlv_count = 6,
},
.endpoint = {
- .seq_type = IPA_SEQ_INVALID,
.config = {
.resource_group = 0,
.checksum = true,
@@ -206,7 +215,7 @@ static const struct ipa_mem ipa_mem_local_data[] = {
[IPA_MEM_UC_INFO] = {
.offset = 0x0080,
.size = 0x0200,
- .canary_count = 2,
+ .canary_count = 0,
},
[IPA_MEM_V4_FILTER_HASHED] = {
.offset = 0x0288,
@@ -253,11 +262,6 @@ static const struct ipa_mem ipa_mem_local_data[] = {
.size = 0x0140,
.canary_count = 2,
},
- [IPA_MEM_AP_HEADER] = {
- .offset = 0x05e8,
- .size = 0x0000,
- .canary_count = 0,
- },
[IPA_MEM_MODEM_PROC_CTX] = {
.offset = 0x05f0,
.size = 0x0200,
@@ -273,7 +277,7 @@ static const struct ipa_mem ipa_mem_local_data[] = {
.size = 0x0050,
.canary_count = 2,
},
- [IPA_MEM_STATS_QUOTA] = {
+ [IPA_MEM_STATS_QUOTA_MODEM] = {
.offset = 0x0a50,
.size = 0x0060,
.canary_count = 2,
@@ -283,11 +287,6 @@ static const struct ipa_mem ipa_mem_local_data[] = {
.size = 0x0140,
.canary_count = 0,
},
- [IPA_MEM_STATS_DROP] = {
- .offset = 0x0bf0,
- .size = 0,
- .canary_count = 0,
- },
[IPA_MEM_MODEM] = {
.offset = 0x0bf0,
.size = 0x140c,
@@ -300,7 +299,7 @@ static const struct ipa_mem ipa_mem_local_data[] = {
},
};
-static struct ipa_mem_data ipa_mem_data = {
+static const struct ipa_mem_data ipa_mem_data = {
.local_count = ARRAY_SIZE(ipa_mem_local_data),
.local = ipa_mem_local_data,
.imem_addr = 0x146a8000,
@@ -310,7 +309,7 @@ static struct ipa_mem_data ipa_mem_data = {
};
/* Interconnect bandwidths are in 1000 byte/second units */
-static struct ipa_interconnect_data ipa_interconnect_data[] = {
+static const struct ipa_interconnect_data ipa_interconnect_data[] = {
{
.name = "memory",
.peak_bandwidth = 465000, /* 465 MBps */
@@ -329,7 +328,7 @@ static struct ipa_interconnect_data ipa_interconnect_data[] = {
},
};
-static struct ipa_clock_data ipa_clock_data = {
+static const struct ipa_clock_data ipa_clock_data = {
.core_clock_rate = 100 * 1000 * 1000, /* Hz */
.interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
.interconnect_data = ipa_interconnect_data,
@@ -338,6 +337,8 @@ static struct ipa_clock_data ipa_clock_data = {
/* Configuration data for the SC7180 SoC. */
const struct ipa_data ipa_data_sc7180 = {
.version = IPA_VERSION_4_2,
+ .qsb_count = ARRAY_SIZE(ipa_qsb_data),
+ .qsb_data = ipa_qsb_data,
.endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
.endpoint_data = ipa_gsi_endpoint_data,
.resource_data = &ipa_resource_data,
diff --git a/drivers/net/ipa/ipa_data-sdm845.c b/drivers/net/ipa/ipa_data-sdm845.c
index 88c9c3562ab7..6b5173f47444 100644
--- a/drivers/net/ipa/ipa_data-sdm845.c
+++ b/drivers/net/ipa/ipa_data-sdm845.c
@@ -11,6 +11,18 @@
#include "ipa_endpoint.h"
#include "ipa_mem.h"
+/* QSB configuration for the SDM845 SoC. */
+static const struct ipa_qsb_data ipa_qsb_data[] = {
+ [IPA_QSB_MASTER_DDR] = {
+ .max_writes = 8,
+ .max_reads = 8,
+ },
+ [IPA_QSB_MASTER_PCIE] = {
+ .max_writes = 4,
+ .max_reads = 12,
+ },
+};
+
/* Endpoint configuration for the SDM845 SoC. */
static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
[IPA_ENDPOINT_AP_COMMAND_TX] = {
@@ -24,11 +36,13 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
.tlv_count = 20,
},
.endpoint = {
- .seq_type = IPA_SEQ_DMA_ONLY,
.config = {
.resource_group = 1,
.dma_mode = true,
.dma_endpoint = IPA_ENDPOINT_AP_LAN_RX,
+ .tx = {
+ .seq_type = IPA_SEQ_DMA,
+ },
},
},
},
@@ -43,7 +57,6 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
.tlv_count = 8,
},
.endpoint = {
- .seq_type = IPA_SEQ_INVALID,
.config = {
.resource_group = 1,
.aggregation = true,
@@ -66,14 +79,13 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
},
.endpoint = {
.filter_support = true,
- .seq_type =
- IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,
.config = {
.resource_group = 1,
.checksum = true,
.qmap = true,
.status_enable = true,
.tx = {
+ .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC,
.status_endpoint =
IPA_ENDPOINT_MODEM_AP_RX,
},
@@ -91,7 +103,6 @@ static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = {
.tlv_count = 8,
},
.endpoint = {
- .seq_type = IPA_SEQ_INVALID,
.config = {
.resource_group = 1,
.checksum = true,
@@ -293,11 +304,6 @@ static const struct ipa_mem ipa_mem_local_data[] = {
.size = 0x0140,
.canary_count = 2,
},
- [IPA_MEM_AP_HEADER] = {
- .offset = 0x07c8,
- .size = 0x0000,
- .canary_count = 0,
- },
[IPA_MEM_MODEM_PROC_CTX] = {
.offset = 0x07d0,
.size = 0x0200,
@@ -320,7 +326,7 @@ static const struct ipa_mem ipa_mem_local_data[] = {
},
};
-static struct ipa_mem_data ipa_mem_data = {
+static const struct ipa_mem_data ipa_mem_data = {
.local_count = ARRAY_SIZE(ipa_mem_local_data),
.local = ipa_mem_local_data,
.imem_addr = 0x146bd000,
@@ -330,7 +336,7 @@ static struct ipa_mem_data ipa_mem_data = {
};
/* Interconnect bandwidths are in 1000 byte/second units */
-static struct ipa_interconnect_data ipa_interconnect_data[] = {
+static const struct ipa_interconnect_data ipa_interconnect_data[] = {
{
.name = "memory",
.peak_bandwidth = 600000, /* 600 MBps */
@@ -349,7 +355,7 @@ static struct ipa_interconnect_data ipa_interconnect_data[] = {
},
};
-static struct ipa_clock_data ipa_clock_data = {
+static const struct ipa_clock_data ipa_clock_data = {
.core_clock_rate = 75 * 1000 * 1000, /* Hz */
.interconnect_count = ARRAY_SIZE(ipa_interconnect_data),
.interconnect_data = ipa_interconnect_data,
@@ -358,6 +364,8 @@ static struct ipa_clock_data ipa_clock_data = {
/* Configuration data for the SDM845 SoC. */
const struct ipa_data ipa_data_sdm845 = {
.version = IPA_VERSION_3_5_1,
+ .qsb_count = ARRAY_SIZE(ipa_qsb_data),
+ .qsb_data = ipa_qsb_data,
.endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data),
.endpoint_data = ipa_gsi_endpoint_data,
.resource_data = &ipa_resource_data,
diff --git a/drivers/net/ipa/ipa_data.h b/drivers/net/ipa/ipa_data.h
index b476fc373f7f..7816583fc14a 100644
--- a/drivers/net/ipa/ipa_data.h
+++ b/drivers/net/ipa/ipa_data.h
@@ -18,8 +18,9 @@
* Boot-time configuration data is used to define the configuration of the
* IPA and GSI resources to use for a given platform. This data is supplied
* via the Device Tree match table, associated with a particular compatible
- * string. The data defines information about resources, endpoints, and
- * channels.
+ * string. The data defines information about how resources, endpoints and
+ * channels, memory, clocking and so on are allocated and used for the
+ * platform.
*
* Resources are data structures used internally by the IPA hardware. The
* configuration data defines the number (or limits of the number) of various
@@ -49,6 +50,24 @@
#define IPA_RESOURCE_GROUP_SRC_MAX 5
#define IPA_RESOURCE_GROUP_DST_MAX 5
+/** enum ipa_qsb_master_id - array index for IPA QSB configuration data */
+enum ipa_qsb_master_id {
+ IPA_QSB_MASTER_DDR,
+ IPA_QSB_MASTER_PCIE,
+};
+
+/**
+ * struct ipa_qsb_data - Qualcomm System Bus configuration data
+ * @max_writes: Maximum outstanding write requests for this master
+ * @max_reads: Maximum outstanding read requests for this master
+ * @max_reads_beats: Max outstanding read bytes in 8-byte "beats" (if non-zero)
+ */
+struct ipa_qsb_data {
+ u8 max_writes;
+ u8 max_reads;
+ u8 max_reads_beats; /* Not present for IPA v3.5.1 */
+};
+
/**
* struct gsi_channel_data - GSI channel configuration data
* @tre_count: number of TREs in the channel ring
@@ -57,10 +76,10 @@
*
* A GSI channel is a unidirectional means of transferring data to or
* from (and through) the IPA. A GSI channel has a ring buffer made
- * up of "transfer elements" (TREs) that specify individual data transfers
- * or IPA immediate commands. TREs are filled by the AP, and control
- * is passed to IPA hardware by writing the last written element
- * into a doorbell register.
+ * up of "transfer ring elements" (TREs) that specify individual data
+ * transfers or IPA immediate commands. TREs are filled by the AP,
+ * and control is passed to IPA hardware by writing the last written
+ * element into a doorbell register.
*
* When data transfer commands have completed the GSI generates an
* event (a structure of data) and optionally signals the AP with
@@ -79,12 +98,16 @@ struct gsi_channel_data {
/**
* struct ipa_endpoint_tx_data - configuration data for TX endpoints
+ * @seq_type: primary packet processing sequencer type
+ * @seq_rep_type: sequencer type for replication processing
* @status_endpoint: endpoint to which status elements are sent
*
* The @status_endpoint is only valid if the endpoint's @status_enable
* flag is set.
*/
struct ipa_endpoint_tx_data {
+ enum ipa_seq_type seq_type;
+ enum ipa_seq_rep_type seq_rep_type;
enum ipa_endpoint_name status_endpoint;
};
@@ -136,7 +159,6 @@ struct ipa_endpoint_config_data {
/**
* struct ipa_endpoint_data - IPA endpoint configuration data
* @filter_support: whether endpoint supports filtering
- * @seq_type: hardware sequencer type used for endpoint
* @config: hardware configuration (see above)
*
* Not all endpoints support the IPA filtering capability. A filter table
@@ -146,14 +168,10 @@ struct ipa_endpoint_config_data {
* in the system, and indicate whether they support filtering.
*
* The remaining endpoint configuration data applies only to AP endpoints.
- * The IPA hardware is implemented by sequencers, and the AP must program
- * the type(s) of these sequencers at initialization time. The remaining
- * endpoint configuration data is defined above.
*/
struct ipa_endpoint_data {
bool filter_support;
- /* The next two are specified only for AP endpoints */
- enum ipa_seq_type seq_type;
+ /* Everything else is specified only for AP endpoints */
struct ipa_endpoint_config_data config;
};
@@ -247,7 +265,7 @@ struct ipa_resource_data {
* @imem_addr: physical address of IPA region within IMEM
* @imem_size: size in bytes of IPA IMEM region
* @smem_id: item identifier for IPA region within SMEM memory
- * @imem_size: size in bytes of the IPA SMEM region
+ * @smem_size: size in bytes of the IPA SMEM region
*/
struct ipa_mem_data {
u32 local_count;
@@ -285,15 +303,19 @@ struct ipa_clock_data {
/**
* struct ipa_data - combined IPA/GSI configuration data
* @version: IPA hardware version
- * @endpoint_count: number of entries in endpoint_data array
+ * @qsb_count: number of entries in the qsb_data array
+ * @qsb_data: Qualcomm System Bus configuration data
+ * @endpoint_count: number of entries in the endpoint_data array
* @endpoint_data: IPA endpoint/GSI channel data
* @resource_data: IPA resource configuration data
- * @mem_count: number of entries in mem_data array
- * @mem_data: IPA-local shared memory region data
+ * @mem_data: IPA memory region data
+ * @clock_data: IPA clock and interconnect data
*/
struct ipa_data {
enum ipa_version version;
- u32 endpoint_count; /* # entries in endpoint_data[] */
+ u32 qsb_count; /* number of entries in qsb_data[] */
+ const struct ipa_qsb_data *qsb_data;
+ u32 endpoint_count; /* number of entries in endpoint_data[] */
const struct ipa_gsi_endpoint_data *endpoint_data;
const struct ipa_resource_data *resource_data;
const struct ipa_mem_data *mem_data;
diff --git a/drivers/net/ipa/ipa_endpoint.c b/drivers/net/ipa/ipa_endpoint.c
index 7209ee3c3124..38e83cd467b5 100644
--- a/drivers/net/ipa/ipa_endpoint.c
+++ b/drivers/net/ipa/ipa_endpoint.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
- * Copyright (C) 2019-2020 Linaro Ltd.
+ * Copyright (C) 2019-2021 Linaro Ltd.
*/
#include <linux/types.h>
@@ -266,7 +266,7 @@ ipa_endpoint_init_ctrl(struct ipa_endpoint *endpoint, bool suspend_delay)
* if (endpoint->toward_ipa)
* assert(ipa->version != IPA_VERSION_4.2);
* else
- * assert(ipa->version == IPA_VERSION_3_5_1);
+ * assert(ipa->version < IPA_VERSION_4_0);
*/
mask = endpoint->toward_ipa ? ENDP_DELAY_FMASK : ENDP_SUSPEND_FMASK;
@@ -347,7 +347,7 @@ ipa_endpoint_program_suspend(struct ipa_endpoint *endpoint, bool enable)
{
bool suspended;
- if (endpoint->ipa->version != IPA_VERSION_3_5_1)
+ if (endpoint->ipa->version >= IPA_VERSION_4_0)
return enable; /* For IPA v4.0+, no change made */
/* assert(!endpoint->toward_ipa); */
@@ -468,6 +468,20 @@ static void ipa_endpoint_init_cfg(struct ipa_endpoint *endpoint)
iowrite32(val, endpoint->ipa->reg_virt + offset);
}
+static void ipa_endpoint_init_nat(struct ipa_endpoint *endpoint)
+{
+ u32 offset;
+ u32 val;
+
+ if (!endpoint->toward_ipa)
+ return;
+
+ offset = IPA_REG_ENDP_INIT_NAT_N_OFFSET(endpoint->endpoint_id);
+ val = u32_encode_bits(IPA_NAT_BYPASS, NAT_EN_FMASK);
+
+ iowrite32(val, endpoint->ipa->reg_virt + offset);
+}
+
/**
* ipa_endpoint_init_hdr() - Initialize HDR endpoint configuration register
* @endpoint: Endpoint pointer
@@ -515,7 +529,7 @@ static void ipa_endpoint_init_hdr(struct ipa_endpoint *endpoint)
/* Where IPA will write the length */
offset = offsetof(struct rmnet_map_header, pkt_len);
/* Upper bits are stored in HDR_EXT with IPA v4.5 */
- if (version == IPA_VERSION_4_5)
+ if (version >= IPA_VERSION_4_5)
offset &= field_mask(HDR_OFST_PKT_SIZE_FMASK);
val |= HDR_OFST_PKT_SIZE_VALID_FMASK;
@@ -562,7 +576,7 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint)
/* IPA v4.5 adds some most-significant bits to a few fields,
* two of which are defined in the HDR (not HDR_EXT) register.
*/
- if (ipa->version == IPA_VERSION_4_5) {
+ if (ipa->version >= IPA_VERSION_4_5) {
/* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0, so MSB is 0 */
if (endpoint->data->qmap && !endpoint->toward_ipa) {
u32 offset;
@@ -776,7 +790,7 @@ static u32 hol_block_timer_val(struct ipa *ipa, u32 microseconds)
if (!microseconds)
return 0; /* Nothing to compute if timer period is 0 */
- if (ipa->version == IPA_VERSION_4_5)
+ if (ipa->version >= IPA_VERSION_4_5)
return hol_block_timer_qtime_val(ipa, microseconds);
/* Use 64 bit arithmetic to avoid overflow... */
@@ -884,18 +898,17 @@ static void ipa_endpoint_init_rsrc_grp(struct ipa_endpoint *endpoint)
static void ipa_endpoint_init_seq(struct ipa_endpoint *endpoint)
{
u32 offset = IPA_REG_ENDP_INIT_SEQ_N_OFFSET(endpoint->endpoint_id);
- u32 seq_type = endpoint->seq_type;
u32 val = 0;
if (!endpoint->toward_ipa)
return; /* Register not valid for RX endpoints */
- /* Sequencer type is made up of four nibbles */
- val |= u32_encode_bits(seq_type & 0xf, HPS_SEQ_TYPE_FMASK);
- val |= u32_encode_bits((seq_type >> 4) & 0xf, DPS_SEQ_TYPE_FMASK);
- /* The second two apply to replicated packets */
- val |= u32_encode_bits((seq_type >> 8) & 0xf, HPS_REP_SEQ_TYPE_FMASK);
- val |= u32_encode_bits((seq_type >> 12) & 0xf, DPS_REP_SEQ_TYPE_FMASK);
+ /* Low-order byte configures primary packet processing */
+ val |= u32_encode_bits(endpoint->data->tx.seq_type, SEQ_TYPE_FMASK);
+
+ /* Second byte configures replicated packet processing */
+ val |= u32_encode_bits(endpoint->data->tx.seq_rep_type,
+ SEQ_REP_TYPE_FMASK);
iowrite32(val, endpoint->ipa->reg_virt + offset);
}
@@ -1469,8 +1482,7 @@ static void ipa_endpoint_reset(struct ipa_endpoint *endpoint)
* is active, we need to handle things specially to recover.
* All other cases just need to reset the underlying GSI channel.
*/
- special = ipa->version == IPA_VERSION_3_5_1 &&
- !endpoint->toward_ipa &&
+ special = ipa->version < IPA_VERSION_4_0 && !endpoint->toward_ipa &&
endpoint->data->aggregation;
if (special && ipa_endpoint_aggr_active(endpoint))
ret = ipa_endpoint_reset_rx_aggr(endpoint);
@@ -1490,6 +1502,7 @@ static void ipa_endpoint_program(struct ipa_endpoint *endpoint)
else
(void)ipa_endpoint_program_suspend(endpoint, false);
ipa_endpoint_init_cfg(endpoint);
+ ipa_endpoint_init_nat(endpoint);
ipa_endpoint_init_hdr(endpoint);
ipa_endpoint_init_hdr_ext(endpoint);
ipa_endpoint_init_hdr_metadata_mask(endpoint);
@@ -1568,8 +1581,10 @@ void ipa_endpoint_suspend_one(struct ipa_endpoint *endpoint)
(void)ipa_endpoint_program_suspend(endpoint, true);
}
- /* IPA v3.5.1 doesn't use channel stop for suspend */
- stop_channel = endpoint->ipa->version != IPA_VERSION_3_5_1;
+ /* Starting with IPA v4.0, endpoints are suspended by stopping the
+ * underlying GSI channel rather than using endpoint suspend mode.
+ */
+ stop_channel = endpoint->ipa->version >= IPA_VERSION_4_0;
ret = gsi_channel_suspend(gsi, endpoint->channel_id, stop_channel);
if (ret)
dev_err(dev, "error %d suspending channel %u\n", ret,
@@ -1589,8 +1604,10 @@ void ipa_endpoint_resume_one(struct ipa_endpoint *endpoint)
if (!endpoint->toward_ipa)
(void)ipa_endpoint_program_suspend(endpoint, false);
- /* IPA v3.5.1 doesn't use channel start for resume */
- start_channel = endpoint->ipa->version != IPA_VERSION_3_5_1;
+ /* Starting with IPA v4.0, the underlying GSI channel must be
+ * restarted for resume.
+ */
+ start_channel = endpoint->ipa->version >= IPA_VERSION_4_0;
ret = gsi_channel_resume(gsi, endpoint->channel_id, start_channel);
if (ret)
dev_err(dev, "error %d resuming channel %u\n", ret,
@@ -1766,7 +1783,6 @@ static void ipa_endpoint_init_one(struct ipa *ipa, enum ipa_endpoint_name name,
endpoint->ipa = ipa;
endpoint->ee_id = data->ee_id;
- endpoint->seq_type = data->endpoint.seq_type;
endpoint->channel_id = data->channel_id;
endpoint->endpoint_id = data->endpoint_id;
endpoint->toward_ipa = data->toward_ipa;
diff --git a/drivers/net/ipa/ipa_endpoint.h b/drivers/net/ipa/ipa_endpoint.h
index 881ecc27bd6e..c6c55ea35394 100644
--- a/drivers/net/ipa/ipa_endpoint.h
+++ b/drivers/net/ipa/ipa_endpoint.h
@@ -46,7 +46,6 @@ enum ipa_endpoint_name {
*/
struct ipa_endpoint {
struct ipa *ipa;
- enum ipa_seq_type seq_type;
enum gsi_ee_id ee_id;
u32 channel_id;
u32 endpoint_id;
diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c
index 97c1b55405cb..ba1bfc30210a 100644
--- a/drivers/net/ipa/ipa_main.c
+++ b/drivers/net/ipa/ipa_main.c
@@ -227,8 +227,8 @@ static void ipa_hardware_config_comp(struct ipa *ipa)
{
u32 val;
- /* Nothing to configure for IPA v3.5.1 */
- if (ipa->version == IPA_VERSION_3_5_1)
+ /* Nothing to configure prior to IPA v4.0 */
+ if (ipa->version < IPA_VERSION_4_0)
return;
val = ioread32(ipa->reg_virt + IPA_REG_COMP_CFG_OFFSET);
@@ -249,56 +249,59 @@ static void ipa_hardware_config_comp(struct ipa *ipa)
iowrite32(val, ipa->reg_virt + IPA_REG_COMP_CFG_OFFSET);
}
-/* Configure DDR and PCIe max read/write QSB values */
-static void ipa_hardware_config_qsb(struct ipa *ipa)
+/* Configure DDR and (possibly) PCIe max read/write QSB values */
+static void
+ipa_hardware_config_qsb(struct ipa *ipa, const struct ipa_data *data)
{
- enum ipa_version version = ipa->version;
- u32 max0;
- u32 max1;
+ const struct ipa_qsb_data *data0;
+ const struct ipa_qsb_data *data1;
u32 val;
- /* QMB_0 represents DDR; QMB_1 represents PCIe */
- val = u32_encode_bits(8, GEN_QMB_0_MAX_WRITES_FMASK);
- switch (version) {
- case IPA_VERSION_4_2:
- max1 = 0; /* PCIe not present */
- break;
- case IPA_VERSION_4_5:
- max1 = 8;
- break;
- default:
- max1 = 4;
- break;
- }
- val |= u32_encode_bits(max1, GEN_QMB_1_MAX_WRITES_FMASK);
+ /* assert(data->qsb_count > 0); */
+ /* assert(data->qsb_count < 3); */
+
+ /* QMB 0 represents DDR; QMB 1 (if present) represents PCIe */
+ data0 = &data->qsb_data[IPA_QSB_MASTER_DDR];
+ if (data->qsb_count > 1)
+ data1 = &data->qsb_data[IPA_QSB_MASTER_PCIE];
+
+ /* Max outstanding write accesses for QSB masters */
+ val = u32_encode_bits(data0->max_writes, GEN_QMB_0_MAX_WRITES_FMASK);
+ if (data->qsb_count > 1)
+ val |= u32_encode_bits(data1->max_writes,
+ GEN_QMB_1_MAX_WRITES_FMASK);
iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_WRITES_OFFSET);
- max1 = 12;
- switch (version) {
- case IPA_VERSION_3_5_1:
- max0 = 8;
- break;
- case IPA_VERSION_4_0:
- case IPA_VERSION_4_1:
- max0 = 12;
- break;
- case IPA_VERSION_4_2:
- max0 = 12;
- max1 = 0; /* PCIe not present */
- break;
- case IPA_VERSION_4_5:
- max0 = 0; /* No limit (hardware maximum) */
- break;
- }
- val = u32_encode_bits(max0, GEN_QMB_0_MAX_READS_FMASK);
- val |= u32_encode_bits(max1, GEN_QMB_1_MAX_READS_FMASK);
- if (version != IPA_VERSION_3_5_1) {
- /* GEN_QMB_0_MAX_READS_BEATS is 0 */
- /* GEN_QMB_1_MAX_READS_BEATS is 0 */
+ /* Max outstanding read accesses for QSB masters */
+ val = u32_encode_bits(data0->max_reads, GEN_QMB_0_MAX_READS_FMASK);
+ if (ipa->version >= IPA_VERSION_4_0)
+ val |= u32_encode_bits(data0->max_reads_beats,
+ GEN_QMB_0_MAX_READS_BEATS_FMASK);
+ if (data->qsb_count > 1) {
+ val |= u32_encode_bits(data1->max_reads,
+ GEN_QMB_1_MAX_READS_FMASK);
+ if (ipa->version >= IPA_VERSION_4_0)
+ val |= u32_encode_bits(data1->max_reads_beats,
+ GEN_QMB_1_MAX_READS_BEATS_FMASK);
}
iowrite32(val, ipa->reg_virt + IPA_REG_QSB_MAX_READS_OFFSET);
}
+/* The internal inactivity timer clock is used for the aggregation timer */
+#define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */
+
+/* Compute the value to use in the COUNTER_CFG register AGGR_GRANULARITY
+ * field to represent the given number of microseconds. The value is one
+ * less than the number of timer ticks in the requested period. 0 is not
+ * a valid granularity value.
+ */
+static u32 ipa_aggr_granularity_val(u32 usec)
+{
+ /* assert(usec != 0); */
+
+ return DIV_ROUND_CLOSEST(usec * TIMER_FREQUENCY, USEC_PER_SEC) - 1;
+}
+
/* IPA uses unified Qtime starting at IPA v4.5, implementing various
* timestamps and timers independent of the IPA core clock rate. The
* Qtimer is based on a 56-bit timestamp incremented at each tick of
@@ -385,8 +388,9 @@ static void ipa_hardware_dcd_deconfig(struct ipa *ipa)
/**
* ipa_hardware_config() - Primitive hardware initialization
* @ipa: IPA pointer
+ * @data: IPA configuration data
*/
-static void ipa_hardware_config(struct ipa *ipa)
+static void ipa_hardware_config(struct ipa *ipa, const struct ipa_data *data)
{
enum ipa_version version = ipa->version;
u32 granularity;
@@ -399,7 +403,7 @@ static void ipa_hardware_config(struct ipa *ipa)
}
/* Implement some hardware workarounds */
- if (version != IPA_VERSION_3_5_1 && version < IPA_VERSION_4_5) {
+ if (version >= IPA_VERSION_4_0 && version < IPA_VERSION_4_5) {
/* Enable open global clocks (not needed for IPA v4.5) */
val = GLOBAL_FMASK;
val |= GLOBAL_2X_CLK_FMASK;
@@ -414,7 +418,7 @@ static void ipa_hardware_config(struct ipa *ipa)
ipa_hardware_config_comp(ipa);
/* Configure system bus limits */
- ipa_hardware_config_qsb(ipa);
+ ipa_hardware_config_qsb(ipa, data);
if (version < IPA_VERSION_4_5) {
/* Configure aggregation timer granularity */
@@ -610,7 +614,7 @@ static int ipa_config(struct ipa *ipa, const struct ipa_data *data)
*/
ipa_clock_get(ipa);
- ipa_hardware_config(ipa);
+ ipa_hardware_config(ipa, data);
ret = ipa_endpoint_config(ipa);
if (ret)
@@ -735,8 +739,14 @@ MODULE_DEVICE_TABLE(of, ipa_match);
static void ipa_validate_build(void)
{
#ifdef IPA_VALIDATE
- /* We assume we're working on 64-bit hardware */
- BUILD_BUG_ON(!IS_ENABLED(CONFIG_64BIT));
+ /* At one time we assumed a 64-bit build, allowing some do_div()
+ * calls to be replaced by simple division or modulo operations.
+ * We currently only perform divide and modulo operations on u32,
+ * u16, or size_t objects, and of those only size_t has any chance
+ * of being a 64-bit value. (It should be guaranteed 32 bits wide
+ * on a 32-bit build, but there is no harm in verifying that.)
+ */
+ BUILD_BUG_ON(!IS_ENABLED(CONFIG_64BIT) && sizeof(size_t) != 4);
/* Code assumes the EE ID for the AP is 0 (zeroed structure field) */
BUILD_BUG_ON(GSI_EE_AP != 0);
diff --git a/drivers/net/ipa/ipa_mem.c b/drivers/net/ipa/ipa_mem.c
index f25029b9ec85..32907dde5dc6 100644
--- a/drivers/net/ipa/ipa_mem.c
+++ b/drivers/net/ipa/ipa_mem.c
@@ -61,6 +61,7 @@ int ipa_mem_setup(struct ipa *ipa)
struct gsi_trans *trans;
u32 offset;
u16 size;
+ u32 val;
/* Get a transaction to define the header memory region and to zero
* the processing context and modem memory regions.
@@ -89,8 +90,9 @@ int ipa_mem_setup(struct ipa *ipa)
gsi_trans_commit_wait(trans);
/* Tell the hardware where the processing context area is located */
- iowrite32(ipa->mem_offset + ipa->mem[IPA_MEM_MODEM_PROC_CTX].offset,
- ipa->reg_virt + IPA_REG_LOCAL_PKT_PROC_CNTXT_BASE_OFFSET);
+ offset = ipa->mem_offset + ipa->mem[IPA_MEM_MODEM_PROC_CTX].offset;
+ val = proc_cntxt_base_addr_encoded(ipa->version, offset);
+ iowrite32(val, ipa->reg_virt + IPA_REG_LOCAL_PKT_PROC_CNTXT_OFFSET);
return 0;
}
diff --git a/drivers/net/ipa/ipa_mem.h b/drivers/net/ipa/ipa_mem.h
index f99180f84f0d..f82e8939622b 100644
--- a/drivers/net/ipa/ipa_mem.h
+++ b/drivers/net/ipa/ipa_mem.h
@@ -28,6 +28,7 @@ struct ipa_mem_data;
* The set of memory regions is defined in configuration data. They are
* subject to these constraints:
* - a zero offset and zero size represents and undefined region
+ * - a region's size does not include space for its "canary" values
* - a region's offset is defined to be *past* all "canary" values
* - offset must be large enough to account for all canaries
* - a region's size may be zero, but may still have canaries
@@ -56,9 +57,16 @@ enum ipa_mem_id {
IPA_MEM_AP_HEADER, /* 0 canaries */
IPA_MEM_MODEM_PROC_CTX, /* 2 canaries */
IPA_MEM_AP_PROC_CTX, /* 0 canaries */
+ IPA_MEM_NAT_TABLE, /* 4 canaries (IPA v4.5 and above) */
IPA_MEM_PDN_CONFIG, /* 2 canaries (IPA v4.0 and above) */
- IPA_MEM_STATS_QUOTA, /* 2 canaries (IPA v4.0 and above) */
+ IPA_MEM_STATS_QUOTA_MODEM, /* 2 canaries (IPA v4.0 and above) */
+ IPA_MEM_STATS_QUOTA_AP, /* 0 canaries (IPA v4.0 and above) */
IPA_MEM_STATS_TETHERING, /* 0 canaries (IPA v4.0 and above) */
+ IPA_MEM_STATS_V4_FILTER, /* 0 canaries (IPA v4.0-v4.2) */
+ IPA_MEM_STATS_V6_FILTER, /* 0 canaries (IPA v4.0-v4.2) */
+ IPA_MEM_STATS_V4_ROUTE, /* 0 canaries (IPA v4.0-v4.2) */
+ IPA_MEM_STATS_V6_ROUTE, /* 0 canaries (IPA v4.0-v4.2) */
+ IPA_MEM_STATS_FILTER_ROUTE, /* 0 canaries (IPA v4.5 and above) */
IPA_MEM_STATS_DROP, /* 0 canaries (IPA v4.0 and above) */
IPA_MEM_MODEM, /* 0 canaries */
IPA_MEM_UC_EVENT_RING, /* 1 canary */
diff --git a/drivers/net/ipa/ipa_qmi.c b/drivers/net/ipa/ipa_qmi.c
index 2fc64483f275..ccdb4a6a4c75 100644
--- a/drivers/net/ipa/ipa_qmi.c
+++ b/drivers/net/ipa/ipa_qmi.c
@@ -249,6 +249,7 @@ static const struct qmi_msg_handler ipa_server_msg_handlers[] = {
.decoded_size = IPA_QMI_DRIVER_INIT_COMPLETE_REQ_SZ,
.fn = ipa_server_driver_init_complete,
},
+ { },
};
/* Handle an INIT_DRIVER response message from the modem. */
@@ -269,6 +270,7 @@ static const struct qmi_msg_handler ipa_client_msg_handlers[] = {
.decoded_size = IPA_QMI_INIT_DRIVER_RSP_SZ,
.fn = ipa_client_init_driver,
},
+ { },
};
/* Return a pointer to an init modem driver request structure, which contains
@@ -377,8 +379,8 @@ init_modem_driver_req(struct ipa_qmi *ipa_qmi)
/* None of the stats fields are valid (IPA v4.0 and above) */
- if (ipa->version != IPA_VERSION_3_5_1) {
- mem = &ipa->mem[IPA_MEM_STATS_QUOTA];
+ if (ipa->version >= IPA_VERSION_4_0) {
+ mem = &ipa->mem[IPA_MEM_STATS_QUOTA_MODEM];
if (mem->size) {
req.hw_stats_quota_base_addr_valid = 1;
req.hw_stats_quota_base_addr =
diff --git a/drivers/net/ipa/ipa_qmi_msg.c b/drivers/net/ipa/ipa_qmi_msg.c
index 73413371e3d3..6838e8065072 100644
--- a/drivers/net/ipa/ipa_qmi_msg.c
+++ b/drivers/net/ipa/ipa_qmi_msg.c
@@ -56,7 +56,7 @@ struct qmi_elem_info ipa_indication_register_req_ei[] = {
.elem_size =
sizeof_field(struct ipa_indication_register_req,
ipa_mhi_ready_ind_valid),
- .tlv_type = 0x11,
+ .tlv_type = 0x12,
.offset = offsetof(struct ipa_indication_register_req,
ipa_mhi_ready_ind_valid),
},
@@ -66,11 +66,51 @@ struct qmi_elem_info ipa_indication_register_req_ei[] = {
.elem_size =
sizeof_field(struct ipa_indication_register_req,
ipa_mhi_ready_ind),
- .tlv_type = 0x11,
+ .tlv_type = 0x12,
.offset = offsetof(struct ipa_indication_register_req,
ipa_mhi_ready_ind),
},
{
+ .data_type = QMI_OPT_FLAG,
+ .elem_len = 1,
+ .elem_size =
+ sizeof_field(struct ipa_indication_register_req,
+ endpoint_desc_ind_valid),
+ .tlv_type = 0x13,
+ .offset = offsetof(struct ipa_indication_register_req,
+ endpoint_desc_ind_valid),
+ },
+ {
+ .data_type = QMI_UNSIGNED_1_BYTE,
+ .elem_len = 1,
+ .elem_size =
+ sizeof_field(struct ipa_indication_register_req,
+ endpoint_desc_ind),
+ .tlv_type = 0x13,
+ .offset = offsetof(struct ipa_indication_register_req,
+ endpoint_desc_ind),
+ },
+ {
+ .data_type = QMI_OPT_FLAG,
+ .elem_len = 1,
+ .elem_size =
+ sizeof_field(struct ipa_indication_register_req,
+ bw_change_ind_valid),
+ .tlv_type = 0x14,
+ .offset = offsetof(struct ipa_indication_register_req,
+ bw_change_ind_valid),
+ },
+ {
+ .data_type = QMI_UNSIGNED_1_BYTE,
+ .elem_len = 1,
+ .elem_size =
+ sizeof_field(struct ipa_indication_register_req,
+ bw_change_ind),
+ .tlv_type = 0x14,
+ .offset = offsetof(struct ipa_indication_register_req,
+ bw_change_ind),
+ },
+ {
.data_type = QMI_EOTI,
},
};
@@ -530,7 +570,7 @@ struct qmi_elem_info ipa_init_modem_driver_req_ei[] = {
hw_stats_quota_base_addr_valid),
},
{
- .data_type = QMI_SIGNED_4_BYTE_ENUM,
+ .data_type = QMI_UNSIGNED_4_BYTE,
.elem_len = 1,
.elem_size =
sizeof_field(struct ipa_init_modem_driver_req,
@@ -545,17 +585,17 @@ struct qmi_elem_info ipa_init_modem_driver_req_ei[] = {
.elem_size =
sizeof_field(struct ipa_init_modem_driver_req,
hw_stats_quota_size_valid),
- .tlv_type = 0x1f,
+ .tlv_type = 0x20,
.offset = offsetof(struct ipa_init_modem_driver_req,
hw_stats_quota_size_valid),
},
{
- .data_type = QMI_SIGNED_4_BYTE_ENUM,
+ .data_type = QMI_UNSIGNED_4_BYTE,
.elem_len = 1,
.elem_size =
sizeof_field(struct ipa_init_modem_driver_req,
hw_stats_quota_size),
- .tlv_type = 0x1f,
+ .tlv_type = 0x20,
.offset = offsetof(struct ipa_init_modem_driver_req,
hw_stats_quota_size),
},
@@ -564,18 +604,38 @@ struct qmi_elem_info ipa_init_modem_driver_req_ei[] = {
.elem_len = 1,
.elem_size =
sizeof_field(struct ipa_init_modem_driver_req,
+ hw_stats_drop_base_addr_valid),
+ .tlv_type = 0x21,
+ .offset = offsetof(struct ipa_init_modem_driver_req,
+ hw_stats_drop_base_addr_valid),
+ },
+ {
+ .data_type = QMI_UNSIGNED_4_BYTE,
+ .elem_len = 1,
+ .elem_size =
+ sizeof_field(struct ipa_init_modem_driver_req,
+ hw_stats_drop_base_addr),
+ .tlv_type = 0x21,
+ .offset = offsetof(struct ipa_init_modem_driver_req,
+ hw_stats_drop_base_addr),
+ },
+ {
+ .data_type = QMI_OPT_FLAG,
+ .elem_len = 1,
+ .elem_size =
+ sizeof_field(struct ipa_init_modem_driver_req,
hw_stats_drop_size_valid),
- .tlv_type = 0x1f,
+ .tlv_type = 0x22,
.offset = offsetof(struct ipa_init_modem_driver_req,
hw_stats_drop_size_valid),
},
{
- .data_type = QMI_SIGNED_4_BYTE_ENUM,
+ .data_type = QMI_UNSIGNED_4_BYTE,
.elem_len = 1,
.elem_size =
sizeof_field(struct ipa_init_modem_driver_req,
hw_stats_drop_size),
- .tlv_type = 0x1f,
+ .tlv_type = 0x22,
.offset = offsetof(struct ipa_init_modem_driver_req,
hw_stats_drop_size),
},
diff --git a/drivers/net/ipa/ipa_qmi_msg.h b/drivers/net/ipa/ipa_qmi_msg.h
index 12b6621f4b0e..3233d145fd87 100644
--- a/drivers/net/ipa/ipa_qmi_msg.h
+++ b/drivers/net/ipa/ipa_qmi_msg.h
@@ -24,7 +24,7 @@
* information for each field. The qmi_send_*() interfaces require
* the message size to be provided.
*/
-#define IPA_QMI_INDICATION_REGISTER_REQ_SZ 12 /* -> server handle */
+#define IPA_QMI_INDICATION_REGISTER_REQ_SZ 20 /* -> server handle */
#define IPA_QMI_INDICATION_REGISTER_RSP_SZ 7 /* <- server handle */
#define IPA_QMI_INIT_DRIVER_REQ_SZ 162 /* client handle -> */
#define IPA_QMI_INIT_DRIVER_RSP_SZ 25 /* client handle <- */
@@ -44,6 +44,10 @@ struct ipa_indication_register_req {
u8 data_usage_quota_reached;
u8 ipa_mhi_ready_ind_valid;
u8 ipa_mhi_ready_ind;
+ u8 endpoint_desc_ind_valid;
+ u8 endpoint_desc_ind;
+ u8 bw_change_ind_valid;
+ u8 bw_change_ind;
};
/* The response to a IPA_QMI_INDICATION_REGISTER request consists only of
diff --git a/drivers/net/ipa/ipa_reg.h b/drivers/net/ipa/ipa_reg.h
index 732e691e9aa6..86fe2978e810 100644
--- a/drivers/net/ipa/ipa_reg.h
+++ b/drivers/net/ipa/ipa_reg.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
- * Copyright (C) 2018-2020 Linaro Ltd.
+ * Copyright (C) 2018-2021 Linaro Ltd.
*/
#ifndef _IPA_REG_H_
#define _IPA_REG_H_
@@ -217,8 +217,18 @@ static inline u32 ipa_reg_bcr_val(enum ipa_version version)
return 0x00000000;
}
-/* The value of the next register must be a multiple of 8 */
-#define IPA_REG_LOCAL_PKT_PROC_CNTXT_BASE_OFFSET 0x000001e8
+/* The value of the next register must be a multiple of 8 (bottom 3 bits 0) */
+#define IPA_REG_LOCAL_PKT_PROC_CNTXT_OFFSET 0x000001e8
+
+/* Encoded value for LOCAL_PKT_PROC_CNTXT register BASE_ADDR field */
+static inline u32 proc_cntxt_base_addr_encoded(enum ipa_version version,
+ u32 addr)
+{
+ if (version < IPA_VERSION_4_5)
+ return u32_encode_bits(addr, GENMASK(16, 0));
+
+ return u32_encode_bits(addr, GENMASK(17, 0));
+}
/* ipa->available defines the valid bits in the AGGR_FORCE_CLOSE register */
#define IPA_REG_AGGR_FORCE_CLOSE_OFFSET 0x000001ec
@@ -227,18 +237,6 @@ static inline u32 ipa_reg_bcr_val(enum ipa_version version)
#define IPA_REG_COUNTER_CFG_OFFSET 0x000001f0
#define AGGR_GRANULARITY_FMASK GENMASK(8, 4)
-/* The internal inactivity timer clock is used for the aggregation timer */
-#define TIMER_FREQUENCY 32000 /* 32 KHz inactivity timer clock */
-
-/* Compute the value to use in the AGGR_GRANULARITY field representing the
- * given number of microseconds. The value is one less than the number of
- * timer ticks in the requested period. 0 not a valid granularity value.
- */
-static inline u32 ipa_aggr_granularity_val(u32 usec)
-{
- return DIV_ROUND_CLOSEST(usec * TIMER_FREQUENCY, USEC_PER_SEC) - 1;
-}
-
/* The next register is not present for IPA v4.5 */
#define IPA_REG_TX_CFG_OFFSET 0x000001fc
/* The first three fields are present for IPA v3.5.1 only */
@@ -388,6 +386,18 @@ enum ipa_cs_offload_en {
IPA_CS_OFFLOAD_DL = 0x2,
};
+/* Valid only for TX (IPA consumer) endpoints */
+#define IPA_REG_ENDP_INIT_NAT_N_OFFSET(ep) \
+ (0x0000080c + 0x0070 * (ep))
+#define NAT_EN_FMASK GENMASK(1, 0)
+
+/** enum ipa_nat_en - ENDP_INIT_NAT register NAT_EN field value */
+enum ipa_nat_en {
+ IPA_NAT_BYPASS = 0x0,
+ IPA_NAT_SRC = 0x1,
+ IPA_NAT_DST = 0x2,
+};
+
#define IPA_REG_ENDP_INIT_HDR_N_OFFSET(ep) \
(0x00000810 + 0x0070 * (ep))
#define HDR_LEN_FMASK GENMASK(5, 0)
@@ -580,28 +590,40 @@ static inline u32 rsrc_grp_encoded(enum ipa_version version, u32 rsrc_grp)
/* Valid only for TX (IPA consumer) endpoints */
#define IPA_REG_ENDP_INIT_SEQ_N_OFFSET(txep) \
(0x0000083c + 0x0070 * (txep))
-#define HPS_SEQ_TYPE_FMASK GENMASK(3, 0)
-#define DPS_SEQ_TYPE_FMASK GENMASK(7, 4)
-#define HPS_REP_SEQ_TYPE_FMASK GENMASK(11, 8)
-#define DPS_REP_SEQ_TYPE_FMASK GENMASK(15, 12)
+#define SEQ_TYPE_FMASK GENMASK(7, 0)
+#define SEQ_REP_TYPE_FMASK GENMASK(15, 8)
/**
- * enum ipa_seq_type - HPS and DPS sequencer type fields in ENDP_INIT_SEQ_N
- * @IPA_SEQ_DMA_ONLY: only DMA is performed
- * @IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP:
- * second packet processing pass + no decipher + microcontroller
- * @IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP:
- * packet processing + no decipher + no uCP + HPS REP DMA parser
- * @IPA_SEQ_INVALID: invalid sequencer type
+ * enum ipa_seq_type - HPS and DPS sequencer type
+ *
+ * The low-order byte of the sequencer type register defines the number of
+ * passes a packet takes through the IPA pipeline. The last pass through can
+ * optionally skip the microprocessor. Deciphering is optional for all types;
+ * if enabled, an additional mask (two bits) is added to the type value.
*
- * The values defined here are broken into 4-bit nibbles that are written
- * into fields of the ENDP_INIT_SEQ registers.
+ * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are
+ * supported (or meaningful).
*/
+#define IPA_SEQ_DECIPHER 0x11
enum ipa_seq_type {
- IPA_SEQ_DMA_ONLY = 0x0000,
- IPA_SEQ_2ND_PKT_PROCESS_PASS_NO_DEC_UCP = 0x0004,
- IPA_SEQ_PKT_PROCESS_NO_DEC_NO_UCP_DMAP = 0x0806,
- IPA_SEQ_INVALID = 0xffff,
+ IPA_SEQ_DMA = 0x00,
+ IPA_SEQ_1_PASS = 0x02,
+ IPA_SEQ_2_PASS_SKIP_LAST_UC = 0x04,
+ IPA_SEQ_1_PASS_SKIP_LAST_UC = 0x06,
+ IPA_SEQ_2_PASS = 0x0a,
+ IPA_SEQ_3_PASS_SKIP_LAST_UC = 0x0c,
+};
+
+/**
+ * enum ipa_seq_rep_type - replicated packet sequencer type
+ *
+ * This goes in the second byte of the endpoint sequencer type register.
+ *
+ * Note: not all combinations of ipa_seq_type and ipa_seq_rep_type are
+ * supported (or meaningful).
+ */
+enum ipa_seq_rep_type {
+ IPA_SEQ_REP_DMA_PARSER = 0x08,
};
#define IPA_REG_ENDP_STATUS_N_OFFSET(ep) \
diff --git a/drivers/net/ipa/ipa_table.c b/drivers/net/ipa/ipa_table.c
index baaab3dd0e63..4236a50ff03a 100644
--- a/drivers/net/ipa/ipa_table.c
+++ b/drivers/net/ipa/ipa_table.c
@@ -118,21 +118,15 @@
/* Check things that can be validated at build time. */
static void ipa_table_validate_build(void)
{
- /* IPA hardware accesses memory 128 bytes at a time. Addresses
- * referred to by entries in filter and route tables must be
- * aligned on 128-byte byte boundaries. The only rule address
- * ever use is the "zero rule", and it's aligned at the base
- * of a coherent DMA allocation.
+ /* Filter and route tables contain DMA addresses that refer
+ * to filter or route rules. But the size of a table entry
+ * is 64 bits regardless of what the size of an AP DMA address
+ * is. A fixed constant defines the size of an entry, and
+ * code in ipa_table_init() uses a pointer to __le64 to
+ * initialize tables.
*/
- BUILD_BUG_ON(ARCH_DMA_MINALIGN % IPA_TABLE_ALIGN);
-
- /* Filter and route tables contain DMA addresses that refer to
- * filter or route rules. We use a fixed constant to represent
- * the size of either type of table entry. Code in ipa_table_init()
- * uses a pointer to __le64 to initialize table entriews.
- */
- BUILD_BUG_ON(IPA_TABLE_ENTRY_SIZE != sizeof(dma_addr_t));
- BUILD_BUG_ON(sizeof(dma_addr_t) != sizeof(__le64));
+ BUILD_BUG_ON(sizeof(dma_addr_t) > IPA_TABLE_ENTRY_SIZE);
+ BUILD_BUG_ON(sizeof(__le64) != IPA_TABLE_ENTRY_SIZE);
/* A "zero rule" is used to represent no filtering or no routing.
* It is a 64-bit block of zeroed memory. Code in ipa_table_init()
@@ -239,11 +233,6 @@ static void ipa_table_validate_build(void)
#endif /* !IPA_VALIDATE */
-bool ipa_table_hash_support(struct ipa *ipa)
-{
- return ipa->version != IPA_VERSION_4_2;
-}
-
/* Zero entry count means no table, so just return a 0 address */
static dma_addr_t ipa_table_addr(struct ipa *ipa, bool filter_mask, u16 count)
{
@@ -668,6 +657,21 @@ int ipa_table_init(struct ipa *ipa)
if (!virt)
return -ENOMEM;
+ /* We put the "zero rule" at the base of our table area. The IPA
+ * hardware requires route and filter table rules to be aligned
+ * on a 128-byte boundary. As long as the alignment constraint
+ * is a power of 2, we can check alignment using just the bottom
+ * 32 bits for a DMA address of any size.
+ */
+ BUILD_BUG_ON(!is_power_of_2(IPA_TABLE_ALIGN));
+ if (lower_32_bits(addr) % IPA_TABLE_ALIGN) {
+ dev_err(dev, "table address %pad not %u-byte aligned\n",
+ &addr, IPA_TABLE_ALIGN);
+ dma_free_coherent(dev, size, virt, addr);
+
+ return -ERANGE;
+ }
+
ipa->table_virt = virt;
ipa->table_addr = addr;
diff --git a/drivers/net/ipa/ipa_table.h b/drivers/net/ipa/ipa_table.h
index 1a68d20f19d6..889c2e93b122 100644
--- a/drivers/net/ipa/ipa_table.h
+++ b/drivers/net/ipa/ipa_table.h
@@ -55,7 +55,10 @@ static inline bool ipa_filter_map_valid(struct ipa *ipa, u32 filter_mask)
* ipa_table_hash_support() - Return true if hashed tables are supported
* @ipa: IPA pointer
*/
-bool ipa_table_hash_support(struct ipa *ipa);
+static inline bool ipa_table_hash_support(struct ipa *ipa)
+{
+ return ipa->version != IPA_VERSION_4_2;
+}
/**
* ipa_table_reset() - Reset filter and route tables entries to "none"
diff --git a/drivers/net/ipa/ipa_version.h b/drivers/net/ipa/ipa_version.h
index 2944e2a89023..ee2b3d02f3cd 100644
--- a/drivers/net/ipa/ipa_version.h
+++ b/drivers/net/ipa/ipa_version.h
@@ -8,17 +8,32 @@
/**
* enum ipa_version
+ * @IPA_VERSION_3_0: IPA version 3.0/GSI version 1.0
+ * @IPA_VERSION_3_1: IPA version 3.1/GSI version 1.1
+ * @IPA_VERSION_3_5: IPA version 3.5/GSI version 1.2
+ * @IPA_VERSION_3_5_1: IPA version 3.5.1/GSI version 1.3
+ * @IPA_VERSION_4_0: IPA version 4.0/GSI version 2.0
+ * @IPA_VERSION_4_1: IPA version 4.1/GSI version 2.0
+ * @IPA_VERSION_4_2: IPA version 4.2/GSI version 2.2
+ * @IPA_VERSION_4_5: IPA version 4.5/GSI version 2.5
+ * @IPA_VERSION_4_7: IPA version 4.7/GSI version 2.7
+ * @IPA_VERSION_4_9: IPA version 4.9/GSI version 2.9
+ * @IPA_VERSION_4_11: IPA version 4.11/GSI version 2.11 (2.1.1)
*
* Defines the version of IPA (and GSI) hardware present on the platform.
- * It seems this might be better defined elsewhere, but having it here gets
- * it where it's needed.
*/
enum ipa_version {
- IPA_VERSION_3_5_1, /* GSI version 1.3.0 */
- IPA_VERSION_4_0, /* GSI version 2.0 */
- IPA_VERSION_4_1, /* GSI version 2.1 */
- IPA_VERSION_4_2, /* GSI version 2.2 */
- IPA_VERSION_4_5, /* GSI version 2.5 */
+ IPA_VERSION_3_0,
+ IPA_VERSION_3_1,
+ IPA_VERSION_3_5,
+ IPA_VERSION_3_5_1,
+ IPA_VERSION_4_0,
+ IPA_VERSION_4_1,
+ IPA_VERSION_4_2,
+ IPA_VERSION_4_5,
+ IPA_VERSION_4_7,
+ IPA_VERSION_4_9,
+ IPA_VERSION_4_11,
};
#endif /* _IPA_VERSION_H_ */
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-23 15:11:11 +0300