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path: root/drivers/net/wireless/realtek/rtlwifi/wifi.h
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Diffstat (limited to 'drivers/net/wireless/realtek/rtlwifi/wifi.h')
-rw-r--r--drivers/net/wireless/realtek/rtlwifi/wifi.h71
1 files changed, 39 insertions, 32 deletions
diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h
index dafe486f8448..65ef42b37651 100644
--- a/drivers/net/wireless/realtek/rtlwifi/wifi.h
+++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h
@@ -157,8 +157,8 @@ enum rtl8192c_h2c_cmd {
#define MAX_REGULATION_NUM 4
#define MAX_RF_PATH_NUM 4
#define MAX_RATE_SECTION_NUM 6
-#define MAX_2_4G_BANDWITH_NUM 4
-#define MAX_5G_BANDWITH_NUM 4
+#define MAX_2_4G_BANDWIDTH_NUM 4
+#define MAX_5G_BANDWIDTH_NUM 4
#define MAX_RF_PATH 4
#define MAX_CHNL_GROUP_24G 6
#define MAX_CHNL_GROUP_5G 14
@@ -925,6 +925,14 @@ enum wolpattern_type {
UNKNOWN_TYPE = 4,
};
+enum package_type {
+ PACKAGE_DEFAULT,
+ PACKAGE_QFN68,
+ PACKAGE_TFBGA90,
+ PACKAGE_TFBGA80,
+ PACKAGE_TFBGA79
+};
+
struct octet_string {
u8 *octet;
u16 length;
@@ -1257,12 +1265,12 @@ struct rtl_phy {
u8 cur_bw40_txpwridx;
s8 txpwr_limit_2_4g[MAX_REGULATION_NUM]
- [MAX_2_4G_BANDWITH_NUM]
+ [MAX_2_4G_BANDWIDTH_NUM]
[MAX_RATE_SECTION_NUM]
[CHANNEL_MAX_NUMBER_2G]
[MAX_RF_PATH_NUM];
s8 txpwr_limit_5g[MAX_REGULATION_NUM]
- [MAX_5G_BANDWITH_NUM]
+ [MAX_5G_BANDWIDTH_NUM]
[MAX_RATE_SECTION_NUM]
[CHANNEL_MAX_NUMBER_5G]
[MAX_RF_PATH_NUM];
@@ -1509,6 +1517,7 @@ struct rtl_hal {
u32 version; /*version of chip */
u8 state; /*stop 0, start 1 */
u8 board_type;
+ u8 package_type;
u8 external_pa;
u8 pa_mode;
@@ -2193,6 +2202,8 @@ struct rtl_hal_ops {
struct rtl_wow_pattern *rtl_pattern,
u8 index);
u16 (*get_available_desc)(struct ieee80211_hw *hw, u8 q_idx);
+ void (*c2h_content_parsing)(struct ieee80211_hw *hw, u8 tag, u8 len,
+ u8 *val);
};
struct rtl_intf_ops {
@@ -2221,11 +2232,13 @@ struct rtl_intf_ops {
};
struct rtl_mod_params {
+ /* default: 0,0 */
+ u64 debug_mask;
/* default: 0 = using hardware encryption */
bool sw_crypto;
/* default: 0 = DBG_EMERG (0)*/
- int debug;
+ int debug_level;
/* default: 1 = using no linked power save */
bool inactiveps;
@@ -2306,6 +2319,7 @@ struct rtl_locks {
spinlock_t waitq_lock;
spinlock_t entry_list_lock;
spinlock_t usb_lock;
+ spinlock_t c2hcmd_lock;
/*FW clock change */
spinlock_t fw_ps_lock;
@@ -2335,6 +2349,7 @@ struct rtl_works {
struct workqueue_struct *rtl_wq;
struct delayed_work watchdog_wq;
struct delayed_work ips_nic_off_wq;
+ struct delayed_work c2hcmd_wq;
/* For SW LPS */
struct delayed_work ps_work;
@@ -2345,16 +2360,6 @@ struct rtl_works {
struct work_struct fill_h2c_cmd;
};
-struct rtl_debug {
- u32 dbgp_type[DBGP_TYPE_MAX];
- int global_debuglevel;
- u64 global_debugcomponents;
-
- /* add for proc debug */
- struct proc_dir_entry *proc_dir;
- char proc_name[20];
-};
-
#define MIMO_PS_STATIC 0
#define MIMO_PS_DYNAMIC 1
#define MIMO_PS_NOLIMIT 3
@@ -2462,6 +2467,7 @@ struct rtl_btc_info {
u8 bt_type;
u8 btcoexist;
u8 ant_num;
+ u8 single_ant_path;
};
struct bt_coexist_info {
@@ -2551,6 +2557,13 @@ struct proxim {
u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
};
+struct rtl_c2hcmd {
+ struct list_head list;
+ u8 tag;
+ u8 len;
+ u8 *val;
+};
+
struct rtl_priv {
struct ieee80211_hw *hw;
struct completion firmware_loading_complete;
@@ -2570,6 +2583,7 @@ struct rtl_priv {
struct rtl_dm dm;
struct rtl_security sec;
struct rtl_efuse efuse;
+ struct rtl_led_ctl ledctl;
struct rtl_ps_ctl psc;
struct rate_adaptive ra;
@@ -2583,7 +2597,9 @@ struct rtl_priv {
/* sta entry list for ap adhoc or mesh */
struct list_head entry_list;
- struct rtl_debug dbg;
+ /* c2hcmd list for kthread level access */
+ struct list_head c2hcmd_list;
+
int max_fw_size;
/*
@@ -2713,23 +2729,14 @@ enum bt_radio_shared {
(le32_to_cpu(_val))
/* Read data from memory */
-#define READEF1BYTE(_ptr) \
+#define READEF1BYTE(_ptr) \
EF1BYTE(*((u8 *)(_ptr)))
/* Read le16 data from memory and convert to host ordering */
-#define READEF2BYTE(_ptr) \
+#define READEF2BYTE(_ptr) \
EF2BYTE(*(_ptr))
-#define READEF4BYTE(_ptr) \
+#define READEF4BYTE(_ptr) \
EF4BYTE(*(_ptr))
-/* Write data to memory */
-#define WRITEEF1BYTE(_ptr, _val) \
- (*((u8 *)(_ptr))) = EF1BYTE(_val)
-/* Write le16 data to memory in host ordering */
-#define WRITEEF2BYTE(_ptr, _val) \
- (*((u16 *)(_ptr))) = EF2BYTE(_val)
-#define WRITEEF4BYTE(_ptr, _val) \
- (*((u32 *)(_ptr))) = EF2BYTE(_val)
-
/* Create a bit mask
* Examples:
* BIT_LEN_MASK_32(0) => 0x00000000
@@ -2810,14 +2817,14 @@ value to host byte ordering.*/
* Set subfield of little-endian 4-byte value to specified value.
*/
#define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
- *((u32 *)(__pstart)) = \
- ( \
+ *((__le32 *)(__pstart)) = \
+ cpu_to_le32( \
LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
);
#define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
- *((u16 *)(__pstart)) = \
- ( \
+ *((__le16 *)(__pstart)) = \
+ cpu_to_le16( \
LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
);