diff options
Diffstat (limited to 'drivers/net/wireless/realtek/rtw89/reg.h')
| -rw-r--r-- | drivers/net/wireless/realtek/rtw89/reg.h | 134 |
1 files changed, 132 insertions, 2 deletions
diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index 266e4231b5f3..55595fde7494 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -19,6 +19,8 @@ #define B_AX_FEN_BBRSTB BIT(0) #define R_AX_SYS_PW_CTRL 0x0004 +#define B_AX_SOP_ASWRM BIT(31) +#define B_AX_SOP_PWMM_DSWR BIT(29) #define B_AX_XTAL_OFF_A_DIE BIT(22) #define B_AX_DIS_WLBT_PDNSUSEN_SOPC BIT(18) #define B_AX_RDY_SYSPWR BIT(17) @@ -134,6 +136,8 @@ #define B_AX_PLATFORM_EN BIT(0) #define R_AX_WLLPS_CTRL 0x0090 +#define B_AX_LPSOP_ASWRM BIT(17) +#define B_AX_LPSOP_DSWRM BIT(9) #define B_AX_DIS_WLBT_LPSEN_LOPC BIT(1) #define SW_LPS_OPTION 0x0001A0B2 @@ -222,9 +226,14 @@ #define B_AX_OCP_L1_MASK GENMASK(15, 13) #define B_AX_VOL_L1_MASK GENMASK(3, 0) +#define R_AX_SPSLDO_ON_CTRL1 0x0204 +#define B_AX_FPWMDELAY BIT(3) + #define R_AX_LDO_AON_CTRL0 0x0218 #define B_AX_PD_REGU_L BIT(16) +#define R_AX_SPSANA_ON_CTRL1 0x0224 + #define R_AX_WLAN_XTAL_SI_CTRL 0x0270 #define B_AX_WL_XTAL_SI_CMD_POLL BIT(31) #define B_AX_BT_XTAL_SI_ERR_FLAG BIT(30) @@ -237,17 +246,30 @@ #define B_AX_WL_XTAL_SI_DATA_MASK GENMASK(15, 8) #define B_AX_WL_XTAL_SI_ADDR_MASK GENMASK(7, 0) +#define R_AX_WLAN_XTAL_SI_CONFIG 0x0274 +#define B_AX_XTAL_SI_ADDR_NOT_CHK BIT(0) + #define R_AX_XTAL_ON_CTRL0 0x0280 #define B_AX_XTAL_SC_LPS BIT(31) #define B_AX_XTAL_SC_XO_MASK GENMASK(23, 17) #define B_AX_XTAL_SC_XI_MASK GENMASK(16, 10) #define B_AX_XTAL_SC_MASK GENMASK(6, 0) +#define R_AX_XTAL_ON_CTRL3 0x028C +#define B_AX_XTAL_SC_INIT_A_BLOCK_MASK GENMASK(30, 24) +#define B_AX_XTAL_SC_LPS_A_BLOCK_MASK GENMASK(22, 16) +#define B_AX_XTAL_SC_XO_A_BLOCK_MASK GENMASK(14, 8) +#define B_AX_XTAL_SC_XI_A_BLOCK_MASK GENMASK(6, 0) + #define R_AX_GPIO0_7_FUNC_SEL 0x02D0 #define R_AX_EECS_EESK_FUNC_SEL 0x02D8 #define B_AX_PINMUX_EESK_FUNC_SEL_MASK GENMASK(7, 4) +#define R_AX_GPIO16_23_FUNC_SEL 0x02D8 +#define B_AX_PINMUX_GPIO17_FUNC_SEL_MASK GENMASK(7, 4) +#define B_AX_PINMUX_GPIO16_FUNC_SEL_MASK GENMASK(3, 0) + #define R_AX_LED1_FUNC_SEL 0x02DC #define B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK GENMASK(27, 24) #define PINMUX_EESK_FUNC_SEL_BT_LOG 0x1 @@ -257,6 +279,10 @@ #define B_AX_EESK_PULL_LOW_EN BIT(17) #define B_AX_EECS_PULL_LOW_EN BIT(16) +#define R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN 0x02E4 +#define B_AX_GPIO16_PULL_LOW_EN_V1 BIT(19) +#define B_AX_GPIO10_PULL_LOW_EN BIT(10) + #define R_AX_WLRF_CTRL 0x02F0 #define B_AX_AFC_AFEDIG BIT(17) #define B_AX_WLRF1_CTRL_7 BIT(15) @@ -3299,10 +3325,36 @@ #define B_AX_TXAGC_BT_EN BIT(1) #define B_AX_TXAGC_BT_MASK GENMASK(11, 3) +#define R_AX_PWR_SWING_OTHER_CTRL0 0xD230 +#define R_AX_PWR_SWING_OTHER_CTRL0_C1 0xF230 +#define B_AX_CFIR_BY_RATE_OFF_MASK GENMASK(17, 0) + #define R_AX_PWR_UL_CTRL0 0xD240 #define R_AX_PWR_UL_CTRL2 0xD248 #define B_AX_PWR_UL_CFO_MASK GENMASK(2, 0) #define B_AX_PWR_UL_CTRL2_MASK 0x07700007 + +#define R_AX_PWR_NORM_FORCE1 0xD260 +#define R_AX_PWR_NORM_FORCE1_C1 0xF260 +#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_EN BIT(29) +#define B_AX_TXAGC_BF_PWR_BOOST_FORCE_VAL_MASK GENMASK(28, 24) +#define B_AX_FORCE_HE_ER_SU_EN_EN BIT(23) +#define B_AX_FORCE_HE_ER_SU_EN_VALUE BIT(22) +#define B_AX_FORCE_MACID_CCA_TH_EN_EN BIT(21) +#define B_AX_FORCE_MACID_CCA_TH_EN_VALUE BIT(20) +#define B_AX_FORCE_BT_GRANT_EN BIT(19) +#define B_AX_FORCE_BT_GRANT_VALUE BIT(18) +#define B_AX_FORCE_RX_LTE_EN BIT(17) +#define B_AX_FORCE_RX_LTE_VALUE BIT(16) +#define B_AX_FORCE_TXBF_EN_EN BIT(15) +#define B_AX_FORCE_TXBF_EN_VALUE BIT(14) +#define B_AX_FORCE_TXSC_EN BIT(13) +#define B_AX_FORCE_TXSC_VALUE_MASK GENMASK(12, 9) +#define B_AX_FORCE_NTX_EN BIT(6) +#define B_AX_FORCE_NTX_VALUE BIT(5) +#define B_AX_FORCE_PWR_MODE_EN BIT(3) +#define B_AX_FORCE_PWR_MODE_VALUE_MASK GENMASK(2, 0) + #define R_AX_PWR_UL_TB_CTRL 0xD288 #define B_AX_PWR_UL_TB_CTRL_EN BIT(31) #define R_AX_PWR_UL_TB_1T 0xD28C @@ -3312,16 +3364,22 @@ #define B_AX_PWR_UL_TB_2T_MASK GENMASK(4, 0) #define B_AX_PWR_UL_TB_2T_V1_MASK GENMASK(7, 0) #define R_AX_PWR_BY_RATE_TABLE0 0xD2C0 +#define R_AX_PWR_BY_RATE_TABLE6 0xD2D8 #define R_AX_PWR_BY_RATE_TABLE10 0xD2E8 #define R_AX_PWR_BY_RATE R_AX_PWR_BY_RATE_TABLE0 +#define R_AX_PWR_BY_RATE_1SS_MAX R_AX_PWR_BY_RATE_TABLE6 #define R_AX_PWR_BY_RATE_MAX R_AX_PWR_BY_RATE_TABLE10 #define R_AX_PWR_LMT_TABLE0 0xD2EC +#define R_AX_PWR_LMT_TABLE9 0xD310 #define R_AX_PWR_LMT_TABLE19 0xD338 #define R_AX_PWR_LMT R_AX_PWR_LMT_TABLE0 +#define R_AX_PWR_LMT_1SS_MAX R_AX_PWR_LMT_TABLE9 #define R_AX_PWR_LMT_MAX R_AX_PWR_LMT_TABLE19 #define R_AX_PWR_RU_LMT_TABLE0 0xD33C +#define R_AX_PWR_RU_LMT_TABLE5 0xD350 #define R_AX_PWR_RU_LMT_TABLE11 0xD368 #define R_AX_PWR_RU_LMT R_AX_PWR_RU_LMT_TABLE0 +#define R_AX_PWR_RU_LMT_1SS_MAX R_AX_PWR_RU_LMT_TABLE5 #define R_AX_PWR_RU_LMT_MAX R_AX_PWR_RU_LMT_TABLE11 #define R_AX_PWR_MACID_LMT_TABLE0 0xD36C #define R_AX_PWR_MACID_LMT_TABLE127 0xD568 @@ -3574,6 +3632,7 @@ #define RR_MOD_MASK GENMASK(19, 16) #define RR_MOD_DCK GENMASK(14, 10) #define RR_MOD_RGM GENMASK(13, 4) +#define RR_MOD_RXB GENMASK(9, 5) #define RR_MOD_V_DOWN 0x0 #define RR_MOD_V_STANDBY 0x1 #define RR_TXAGC 0x10001 @@ -3713,6 +3772,7 @@ #define RR_RXBB 0x83 #define RR_RXBB_VOBUF GENMASK(15, 12) #define RR_RXBB_C2G GENMASK(16, 10) +#define RR_RXBB_C2 GENMASK(11, 8) #define RR_RXBB_C1G GENMASK(9, 8) #define RR_RXBB_FATT GENMASK(7, 0) #define RR_RXBB_ATTR GENMASK(7, 4) @@ -3727,6 +3787,7 @@ #define RR_RXA_DPK GENMASK(9, 8) #define RR_RXA_LNA 0x8b #define RR_RXA2 0x8c +#define RR_RAA2_SATT GENMASK(15, 13) #define RR_RAA2_SWATT GENMASK(15, 9) #define RR_RXA2_C1 GENMASK(12, 10) #define RR_RXA2_C2 GENMASK(9, 3) @@ -3776,19 +3837,26 @@ #define RR_LOGEN 0xa3 #define RR_LOGEN_RPT GENMASK(19, 16) #define RR_SX 0xaf +#define RR_IBD 0xc9 +#define RR_IBD_VAL GENMASK(4, 0) #define RR_LDO 0xb1 #define RR_LDO_SEL GENMASK(8, 6) #define RR_VCO 0xb2 +#define RR_VCO_SEL GENMASK(9, 8) +#define RR_VCI 0xb3 +#define RR_VCI_ON BIT(7) #define RR_LPF 0xb7 #define RR_LPF_BUSY BIT(8) #define RR_XTALX2 0xb8 #define RR_MALSEL 0xbe #define RR_SYNFB 0xc5 #define RR_SYNFB_LK BIT(15) +#define RR_AACK 0xca #define RR_LCKST 0xcf #define RR_LCKST_BIN BIT(0) #define RR_LCK_TRG 0xd3 #define RR_LCK_TRGSEL BIT(8) +#define RR_LCK_ST BIT(4) #define RR_MMD 0xd5 #define RR_MMD_RST_EN BIT(8) #define RR_MMD_RST_SYN BIT(6) @@ -3807,6 +3875,7 @@ #define RR_CAL_RW BIT(19) #define RR_LUTWE2 0xee #define RR_LUTWE2_RTXBW BIT(2) +#define RR_LUTWE2_DIS BIT(6) #define RR_LUTWE 0xef #define RR_LUTWE_LOK BIT(2) #define RR_RFC 0xf0 @@ -3832,6 +3901,7 @@ #define R_RFE_E_A2 0x0334 #define R_RFE_O_SEL_A2 0x0338 #define R_RFE_SEL0_A2 0x033C +#define B_RFE_SEL0_MASK GENMASK(1, 0) #define R_RFE_SEL32_A2 0x0340 #define R_CIRST 0x035c #define B_CIRST_SYN GENMASK(11, 10) @@ -3852,6 +3922,9 @@ #define B_ENABLE_CCK BIT(5) #define R_RSTB_ASYNC 0x0704 #define B_RSTB_ASYNC_ALL BIT(1) +#define R_P0_ANT_SW 0x0728 +#define B_P0_HW_ANTSW_DIS_BY_GNT_BT BIT(12) +#define B_P0_TRSW_TX_EXTEND GENMASK(3, 0) #define R_MAC_PIN_SEL 0x0734 #define B_CH_IDX_SEG0 GENMASK(23, 16) #define R_PLCP_HISTOGRAM 0x0738 @@ -3961,6 +4034,7 @@ #define R_S0_HW_SI_DIS 0x1200 #define B_S0_HW_SI_DIS_W_R_TRIG GENMASK(30, 28) #define R_P0_RXCK 0x12A0 +#define B_P0_RXCK_ADJ GENMASK(31, 23) #define B_P0_RXCK_BW3 BIT(30) #define B_P0_TXCK_ALL GENMASK(19, 12) #define B_P0_RXCK_ON BIT(19) @@ -4034,6 +4108,7 @@ #define R_TXAGC_BB 0x1C60 #define B_TXAGC_BB_OFT GENMASK(31, 16) #define B_TXAGC_BB GENMASK(31, 24) +#define B_TXAGC_RF GENMASK(5, 0) #define R_S0_ADDCK 0x1E00 #define B_S0_ADDCK_I GENMASK(9, 0) #define B_S0_ADDCK_Q GENMASK(19, 10) @@ -4117,8 +4192,10 @@ #define R_DCFO 0x4264 #define B_DCFO GENMASK(7, 0) #define R_SEG0CSI 0x42AC +#define R_SEG0CSI_V1 0x42B0 #define B_SEG0CSI_IDX GENMASK(10, 0) #define R_SEG0CSI_EN 0x42C4 +#define R_SEG0CSI_EN_V1 0x42C8 #define B_SEG0CSI_EN BIT(23) #define R_BSS_CLR_MAP 0x43ac #define R_BSS_CLR_MAP_V1 0x43B0 @@ -4350,6 +4427,14 @@ #define B_PATH0_BT_BACKOFF_V1 GENMASK(23, 0) #define R_PATH1_BT_BACKOFF_V1 0x4AEC #define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0) +#define R_DCFO_COMP_S0_V2 0x4B20 +#define B_DCFO_COMP_S0_MSK_V2 GENMASK(13, 0) +#define R_PATH0_TX_CFR 0x4B30 +#define B_PATH0_TX_CFR_LGC1 GENMASK(19, 10) +#define B_PATH0_TX_CFR_LGC0 GENMASK(9, 0) +#define R_PATH0_TX_POLAR_CLIPPING 0x4B3C +#define B_PATH0_TX_POLAR_CLIPPING_LGC1 GENMASK(19, 16) +#define B_PATH0_TX_POLAR_CLIPPING_LGC0 GENMASK(15, 12) #define R_PATH0_FRC_FIR_TYPE_V1 0x4C00 #define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0) #define R_PATH0_NOTCH 0x4C14 @@ -4455,10 +4540,29 @@ #define B_P0_RFCTM_VAL GENMASK(25, 20) #define R_P0_RFCTM_RDY BIT(26) #define R_P0_TRSW 0x5868 -#define B_P0_TRSW_B BIT(0) -#define B_P0_TRSW_A BIT(1) +#define B_P0_BT_FORCE_ANTIDX_EN BIT(12) #define B_P0_TRSW_X BIT(2) +#define B_P0_TRSW_A BIT(1) +#define B_P0_TX_ANT_SEL BIT(1) +#define B_P0_TRSW_B BIT(0) +#define B_P0_ANT_TRAIN_EN BIT(0) #define B_P0_TRSW_SO_A2 GENMASK(7, 5) +#define R_P0_ANTSEL 0x586C +#define B_P0_ANTSEL_SW_5G BIT(25) +#define B_P0_ANTSEL_SW_2G BIT(23) +#define B_P0_ANTSEL_BTG_TRX BIT(21) +#define B_P0_ANTSEL_CGCS_CTRL BIT(17) +#define B_P0_ANTSEL_HW_CTRL BIT(16) +#define B_P0_ANTSEL_TX_ORI GENMASK(15, 12) +#define B_P0_ANTSEL_RX_ALT GENMASK(11, 8) +#define B_P0_ANTSEL_RX_ORI GENMASK(7, 4) +#define R_RFSW_CTRL_ANT0_BASE 0x5870 +#define B_RFSW_CTRL_ANT_MAPPING GENMASK(15, 0) +#define R_RFE_SEL0_BASE 0x5880 +#define B_RFE_SEL0_SRC_MASK GENMASK(3, 0) +#define R_RFE_SEL32_BASE 0x5884 +#define RFE_SEL0_SRC_ANTSEL_0 8 +#define R_RFE_INV0 0x5890 #define R_P0_RFM 0x5894 #define B_P0_RFM_DIS_WL BIT(7) #define B_P0_RFM_TX_OPT BIT(6) @@ -4572,12 +4676,15 @@ #define IQK_DF4_TXT_8_25MHZ 0x021 #define R_IQK_CFG 0x8034 #define B_IQK_CFG_SET GENMASK(5, 4) +#define R_IQK_RXA 0x8044 +#define B_IQK_RXAGC GENMASK(15, 13) #define R_TPG_SEL 0x8068 #define R_TPG_MOD 0x806C #define B_TPG_MOD_F GENMASK(2, 1) #define R_MDPK_SYNC 0x8070 #define B_MDPK_SYNC_SEL BIT(31) #define B_MDPK_SYNC_MAN GENMASK(31, 28) +#define B_MDPK_SYNC_DMAN GENMASK(30, 28) #define R_MDPK_RX_DCK 0x8074 #define B_MDPK_RX_DCK_EN BIT(31) #define R_KIP_MOD 0x8078 @@ -4586,6 +4693,7 @@ #define R_KIP_SYSCFG 0x8088 #define R_KIP_CLK 0x808C #define R_DPK_IDL 0x809C +#define B_DPK_IDL_SEL GENMASK(10, 9) #define B_DPK_IDL BIT(8) #define R_LDL_NORM 0x80A0 #define B_LDL_NORM_MA BIT(16) @@ -4604,6 +4712,10 @@ #define B_KIP_RPT1_SEL GENMASK(21, 16) #define B_KIP_RPT1_SEL_V1 GENMASK(19, 16) #define R_SRAM_IQRX 0x80D8 +#define R_IDL_MPA 0x80DC +#define B_IDL_DN BIT(31) +#define B_IDL_MD530 BIT(1) +#define B_IDL_MD500 BIT(0) #define R_GAPK 0x80E0 #define B_GAPK_ADR BIT(0) #define R_SRAM_IQRX2 0x80E8 @@ -4619,6 +4731,7 @@ #define B_PRT_COM_SYNERR BIT(30) #define B_PRT_COM_DCI GENMASK(27, 16) #define B_PRT_COM_CORV GENMASK(15, 8) +#define B_RPT_COM_RDY GENMASK(15, 0) #define B_PRT_COM_DCQ GENMASK(11, 0) #define B_PRT_COM_RXOV BIT(8) #define B_PRT_COM_GL GENMASK(7, 4) @@ -4690,6 +4803,7 @@ #define B_DPK_GL_A0 GENMASK(31, 28) #define B_DPK_GL_A1 GENMASK(17, 0) #define R_RPT_PER 0x81FC +#define B_RPT_PER_KSET GENMASK(31, 29) #define B_RPT_PER_TSSI GENMASK(28, 16) #define B_RPT_PER_OF GENMASK(15, 8) #define B_RPT_PER_TH GENMASK(5, 0) @@ -4730,11 +4844,15 @@ #define B_IQKINF2_KCNT GENMASK(15, 8) #define B_IQKINF2_NCTLV GENMASK(7, 0) #define R_DCOF0 0xC000 +#define B_DCOF0_RST BIT(17) #define B_DCOF0_V GENMASK(4, 1) #define R_DCOF1 0xC004 +#define B_DCOF1_RST BIT(17) #define B_DCOF1_S BIT(0) #define R_DCOF8 0xC020 #define B_DCOF8_V GENMASK(4, 1) +#define R_DCOF9 0xC024 +#define B_DCOF9_RST BIT(17) #define R_DACK_S0P0 0xC040 #define B_DACK_S0P0_OK BIT(31) #define R_DACK_BIAS00 0xc048 @@ -4779,13 +4897,19 @@ #define R_P0_CFCH_BW1 0xC0D8 #define B_P0_CFCH_EX BIT(13) #define B_P0_CFCH_BW1 GENMASK(8, 5) +#define R_WDADC 0xC0E4 +#define B_WDADC_SEL GENMASK(5, 4) #define R_ADCMOD 0xC0E8 #define B_ADCMOD_LP GENMASK(31, 16) +#define R_DCIM 0xC0EC +#define B_DCIM_FR GENMASK(14, 13) #define R_ADDCK0D 0xC0F0 #define B_ADDCK0D_VAL2 GENMASK(31, 26) #define B_ADDCK0D_VAL GENMASK(25, 16) +#define B_ADDCK_DS BIT(16) #define R_ADDCK0 0xC0F4 #define B_ADDCK0_TRG BIT(11) +#define B_ADDCK0_IQ BIT(10) #define B_ADDCK0 GENMASK(9, 8) #define B_ADDCK0_MAN GENMASK(5, 4) #define B_ADDCK0_EN BIT(4) @@ -4797,6 +4921,7 @@ #define B_ADDCK0_RL0 GENMASK(17, 8) #define R_ADDCKR0 0xC0FC #define B_ADDCKR0_A0 GENMASK(19, 10) +#define B_ADDCKR0_DC GENMASK(15, 4) #define B_ADDCKR0_A1 GENMASK(9, 0) #define R_DACK10 0xC100 #define B_DACK10 GENMASK(4, 1) @@ -4847,6 +4972,11 @@ #define R_ADDCKR1 0xC1fC #define B_ADDCKR1_A0 GENMASK(19, 10) #define B_ADDCKR1_A1 GENMASK(9, 0) +#define R_DACKN0_CTL 0xC210 +#define B_DACKN0_EN BIT(0) +#define B_DACKN0_V GENMASK(21, 14) +#define R_DACKN1_CTL 0xC224 +#define B_DACKN1_V GENMASK(21, 14) /* WiFi CPU local domain */ #define R_AX_WDT_CTRL 0x0040 |