diff options
Diffstat (limited to 'drivers/net/wireless/realtek')
24 files changed, 2217 insertions, 259 deletions
diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c index 43ee7592bc6e..180907319e8c 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c @@ -7961,6 +7961,18 @@ static const struct usb_device_id dev_table[] = { .driver_info = (unsigned long)&rtl8192eu_fops}, {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff), .driver_info = (unsigned long)&rtl8192eu_fops}, +/* D-Link DWA-131 rev C1 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3312, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192eu_fops}, +/* TP-Link TL-WN8200ND V2 */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0126, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192eu_fops}, +/* Mercusys MW300UM */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0100, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192eu_fops}, +/* Mercusys MW300UH */ +{USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0104, 0xff, 0xff, 0xff), + .driver_info = (unsigned long)&rtl8192eu_fops}, #endif { } }; diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c index 12d0b3a87af7..0fab3a0c7d49 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/phy.c @@ -16,12 +16,6 @@ static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw, static void _rtl88e_phy_rf_serial_write(struct ieee80211_hw *hw, enum radio_path rfpath, u32 offset, u32 data); -static u32 _rtl88e_phy_calculate_bit_shift(u32 bitmask) -{ - u32 i = ffs(bitmask); - - return i ? i - 1 : 32; -} static bool _rtl88e_phy_bb8188e_config_parafile(struct ieee80211_hw *hw); static bool _rtl88e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw); static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw, @@ -51,7 +45,7 @@ u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask); originalvalue = rtl_read_dword(rtlpriv, regaddr); - bitshift = _rtl88e_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); returnvalue = (originalvalue & bitmask) >> bitshift; rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, @@ -74,7 +68,7 @@ void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw, if (bitmask != MASKDWORD) { originalvalue = rtl_read_dword(rtlpriv, regaddr); - bitshift = _rtl88e_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((originalvalue & (~bitmask)) | (data << bitshift)); } @@ -99,7 +93,7 @@ u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw, original_value = _rtl88e_phy_rf_serial_read(hw, rfpath, regaddr); - bitshift = _rtl88e_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); readback_value = (original_value & bitmask) >> bitshift; spin_unlock(&rtlpriv->locks.rf_lock); @@ -127,7 +121,7 @@ void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw, original_value = _rtl88e_phy_rf_serial_read(hw, rfpath, regaddr); - bitshift = _rtl88e_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((original_value & (~bitmask)) | (data << bitshift)); diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c index d448efe2c229..3730613a3962 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c @@ -17,7 +17,7 @@ u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask); originalvalue = rtl_read_dword(rtlpriv, regaddr); - bitshift = _rtl92c_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); returnvalue = (originalvalue & bitmask) >> bitshift; rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, @@ -40,7 +40,7 @@ void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw, if (bitmask != MASKDWORD) { originalvalue = rtl_read_dword(rtlpriv, regaddr); - bitshift = _rtl92c_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((originalvalue & (~bitmask)) | (data << bitshift)); } @@ -143,14 +143,6 @@ void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw, } EXPORT_SYMBOL(_rtl92c_phy_rf_serial_write); -u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask) -{ - u32 i = ffs(bitmask); - - return i ? i - 1 : 32; -} -EXPORT_SYMBOL(_rtl92c_phy_calculate_bit_shift); - static void _rtl92c_phy_bb_config_1t(struct ieee80211_hw *hw) { rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2); diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.h index 75afa6253ad0..e64d377dfe9e 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.h +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.h @@ -196,7 +196,6 @@ bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw, void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw); void rtl92c_phy_set_io(struct ieee80211_hw *hw); void rtl92c_bb_block_on(struct ieee80211_hw *hw); -u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask); long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw, enum wireless_mode wirelessmode, u8 txpwridx); diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c index da54e51badd3..fa70a7d5539f 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.c @@ -39,7 +39,7 @@ u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw, rfpath, regaddr); } - bitshift = _rtl92c_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); readback_value = (original_value & bitmask) >> bitshift; spin_unlock(&rtlpriv->locks.rf_lock); @@ -110,7 +110,7 @@ void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw, original_value = _rtl92c_phy_rf_serial_read(hw, rfpath, regaddr); - bitshift = _rtl92c_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((original_value & (~bitmask)) | (data << bitshift)); @@ -122,7 +122,7 @@ void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw, original_value = _rtl92c_phy_fw_rf_serial_read(hw, rfpath, regaddr); - bitshift = _rtl92c_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((original_value & (~bitmask)) | (data << bitshift)); diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.h b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.h index 7582a162bd11..c7a0d4c776f0 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.h +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ce/phy.h @@ -94,7 +94,6 @@ u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw, enum radio_path rfpath, u32 offset); u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw, enum radio_path rfpath, u32 offset); -u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask); void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw, enum radio_path rfpath, u32 offset, u32 data); void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw, diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c index a8d9fe269f31..0b8cb7e61fd8 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/phy.c @@ -32,7 +32,7 @@ u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw, original_value = _rtl92c_phy_fw_rf_serial_read(hw, rfpath, regaddr); } - bitshift = _rtl92c_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); readback_value = (original_value & bitmask) >> bitshift; rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n", @@ -56,7 +56,7 @@ void rtl92cu_phy_set_rf_reg(struct ieee80211_hw *hw, original_value = _rtl92c_phy_rf_serial_read(hw, rfpath, regaddr); - bitshift = _rtl92c_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((original_value & (~bitmask)) | (data << bitshift)); @@ -67,7 +67,7 @@ void rtl92cu_phy_set_rf_reg(struct ieee80211_hw *hw, original_value = _rtl92c_phy_fw_rf_serial_read(hw, rfpath, regaddr); - bitshift = _rtl92c_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((original_value & (~bitmask)) | (data << bitshift)); diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c index d18c092b6142..d835a27429f0 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c @@ -169,13 +169,6 @@ static const u8 channel_all[59] = { 157, 159, 161, 163, 165 }; -static u32 _rtl92d_phy_calculate_bit_shift(u32 bitmask) -{ - u32 i = ffs(bitmask); - - return i ? i - 1 : 32; -} - u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) { struct rtl_priv *rtlpriv = rtl_priv(hw); @@ -198,7 +191,7 @@ u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) } else { originalvalue = rtl_read_dword(rtlpriv, regaddr); } - bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); returnvalue = (originalvalue & bitmask) >> bitshift; rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n", @@ -230,7 +223,7 @@ void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw, dbi_direct); else originalvalue = rtl_read_dword(rtlpriv, regaddr); - bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((originalvalue & (~bitmask)) | (data << bitshift)); } if (rtlhal->during_mac1init_radioa || rtlhal->during_mac0init_radiob) @@ -317,7 +310,7 @@ u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw, regaddr, rfpath, bitmask); spin_lock(&rtlpriv->locks.rf_lock); original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr); - bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); readback_value = (original_value & bitmask) >> bitshift; spin_unlock(&rtlpriv->locks.rf_lock); rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, @@ -343,7 +336,7 @@ void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, if (bitmask != RFREG_OFFSET_MASK) { original_value = _rtl92d_phy_rf_serial_read(hw, rfpath, regaddr); - bitshift = _rtl92d_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((original_value & (~bitmask)) | (data << bitshift)); } diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c index cc0bcaf13e96..73ef602bfb01 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/phy.c @@ -16,7 +16,6 @@ static u32 _rtl92ee_phy_rf_serial_read(struct ieee80211_hw *hw, static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw, enum radio_path rfpath, u32 offset, u32 data); -static u32 _rtl92ee_phy_calculate_bit_shift(u32 bitmask); static bool _rtl92ee_phy_bb8192ee_config_parafile(struct ieee80211_hw *hw); static bool _rtl92ee_phy_config_mac_with_headerfile(struct ieee80211_hw *hw); static bool phy_config_bb_with_hdr_file(struct ieee80211_hw *hw, @@ -46,7 +45,7 @@ u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask); originalvalue = rtl_read_dword(rtlpriv, regaddr); - bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); returnvalue = (originalvalue & bitmask) >> bitshift; rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, @@ -68,7 +67,7 @@ void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, if (bitmask != MASKDWORD) { originalvalue = rtl_read_dword(rtlpriv, regaddr); - bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((originalvalue & (~bitmask)) | (data << bitshift)); } @@ -92,7 +91,7 @@ u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw, spin_lock(&rtlpriv->locks.rf_lock); original_value = _rtl92ee_phy_rf_serial_read(hw , rfpath, regaddr); - bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); readback_value = (original_value & bitmask) >> bitshift; spin_unlock(&rtlpriv->locks.rf_lock); @@ -119,7 +118,7 @@ void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw, if (bitmask != RFREG_OFFSET_MASK) { original_value = _rtl92ee_phy_rf_serial_read(hw, rfpath, addr); - bitshift = _rtl92ee_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = (original_value & (~bitmask)) | (data << bitshift); } @@ -201,13 +200,6 @@ static void _rtl92ee_phy_rf_serial_write(struct ieee80211_hw *hw, pphyreg->rf3wire_offset, data_and_addr); } -static u32 _rtl92ee_phy_calculate_bit_shift(u32 bitmask) -{ - u32 i = ffs(bitmask); - - return i ? i - 1 : 32; -} - bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw) { return _rtl92ee_phy_config_mac_with_headerfile(hw); diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c index 09591a0b5a81..d9ef7e1da1db 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192se/phy.c @@ -14,13 +14,6 @@ #include "hw.h" #include "table.h" -static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask) -{ - u32 i = ffs(bitmask); - - return i ? i - 1 : 32; -} - u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) { struct rtl_priv *rtlpriv = rtl_priv(hw); @@ -30,7 +23,7 @@ u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask) regaddr, bitmask); originalvalue = rtl_read_dword(rtlpriv, regaddr); - bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); returnvalue = (originalvalue & bitmask) >> bitshift; rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n", @@ -52,7 +45,7 @@ void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, if (bitmask != MASKDWORD) { originalvalue = rtl_read_dword(rtlpriv, regaddr); - bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((originalvalue & (~bitmask)) | (data << bitshift)); } @@ -157,7 +150,7 @@ u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr); - bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); readback_value = (original_value & bitmask) >> bitshift; spin_unlock(&rtlpriv->locks.rf_lock); @@ -188,7 +181,7 @@ void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, if (bitmask != RFREG_OFFSET_MASK) { original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr); - bitshift = _rtl92s_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((original_value & (~bitmask)) | (data << bitshift)); } diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c index fe9b407dc2af..71e29b103da5 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/phy.c @@ -49,7 +49,7 @@ u32 rtl8723e_phy_query_rf_reg(struct ieee80211_hw *hw, rfpath, regaddr); } - bitshift = rtl8723_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); readback_value = (original_value & bitmask) >> bitshift; spin_unlock(&rtlpriv->locks.rf_lock); @@ -80,7 +80,7 @@ void rtl8723e_phy_set_rf_reg(struct ieee80211_hw *hw, original_value = rtl8723_phy_rf_serial_read(hw, rfpath, regaddr); - bitshift = rtl8723_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((original_value & (~bitmask)) | (data << bitshift)); @@ -89,7 +89,7 @@ void rtl8723e_phy_set_rf_reg(struct ieee80211_hw *hw, rtl8723_phy_rf_serial_write(hw, rfpath, regaddr, data); } else { if (bitmask != RFREG_OFFSET_MASK) { - bitshift = rtl8723_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((original_value & (~bitmask)) | (data << bitshift)); diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c index 2b9313cb93db..094cb36153f5 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723be/phy.c @@ -41,7 +41,7 @@ u32 rtl8723be_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath, spin_lock(&rtlpriv->locks.rf_lock); original_value = rtl8723_phy_rf_serial_read(hw, rfpath, regaddr); - bitshift = rtl8723_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); readback_value = (original_value & bitmask) >> bitshift; spin_unlock(&rtlpriv->locks.rf_lock); @@ -68,7 +68,7 @@ void rtl8723be_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path path, if (bitmask != RFREG_OFFSET_MASK) { original_value = rtl8723_phy_rf_serial_read(hw, path, regaddr); - bitshift = rtl8723_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((original_value & (~bitmask)) | (data << bitshift)); } diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c index 47b6c1aa36b0..d97c88ebce75 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.c @@ -17,7 +17,7 @@ u32 rtl8723_phy_query_bb_reg(struct ieee80211_hw *hw, rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask); originalvalue = rtl_read_dword(rtlpriv, regaddr); - bitshift = rtl8723_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); returnvalue = (originalvalue & bitmask) >> bitshift; rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, @@ -39,7 +39,7 @@ void rtl8723_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, if (bitmask != MASKDWORD) { originalvalue = rtl_read_dword(rtlpriv, regaddr); - bitshift = rtl8723_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((originalvalue & (~bitmask)) | (data << bitshift)); } @@ -51,14 +51,6 @@ void rtl8723_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, } EXPORT_SYMBOL_GPL(rtl8723_phy_set_bb_reg); -u32 rtl8723_phy_calculate_bit_shift(u32 bitmask) -{ - u32 i = ffs(bitmask); - - return i ? i - 1 : 32; -} -EXPORT_SYMBOL_GPL(rtl8723_phy_calculate_bit_shift); - u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw, enum radio_path rfpath, u32 offset) { diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.h b/drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.h index edf1c52f0ee2..af85c3287507 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.h +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723com/phy_common.h @@ -27,7 +27,6 @@ u32 rtl8723_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); void rtl8723_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, u32 data); -u32 rtl8723_phy_calculate_bit_shift(u32 bitmask); u32 rtl8723_phy_rf_serial_read(struct ieee80211_hw *hw, enum radio_path rfpath, u32 offset); void rtl8723_phy_rf_serial_write(struct ieee80211_hw *hw, diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c index 68c3fb0395ce..1be51ea3f3c8 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c @@ -27,13 +27,6 @@ static u32 _rtl8821ae_phy_rf_serial_read(struct ieee80211_hw *hw, static void _rtl8821ae_phy_rf_serial_write(struct ieee80211_hw *hw, enum radio_path rfpath, u32 offset, u32 data); -static u32 _rtl8821ae_phy_calculate_bit_shift(u32 bitmask) -{ - if (WARN_ON_ONCE(!bitmask)) - return 0; - - return __ffs(bitmask); -} static bool _rtl8821ae_phy_bb8821a_config_parafile(struct ieee80211_hw *hw); /*static bool _rtl8812ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);*/ static bool _rtl8821ae_phy_config_mac_with_headerfile(struct ieee80211_hw *hw); @@ -106,7 +99,7 @@ u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask); originalvalue = rtl_read_dword(rtlpriv, regaddr); - bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); returnvalue = (originalvalue & bitmask) >> bitshift; rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, @@ -127,7 +120,7 @@ void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw, if (bitmask != MASKDWORD) { originalvalue = rtl_read_dword(rtlpriv, regaddr); - bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((originalvalue & (~bitmask)) | ((data << bitshift) & bitmask)); } @@ -153,7 +146,7 @@ u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw, spin_lock(&rtlpriv->locks.rf_lock); original_value = _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr); - bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); readback_value = (original_value & bitmask) >> bitshift; spin_unlock(&rtlpriv->locks.rf_lock); @@ -181,7 +174,7 @@ void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw, if (bitmask != RFREG_OFFSET_MASK) { original_value = _rtl8821ae_phy_rf_serial_read(hw, rfpath, regaddr); - bitshift = _rtl8821ae_phy_calculate_bit_shift(bitmask); + bitshift = calculate_bit_shift(bitmask); data = ((original_value & (~bitmask)) | (data << bitshift)); } diff --git a/drivers/net/wireless/realtek/rtlwifi/wifi.h b/drivers/net/wireless/realtek/rtlwifi/wifi.h index ac8dfda7099d..d87cd2252eac 100644 --- a/drivers/net/wireless/realtek/rtlwifi/wifi.h +++ b/drivers/net/wireless/realtek/rtlwifi/wifi.h @@ -3052,4 +3052,11 @@ static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw, return ieee80211_find_sta(mac->vif, mac_addr); } +static inline u32 calculate_bit_shift(u32 bitmask) +{ + if (WARN_ON_ONCE(!bitmask)) + return 0; + + return __ffs(bitmask); +} #endif diff --git a/drivers/net/wireless/realtek/rtw88/fw.c b/drivers/net/wireless/realtek/rtw88/fw.c index acd78311c8c4..3f037ddcecf1 100644 --- a/drivers/net/wireless/realtek/rtw88/fw.c +++ b/drivers/net/wireless/realtek/rtw88/fw.c @@ -998,7 +998,7 @@ static u8 rtw_get_rsvd_page_probe_req_location(struct rtw_dev *rtwdev, if (rsvd_pkt->type != RSVD_PROBE_REQ) continue; if ((!ssid && !rsvd_pkt->ssid) || - rtw_ssid_equal(rsvd_pkt->ssid, ssid)) + cfg80211_ssid_eq(rsvd_pkt->ssid, ssid)) location = rsvd_pkt->page; } @@ -1015,7 +1015,7 @@ static u16 rtw_get_rsvd_page_probe_req_size(struct rtw_dev *rtwdev, if (rsvd_pkt->type != RSVD_PROBE_REQ) continue; if ((!ssid && !rsvd_pkt->ssid) || - rtw_ssid_equal(rsvd_pkt->ssid, ssid)) + cfg80211_ssid_eq(rsvd_pkt->ssid, ssid)) size = rsvd_pkt->probe_req_size; } diff --git a/drivers/net/wireless/realtek/rtw88/main.h b/drivers/net/wireless/realtek/rtw88/main.h index b6bfd4c02e2d..e14d1da43940 100644 --- a/drivers/net/wireless/realtek/rtw88/main.h +++ b/drivers/net/wireless/realtek/rtw88/main.h @@ -2090,18 +2090,6 @@ static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) return container_of(p, struct ieee80211_vif, drv_priv); } -static inline bool rtw_ssid_equal(struct cfg80211_ssid *a, - struct cfg80211_ssid *b) -{ - if (!a || !b || a->ssid_len != b->ssid_len) - return false; - - if (memcmp(a->ssid, b->ssid, a->ssid_len)) - return false; - - return true; -} - static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) { if (rtwdev->chip->ops->efuse_grant) diff --git a/drivers/net/wireless/realtek/rtw89/coex.c b/drivers/net/wireless/realtek/rtw89/coex.c index 9c0db35d3e13..f37afb4cbb63 100644 --- a/drivers/net/wireless/realtek/rtw89/coex.c +++ b/drivers/net/wireless/realtek/rtw89/coex.c @@ -6,6 +6,7 @@ #include "debug.h" #include "fw.h" #include "mac.h" +#include "phy.h" #include "ps.h" #include "reg.h" @@ -122,7 +123,8 @@ static const u32 cxtbl[] = { 0xea55556a, /* 21 */ 0xaafafafa, /* 22 */ 0xfafaaafa, /* 23 */ - 0xfafffaff /* 24 */ + 0xfafffaff, /* 24 */ + 0xea6a5a5a, /* 25 */ }; static const struct rtw89_btc_ver rtw89_btc_ver_defs[] = { @@ -131,7 +133,7 @@ static const struct rtw89_btc_ver rtw89_btc_ver_defs[] = { .fcxbtcrpt = 105, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 5, .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 2, .fcxgpiodbg = 1, .fcxbtver = 1, .fcxbtscan = 2, .fcxbtafh = 2, .fcxbtdevinfo = 1, - .fwlrole = 1, .frptmap = 3, .fcxctrl = 1, + .fwlrole = 2, .frptmap = 3, .fcxctrl = 1, .info_buf = 1800, .max_role_num = 6, }, {RTL8852C, RTW89_FW_VER_CODE(0, 27, 57, 0), @@ -159,7 +161,7 @@ static const struct rtw89_btc_ver rtw89_btc_ver_defs[] = { .fcxbtcrpt = 105, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 5, .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 2, .fcxgpiodbg = 1, .fcxbtver = 1, .fcxbtscan = 2, .fcxbtafh = 2, .fcxbtdevinfo = 1, - .fwlrole = 1, .frptmap = 3, .fcxctrl = 1, + .fwlrole = 2, .frptmap = 3, .fcxctrl = 1, .info_buf = 1800, .max_role_num = 6, }, {RTL8852B, RTW89_FW_VER_CODE(0, 29, 14, 0), @@ -246,6 +248,11 @@ struct rtw89_btc_btf_set_mon_reg { struct rtw89_btc_fbtc_mreg regs[] __counted_by(reg_num); } __packed; +struct _wl_rinfo_now { + u8 link_mode; + u32 dbcc_2g_phy: 2; +}; + enum btc_btf_set_cx_policy { CXPOLICY_TDMA = 0x0, CXPOLICY_SLOT = 0x1, @@ -262,6 +269,8 @@ enum btc_b2w_scoreboard { BTC_BSCB_RFK_RUN = BIT(5), BTC_BSCB_RFK_REQ = BIT(6), BTC_BSCB_LPS = BIT(7), + BTC_BSCB_BT_LNAB0 = BIT(8), + BTC_BSCB_BT_LNAB1 = BIT(10), BTC_BSCB_WLRFK = BIT(11), BTC_BSCB_BT_HILNA = BIT(13), BTC_BSCB_BT_CONNECT = BIT(16), @@ -405,11 +414,14 @@ enum btc_cx_poicy_type { /* TDMA Fix slot-8: W1:B1 = user-define */ BTC_CXP_FIX_TDW1B1 = (BTC_CXP_FIX << 8) | 8, - /* TDMA Fix slot-9: W1:B1 = 40:20 */ - BTC_CXP_FIX_TD4020 = (BTC_CXP_FIX << 8) | 9, - /* TDMA Fix slot-9: W1:B1 = 40:10 */ - BTC_CXP_FIX_TD4010ISO = (BTC_CXP_FIX << 8) | 10, + BTC_CXP_FIX_TD4010ISO = (BTC_CXP_FIX << 8) | 9, + + /* TDMA Fix slot-10: W1:B1 = 40:10 */ + BTC_CXP_FIX_TD4010ISO_DL = (BTC_CXP_FIX << 8) | 10, + + /* TDMA Fix slot-11: W1:B1 = 40:10 */ + BTC_CXP_FIX_TD4010ISO_UL = (BTC_CXP_FIX << 8) | 11, /* PS-TDMA Fix slot-0: W1:B1 = 30:30 */ BTC_CXP_PFIX_TD3030 = (BTC_CXP_PFIX << 8) | 0, @@ -710,7 +722,8 @@ static void _reset_btc_var(struct rtw89_dev *rtwdev, u8 type) if (type & BTC_RESET_CX) memset(cx, 0, sizeof(*cx)); - else if (type & BTC_RESET_BTINFO) /* only for BT enable */ + + if (type & BTC_RESET_BTINFO) /* only for BT enable */ memset(bt, 0, sizeof(*bt)); if (type & BTC_RESET_CTRL) { @@ -739,12 +752,115 @@ static void _reset_btc_var(struct rtw89_dev *rtwdev, u8 type) btc->dm.coex_info_map = BTC_COEX_INFO_ALL; btc->dm.wl_tx_limit.tx_time = BTC_MAX_TX_TIME_DEF; btc->dm.wl_tx_limit.tx_retry = BTC_MAX_TX_RETRY_DEF; + btc->dm.wl_pre_agc_rb = BTC_PREAGC_NOTFOUND; + btc->dm.wl_btg_rx_rb = BTC_BTGCTRL_BB_GNT_NOTFOUND; } if (type & BTC_RESET_MDINFO) memset(&btc->mdinfo, 0, sizeof(btc->mdinfo)); } +static u8 _search_reg_index(struct rtw89_dev *rtwdev, u8 mreg_num, u16 reg_type, u32 target) +{ + const struct rtw89_chip_info *chip = rtwdev->chip; + u8 i; + + for (i = 0; i < mreg_num; i++) + if (le16_to_cpu(chip->mon_reg[i].type) == reg_type && + le32_to_cpu(chip->mon_reg[i].offset) == target) { + return i; + } + return BTC_REG_NOTFOUND; +} + +static void _get_reg_status(struct rtw89_dev *rtwdev, u8 type, u8 *val) +{ + struct rtw89_btc *btc = &rtwdev->btc; + const struct rtw89_btc_ver *ver = btc->ver; + struct rtw89_btc_module *md = &btc->mdinfo; + union rtw89_btc_fbtc_mreg_val *pmreg; + u32 pre_agc_addr = R_BTC_BB_PRE_AGC_S1; + u32 reg_val; + u8 idx; + + if (md->ant.btg_pos == RF_PATH_A) + pre_agc_addr = R_BTC_BB_PRE_AGC_S0; + + switch (type) { + case BTC_CSTATUS_TXDIV_POS: + if (md->switch_type == BTC_SWITCH_INTERNAL) + *val = BTC_ANT_DIV_MAIN; + break; + case BTC_CSTATUS_RXDIV_POS: + if (md->switch_type == BTC_SWITCH_INTERNAL) + *val = BTC_ANT_DIV_MAIN; + break; + case BTC_CSTATUS_BB_GNT_MUX: + reg_val = rtw89_phy_read32(rtwdev, R_BTC_BB_BTG_RX); + *val = !(reg_val & B_BTC_BB_GNT_MUX); + break; + case BTC_CSTATUS_BB_GNT_MUX_MON: + if (!btc->fwinfo.rpt_fbtc_mregval.cinfo.valid) + return; + + pmreg = &btc->fwinfo.rpt_fbtc_mregval.finfo; + if (ver->fcxmreg == 1) { + idx = _search_reg_index(rtwdev, pmreg->v1.reg_num, + REG_BB, R_BTC_BB_BTG_RX); + if (idx == BTC_REG_NOTFOUND) { + *val = BTC_BTGCTRL_BB_GNT_NOTFOUND; + } else { + reg_val = le32_to_cpu(pmreg->v1.mreg_val[idx]); + *val = !(reg_val & B_BTC_BB_GNT_MUX); + } + } else if (ver->fcxmreg == 2) { + idx = _search_reg_index(rtwdev, pmreg->v2.reg_num, + REG_BB, R_BTC_BB_BTG_RX); + if (idx == BTC_REG_NOTFOUND) { + *val = BTC_BTGCTRL_BB_GNT_NOTFOUND; + } else { + reg_val = le32_to_cpu(pmreg->v2.mreg_val[idx]); + *val = !(reg_val & B_BTC_BB_GNT_MUX); + } + } + break; + case BTC_CSTATUS_BB_PRE_AGC: + reg_val = rtw89_phy_read32(rtwdev, pre_agc_addr); + reg_val &= B_BTC_BB_PRE_AGC_MASK; + *val = (reg_val == B_BTC_BB_PRE_AGC_VAL); + break; + case BTC_CSTATUS_BB_PRE_AGC_MON: + if (!btc->fwinfo.rpt_fbtc_mregval.cinfo.valid) + return; + + pmreg = &btc->fwinfo.rpt_fbtc_mregval.finfo; + if (ver->fcxmreg == 1) { + idx = _search_reg_index(rtwdev, pmreg->v1.reg_num, + REG_BB, pre_agc_addr); + if (idx == BTC_REG_NOTFOUND) { + *val = BTC_PREAGC_NOTFOUND; + } else { + reg_val = le32_to_cpu(pmreg->v1.mreg_val[idx]) & + B_BTC_BB_PRE_AGC_MASK; + *val = (reg_val == B_BTC_BB_PRE_AGC_VAL); + } + } else if (ver->fcxmreg == 2) { + idx = _search_reg_index(rtwdev, pmreg->v2.reg_num, + REG_BB, pre_agc_addr); + if (idx == BTC_REG_NOTFOUND) { + *val = BTC_PREAGC_NOTFOUND; + } else { + reg_val = le32_to_cpu(pmreg->v2.mreg_val[idx]) & + B_BTC_BB_PRE_AGC_MASK; + *val = (reg_val == B_BTC_BB_PRE_AGC_VAL); + } + } + break; + default: + break; + } +} + #define BTC_RPT_HDR_SIZE 3 #define BTC_CHK_WLSLOT_DRIFT_MAX 15 #define BTC_CHK_BTSLOT_DRIFT_MAX 15 @@ -1003,7 +1119,7 @@ static u32 _chk_btc_report(struct rtw89_dev *rtwdev, u16 wl_slot_set = 0, wl_slot_real = 0; u32 trace_step = btc->ctrl.trace_step, rpt_len = 0, diff_t = 0; u32 cnt_leak_slot, bt_slot_real, bt_slot_set, cnt_rx_imr; - u8 i; + u8 i, val = 0; rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): index:%d\n", @@ -1508,6 +1624,19 @@ static u32 _chk_btc_report(struct rtw89_dev *rtwdev, goto err; } break; + case BTC_RPT_TYPE_MREG: + _get_reg_status(rtwdev, BTC_CSTATUS_BB_GNT_MUX_MON, &val); + if (dm->wl_btg_rx == BTC_BTGCTRL_BB_GNT_FWCTRL) + dm->wl_btg_rx_rb = BTC_BTGCTRL_BB_GNT_FWCTRL; + else + dm->wl_btg_rx_rb = val; + + _get_reg_status(rtwdev, BTC_CSTATUS_BB_PRE_AGC_MON, &val); + if (dm->wl_pre_agc == BTC_PREAGC_BB_FWCTRL) + dm->wl_pre_agc_rb = BTC_PREAGC_BB_FWCTRL; + else + dm->wl_pre_agc_rb = val; + break; case BTC_RPT_TYPE_BT_VER: case BTC_RPT_TYPE_BT_SCAN: case BTC_RPT_TYPE_BT_AFH: @@ -2155,8 +2284,9 @@ static void _set_bt_rx_gain(struct rtw89_dev *rtwdev, u8 level) struct rtw89_btc *btc = &rtwdev->btc; struct rtw89_btc_bt_info *bt = &btc->cx.bt; - if (bt->rf_para.rx_gain_freerun == level || - level > BTC_BT_RX_NORMAL_LVL) + if ((bt->rf_para.rx_gain_freerun == level || + level > BTC_BT_RX_NORMAL_LVL) && + (!rtwdev->chip->scbd || bt->lna_constrain == level)) return; bt->rf_para.rx_gain_freerun = level; @@ -2171,32 +2301,59 @@ static void _set_bt_rx_gain(struct rtw89_dev *rtwdev, u8 level) else _write_scbd(rtwdev, BTC_WSCB_RXGAIN, true); - _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_LNA_CONSTRAIN, &level, 1); + _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_LNA_CONSTRAIN, &level, sizeof(level)); } static void _set_rf_trx_para(struct rtw89_dev *rtwdev) { const struct rtw89_chip_info *chip = rtwdev->chip; struct rtw89_btc *btc = &rtwdev->btc; + const struct rtw89_btc_ver *ver = btc->ver; struct rtw89_btc_dm *dm = &btc->dm; struct rtw89_btc_wl_info *wl = &btc->cx.wl; struct rtw89_btc_bt_info *bt = &btc->cx.bt; struct rtw89_btc_bt_link_info *b = &bt->link_info; + struct rtw89_btc_wl_smap *wl_smap = &wl->status.map; struct rtw89_btc_rf_trx_para para; u32 wl_stb_chg = 0; - u8 level_id = 0; + u8 level_id = 0, link_mode = 0, i, dbcc_2g_phy = 0; + + if (ver->fwlrole == 0) { + link_mode = wl->role_info.link_mode; + for (i = 0; i < RTW89_PHY_MAX; i++) { + if (wl->dbcc_info.real_band[i] == RTW89_BAND_2G) + dbcc_2g_phy = i; + } + } else if (ver->fwlrole == 1) { + link_mode = wl->role_info_v1.link_mode; + dbcc_2g_phy = wl->role_info_v1.dbcc_2g_phy; + } else if (ver->fwlrole == 2) { + link_mode = wl->role_info_v2.link_mode; + dbcc_2g_phy = wl->role_info_v2.dbcc_2g_phy; + } - if (!dm->freerun) { - /* fix LNA2 = level-5 for BT ACI issue at BTG */ + /* decide trx_para_level */ + if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { + /* fix LNA2 + TIA gain not change by GNT_BT */ if ((btc->dm.wl_btg_rx && b->profile_cnt.now != 0) || dm->bt_only == 1) - dm->trx_para_level = 1; + dm->trx_para_level = 1; /* for better BT ACI issue */ else dm->trx_para_level = 0; + } else { /* non-shared antenna */ + dm->trx_para_level = 5; + /* modify trx_para if WK 2.4G-STA-DL + bt link */ + if (b->profile_cnt.now != 0 && + link_mode == BTC_WLINK_2G_STA && + wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) { /* uplink */ + if (wl->rssi_level == 4 && bt->rssi_level > 2) + dm->trx_para_level = 6; + else if (wl->rssi_level == 3 && bt->rssi_level > 3) + dm->trx_para_level = 7; + } } - level_id = (u8)dm->trx_para_level; - + level_id = dm->trx_para_level; if (level_id >= chip->rf_para_dlink_num || level_id >= chip->rf_para_ulink_num) { rtw89_debug(rtwdev, RTW89_DBG_BTC, @@ -2210,25 +2367,26 @@ static void _set_rf_trx_para(struct rtw89_dev *rtwdev) else para = chip->rf_para_dlink[level_id]; - if (para.wl_tx_power != RTW89_BTC_WL_DEF_TX_PWR) - rtw89_debug(rtwdev, RTW89_DBG_BTC, - "[BTC], %s(): wl_tx_power=%d\n", - __func__, para.wl_tx_power); - _set_wl_tx_power(rtwdev, para.wl_tx_power); - _set_wl_rx_gain(rtwdev, para.wl_rx_gain); - _set_bt_tx_power(rtwdev, para.bt_tx_power); - _set_bt_rx_gain(rtwdev, para.bt_rx_gain); - - if (bt->enable.now == 0 || wl->status.map.rf_off == 1 || - wl->status.map.lps == BTC_LPS_RF_OFF) + if (dm->fddt_train) { + _set_wl_rx_gain(rtwdev, 1); + _write_scbd(rtwdev, BTC_WSCB_RXGAIN, true); + } else { + _set_wl_tx_power(rtwdev, para.wl_tx_power); + _set_wl_rx_gain(rtwdev, para.wl_rx_gain); + _set_bt_tx_power(rtwdev, para.bt_tx_power); + _set_bt_rx_gain(rtwdev, para.bt_rx_gain); + } + + if (!bt->enable.now || dm->wl_only || wl_smap->rf_off || + wl_smap->lps == BTC_LPS_RF_OFF || + link_mode == BTC_WLINK_5G || + link_mode == BTC_WLINK_NOLINK || + (rtwdev->dbcc_en && dbcc_2g_phy != RTW89_PHY_1)) wl_stb_chg = 0; else wl_stb_chg = 1; if (wl_stb_chg != dm->wl_stb_chg) { - rtw89_debug(rtwdev, RTW89_DBG_BTC, - "[BTC], %s(): wl_stb_chg=%d\n", - __func__, wl_stb_chg); dm->wl_stb_chg = wl_stb_chg; chip->ops->btc_wl_s1_standby(rtwdev, dm->wl_stb_chg); } @@ -2661,9 +2819,17 @@ void rtw89_btc_set_policy(struct rtw89_dev *rtwdev, u16 policy_type) _slot_set(btc, CXST_W1, 40, tbl_w1, SLOT_ISO); _slot_set(btc, CXST_B1, 10, tbl_b1, SLOT_MIX); break; - case BTC_CXP_FIX_TD4020: - _slot_set(btc, CXST_W1, 40, cxtbl[1], SLOT_MIX); - _slot_set(btc, CXST_B1, 20, tbl_b1, SLOT_MIX); + case BTC_CXP_FIX_TD4010ISO: + _slot_set(btc, CXST_W1, 40, cxtbl[1], SLOT_ISO); + _slot_set(btc, CXST_B1, 10, tbl_b1, SLOT_MIX); + break; + case BTC_CXP_FIX_TD4010ISO_DL: + _slot_set(btc, CXST_W1, 40, cxtbl[25], SLOT_ISO); + _slot_set(btc, CXST_B1, 10, cxtbl[25], SLOT_ISO); + break; + case BTC_CXP_FIX_TD4010ISO_UL: + _slot_set(btc, CXST_W1, 40, cxtbl[20], SLOT_ISO); + _slot_set(btc, CXST_B1, 10, cxtbl[25], SLOT_MIX); break; case BTC_CXP_FIX_TD7010: _slot_set(btc, CXST_W1, 70, tbl_w1, SLOT_ISO); @@ -3002,9 +3168,13 @@ void rtw89_btc_set_policy_v1(struct rtw89_dev *rtwdev, u16 policy_type) _slot_set(btc, CXST_W1, 40, cxtbl[1], SLOT_ISO); _slot_set(btc, CXST_B1, 10, tbl_b1, SLOT_MIX); break; - case BTC_CXP_FIX_TD4020: - _slot_set(btc, CXST_W1, 40, cxtbl[1], SLOT_MIX); - _slot_set(btc, CXST_B1, 20, tbl_b1, SLOT_MIX); + case BTC_CXP_FIX_TD4010ISO_DL: + _slot_set(btc, CXST_W1, 40, cxtbl[25], SLOT_ISO); + _slot_set(btc, CXST_B1, 10, cxtbl[25], SLOT_ISO); + break; + case BTC_CXP_FIX_TD4010ISO_UL: + _slot_set(btc, CXST_W1, 40, cxtbl[20], SLOT_ISO); + _slot_set(btc, CXST_B1, 10, cxtbl[25], SLOT_MIX); break; case BTC_CXP_FIX_TD7010: _slot_set(btc, CXST_W1, 70, tbl_w1, SLOT_ISO); @@ -3381,17 +3551,32 @@ static void _action_wl_init(struct rtw89_dev *rtwdev) _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_INIT); } -static void _action_wl_off(struct rtw89_dev *rtwdev) +static void _action_wl_off(struct rtw89_dev *rtwdev, u8 mode) { struct rtw89_btc *btc = &rtwdev->btc; struct rtw89_btc_wl_info *wl = &btc->cx.wl; rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); - if (wl->status.map.rf_off || btc->dm.bt_only) + if (wl->status.map.rf_off || btc->dm.bt_only) { _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_WOFF); + } else if (wl->status.map.lps == BTC_LPS_RF_ON) { + if (wl->role_info.link_mode == BTC_WLINK_5G) + _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_W5G); + else + _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); + } - _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_OFF); + if (mode == BTC_WLINK_5G) { + _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_OFF); + } else if (wl->status.map.lps == BTC_LPS_RF_ON) { + if (btc->cx.bt.link_info.a2dp_desc.active) + _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_OFF); + else + _set_policy(rtwdev, BTC_CXP_OFF_BWB1, BTC_ACT_WL_OFF); + } else { + _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_OFF); + } } static void _action_freerun(struct rtw89_dev *rtwdev) @@ -3426,31 +3611,25 @@ static void _action_bt_idle(struct rtw89_dev *rtwdev) { struct rtw89_btc *btc = &rtwdev->btc; struct rtw89_btc_bt_link_info *b = &btc->cx.bt.link_info; + struct rtw89_btc_wl_info *wl = &btc->cx.wl; _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); if (btc->mdinfo.ant.type == BTC_ANT_SHARED) { /* shared-antenna */ switch (btc->cx.state_map) { case BTC_WBUSY_BNOSCAN: /*wl-busy + bt idle*/ - if (b->profile_cnt.now > 0) - _set_policy(rtwdev, BTC_CXP_FIX_TD4010, - BTC_ACT_BT_IDLE); + case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-idle */ + if (b->status.map.connect) + _set_policy(rtwdev, BTC_CXP_FIX_TD4010, BTC_ACT_BT_IDLE); + else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_DL)) + _set_policy(rtwdev, BTC_CXP_FIX_TD4010ISO_DL, BTC_ACT_BT_IDLE); else - _set_policy(rtwdev, BTC_CXP_FIX_TD4020, - BTC_ACT_BT_IDLE); + _set_policy(rtwdev, BTC_CXP_FIX_TD4010ISO_UL, BTC_ACT_BT_IDLE); break; case BTC_WBUSY_BSCAN: /*wl-busy + bt-inq */ _set_policy(rtwdev, BTC_CXP_PFIX_TD5050, BTC_ACT_BT_IDLE); break; - case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-idle */ - if (b->profile_cnt.now > 0) - _set_policy(rtwdev, BTC_CXP_FIX_TD4010, - BTC_ACT_BT_IDLE); - else - _set_policy(rtwdev, BTC_CXP_FIX_TD4020, - BTC_ACT_BT_IDLE); - break; case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq */ _set_policy(rtwdev, BTC_CXP_FIX_TD5050, BTC_ACT_BT_IDLE); @@ -3617,7 +3796,7 @@ static void _action_bt_pan(struct rtw89_dev *rtwdev) _set_policy(rtwdev, BTC_CXP_FIX_TD3060, BTC_ACT_BT_PAN); break; case BTC_WLINKING: /* wl-connecting + bt-PAN */ - _set_policy(rtwdev, BTC_CXP_FIX_TD4020, BTC_ACT_BT_PAN); + _set_policy(rtwdev, BTC_CXP_FIX_TD4010ISO, BTC_ACT_BT_PAN); break; case BTC_WIDLE: /* wl-idle + bt-pan */ _set_policy(rtwdev, BTC_CXP_PFIX_TD2080, BTC_ACT_BT_PAN); @@ -3798,46 +3977,134 @@ static void _action_wl_rfk(struct rtw89_dev *rtwdev) static void _set_btg_ctrl(struct rtw89_dev *rtwdev) { struct rtw89_btc *btc = &rtwdev->btc; - const struct rtw89_btc_ver *ver = btc->ver; struct rtw89_btc_wl_info *wl = &btc->cx.wl; - struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; struct rtw89_btc_wl_role_info_v1 *wl_rinfo_v1 = &wl->role_info_v1; struct rtw89_btc_wl_role_info_v2 *wl_rinfo_v2 = &wl->role_info_v2; + struct rtw89_btc_wl_role_info *wl_rinfo_v0 = &wl->role_info; struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; - bool is_btg; - u8 mode; + const struct rtw89_chip_info *chip = rtwdev->chip; + const struct rtw89_btc_ver *ver = btc->ver; + struct rtw89_btc_bt_info *bt = &btc->cx.bt; + struct rtw89_btc_dm *dm = &btc->dm; + struct _wl_rinfo_now wl_rinfo; + u32 run_reason = btc->dm.run_reason; + u32 is_btg; + u8 i, val; if (btc->ctrl.manual) return; if (ver->fwlrole == 0) - mode = wl_rinfo->link_mode; + wl_rinfo.link_mode = wl_rinfo_v0->link_mode; else if (ver->fwlrole == 1) - mode = wl_rinfo_v1->link_mode; + wl_rinfo.link_mode = wl_rinfo_v1->link_mode; else if (ver->fwlrole == 2) - mode = wl_rinfo_v2->link_mode; + wl_rinfo.link_mode = wl_rinfo_v2->link_mode; else return; - /* notify halbb ignore GNT_BT or not for WL BB Rx-AGC control */ - if (mode == BTC_WLINK_5G) /* always 0 if 5G */ - is_btg = false; - else if (mode == BTC_WLINK_25G_DBCC && - wl_dinfo->real_band[RTW89_PHY_1] != RTW89_BAND_2G) - is_btg = false; + if (rtwdev->dbcc_en) { + if (ver->fwlrole == 0) { + for (i = 0; i < RTW89_PHY_MAX; i++) { + if (wl_dinfo->real_band[i] == RTW89_BAND_2G) + wl_rinfo.dbcc_2g_phy = i; + } + } else if (ver->fwlrole == 1) { + wl_rinfo.dbcc_2g_phy = wl_rinfo_v1->dbcc_2g_phy; + } else if (ver->fwlrole == 2) { + wl_rinfo.dbcc_2g_phy = wl_rinfo_v2->dbcc_2g_phy; + } else { + return; + } + } + + if (wl_rinfo.link_mode == BTC_WLINK_25G_MCC) + is_btg = BTC_BTGCTRL_BB_GNT_FWCTRL; + else if (!(bt->run_patch_code && bt->enable.now)) + is_btg = BTC_BTGCTRL_DISABLE; + else if (wl_rinfo.link_mode == BTC_WLINK_5G) + is_btg = BTC_BTGCTRL_DISABLE; + else if (dm->freerun) + is_btg = BTC_BTGCTRL_DISABLE; + else if (rtwdev->dbcc_en && wl_rinfo.dbcc_2g_phy != RTW89_PHY_1) + is_btg = BTC_BTGCTRL_DISABLE; else - is_btg = true; + is_btg = BTC_BTGCTRL_ENABLE; - if (btc->dm.run_reason != BTC_RSN_NTFY_INIT && - is_btg == btc->dm.wl_btg_rx) - return; + if (dm->wl_btg_rx_rb != dm->wl_btg_rx && + dm->wl_btg_rx_rb != BTC_BTGCTRL_BB_GNT_NOTFOUND) { + _get_reg_status(rtwdev, BTC_CSTATUS_BB_GNT_MUX, &val); + dm->wl_btg_rx_rb = val; + } + + if (run_reason == BTC_RSN_NTFY_INIT || + run_reason == BTC_RSN_NTFY_SWBAND || + dm->wl_btg_rx_rb != dm->wl_btg_rx || + is_btg != dm->wl_btg_rx) { + + dm->wl_btg_rx = is_btg; - btc->dm.wl_btg_rx = is_btg; + if (is_btg > BTC_BTGCTRL_ENABLE) + return; + + chip->ops->ctrl_btg_bt_rx(rtwdev, is_btg, RTW89_PHY_0); + } +} - if (mode == BTC_WLINK_25G_MCC) +static void _set_wl_preagc_ctrl(struct rtw89_dev *rtwdev) +{ + struct rtw89_btc *btc = &rtwdev->btc; + struct rtw89_btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; + struct rtw89_btc_wl_info *wl = &btc->cx.wl; + struct rtw89_btc_wl_role_info_v2 *wl_rinfo = &wl->role_info_v2; + const struct rtw89_chip_info *chip = rtwdev->chip; + const struct rtw89_btc_ver *ver = btc->ver; + struct rtw89_btc_bt_info *bt = &btc->cx.bt; + struct rtw89_btc_dm *dm = &btc->dm; + u8 is_preagc, val; + + if (btc->ctrl.manual) return; - rtw89_ctrl_btg_bt_rx(rtwdev, is_btg, RTW89_PHY_0); + if (wl_rinfo->link_mode == BTC_WLINK_25G_MCC) + is_preagc = BTC_PREAGC_BB_FWCTRL; + else if (!(bt->run_patch_code && bt->enable.now)) + is_preagc = BTC_PREAGC_DISABLE; + else if (wl_rinfo->link_mode == BTC_WLINK_5G) + is_preagc = BTC_PREAGC_DISABLE; + else if (wl_rinfo->link_mode == BTC_WLINK_NOLINK || + btc->cx.bt.link_info.profile_cnt.now == 0) + is_preagc = BTC_PREAGC_DISABLE; + else if (dm->tdma_now.type != CXTDMA_OFF && + !bt_linfo->hfp_desc.exist && + !bt_linfo->hid_desc.exist && + dm->fddt_train == BTC_FDDT_DISABLE) + is_preagc = BTC_PREAGC_DISABLE; + else if (ver->fwlrole == 2 && wl_rinfo->dbcc_en && + wl_rinfo->dbcc_2g_phy != RTW89_PHY_1) + is_preagc = BTC_PREAGC_DISABLE; + else if (btc->mdinfo.ant.type == BTC_ANT_SHARED) + is_preagc = BTC_PREAGC_DISABLE; + else + is_preagc = BTC_PREAGC_ENABLE; + + if (dm->wl_pre_agc_rb != dm->wl_pre_agc && + dm->wl_pre_agc_rb != BTC_PREAGC_NOTFOUND) { + _get_reg_status(rtwdev, BTC_CSTATUS_BB_PRE_AGC, &val); + dm->wl_pre_agc_rb = val; + } + + if ((wl->coex_mode == BTC_MODE_NORMAL && + (dm->run_reason == BTC_RSN_NTFY_INIT || + dm->run_reason == BTC_RSN_NTFY_SWBAND || + dm->wl_pre_agc_rb != dm->wl_pre_agc)) || + is_preagc != dm->wl_pre_agc) { + dm->wl_pre_agc = is_preagc; + + if (is_preagc > BTC_PREAGC_ENABLE) + return; + chip->ops->ctrl_nbtg_bt_tx(rtwdev, dm->wl_pre_agc, RTW89_PHY_0); + } } struct rtw89_txtime_data { @@ -4024,6 +4291,7 @@ static void _action_common(struct rtw89_dev *rtwdev) struct rtw89_btc_wl_info *wl = &btc->cx.wl; _set_btg_ctrl(rtwdev); + _set_wl_preagc_ctrl(rtwdev); _set_wl_tx_limit(rtwdev); _set_bt_afh_info(rtwdev); _set_bt_rx_agc(rtwdev); @@ -5008,8 +5276,7 @@ static void _update_bt_scbd(struct rtw89_dev *rtwdev, bool only_update) return; } - if (!(val & BTC_BSCB_ON) || - btc->dm.cnt_dm[BTC_DCNT_BTCNT_HANG] >= BTC_CHK_HANG_MAX) + if (!(val & BTC_BSCB_ON)) bt->enable.now = 0; else bt->enable.now = 1; @@ -5035,6 +5302,9 @@ static void _update_bt_scbd(struct rtw89_dev *rtwdev, bool only_update) bt->btg_type = val & BTC_BSCB_BT_S1 ? BTC_BT_BTG : BTC_BT_ALONE; bt->link_info.a2dp_desc.exist = !!(val & BTC_BSCB_A2DP_ACT); + bt->lna_constrain = !!(val & BTC_BSCB_BT_LNAB0) + + !!(val & BTC_BSCB_BT_LNAB1) * 2 + 4; + /* if rfk run 1->0 */ if (bt->rfk_info.map.run && !(val & BTC_BSCB_RFK_RUN)) status_change = true; @@ -5128,17 +5398,28 @@ void _run_coex(struct rtw89_dev *rtwdev, enum btc_reason_and_action reason) } if (wl->status.map.rf_off_pre == wl->status.map.rf_off && - wl->status.map.lps_pre == wl->status.map.lps && - (reason == BTC_RSN_NTFY_POWEROFF || - reason == BTC_RSN_NTFY_RADIO_STATE)) { - rtw89_debug(rtwdev, RTW89_DBG_BTC, - "[BTC], %s(): return for WL rf off state no change!!\n", - __func__); - return; + wl->status.map.lps_pre == wl->status.map.lps) { + if (reason == BTC_RSN_NTFY_POWEROFF || + reason == BTC_RSN_NTFY_RADIO_STATE) { + rtw89_debug(rtwdev, RTW89_DBG_BTC, + "[BTC], %s(): return for WL rf off state no change!!\n", + __func__); + return; + } + if (wl->status.map.rf_off == 1 || + wl->status.map.lps == BTC_LPS_RF_OFF) { + rtw89_debug(rtwdev, RTW89_DBG_BTC, + "[BTC], %s(): return for WL rf off state!!\n", + __func__); + return; + } } + dm->freerun = false; dm->cnt_dm[BTC_DCNT_RUN]++; dm->fddt_train = BTC_FDDT_DISABLE; + btc->ctrl.igno_bt = false; + bt->scan_rx_low_pri = false; if (btc->ctrl.always_freerun) { _action_freerun(rtwdev); @@ -5153,15 +5434,11 @@ void _run_coex(struct rtw89_dev *rtwdev, enum btc_reason_and_action reason) } if (wl->status.map.rf_off || wl->status.map.lps || dm->bt_only) { - _action_wl_off(rtwdev); + _action_wl_off(rtwdev, mode); btc->ctrl.igno_bt = true; goto exit; } - btc->ctrl.igno_bt = false; - dm->freerun = false; - bt->scan_rx_low_pri = false; - if (reason == BTC_RSN_NTFY_INIT) { _action_wl_init(rtwdev); goto exit; @@ -5186,12 +5463,14 @@ void _run_coex(struct rtw89_dev *rtwdev, enum btc_reason_and_action reason) if (mode == BTC_WLINK_NOLINK || mode == BTC_WLINK_2G_STA || mode == BTC_WLINK_5G) { _action_wl_scan(rtwdev); + bt->scan_rx_low_pri = false; goto exit; } } if (wl->status.map.scan) { _action_wl_scan(rtwdev); + bt->scan_rx_low_pri = false; goto exit; } @@ -5308,6 +5587,7 @@ void rtw89_btc_ntfy_init(struct rtw89_dev *rtwdev, u8 mode) rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): mode=%d\n", __func__, mode); + wl->coex_mode = mode; dm->cnt_notify[BTC_NCNT_INIT_COEX]++; dm->wl_only = mode == BTC_MODE_WL ? 1 : 0; dm->bt_only = mode == BTC_MODE_BT ? 1 : 0; @@ -5525,6 +5805,37 @@ void rtw89_btc_ntfy_icmp_packet_work(struct work_struct *work) mutex_unlock(&rtwdev->mutex); } +static u8 _update_bt_rssi_level(struct rtw89_dev *rtwdev, u8 rssi) +{ + const struct rtw89_chip_info *chip = rtwdev->chip; + struct rtw89_btc *btc = &rtwdev->btc; + struct rtw89_btc_bt_info *bt = &btc->cx.bt; + u8 *rssi_st, rssi_th, rssi_level = 0; + u8 i; + + /* for rssi locate in which {40, 36, 31, 28} + * if rssi >= 40% (-60dBm) --> rssi_level = 4 + * if 36% <= rssi < 40% --> rssi_level = 3 + * if 31% <= rssi < 36% --> rssi_level = 2 + * if 28% <= rssi < 31% --> rssi_level = 1 + * if rssi < 28% --> rssi_level = 0 + */ + + /* check if rssi across bt_rssi_thres boundary */ + for (i = 0; i < BTC_BT_RSSI_THMAX; i++) { + rssi_th = chip->bt_rssi_thres[i]; + rssi_st = &bt->link_info.rssi_state[i]; + + *rssi_st = _update_rssi_state(rtwdev, *rssi_st, rssi, rssi_th); + + if (BTC_RSSI_HIGH(*rssi_st)) { + rssi_level = BTC_BT_RSSI_THMAX - i; + break; + } + } + return rssi_level; +} + #define BT_PROFILE_PROTOCOL_MASK GENMASK(7, 4) static void _update_bt_info(struct rtw89_dev *rtwdev, u8 *buf, u32 len) @@ -5600,7 +5911,8 @@ static void _update_bt_info(struct rtw89_dev *rtwdev, u8 *buf, u32 len) btinfo.val = bt->raw_info[BTC_BTINFO_H0]; /* raw val is dBm unit, translate from -100~ 0dBm to 0~100%*/ b->rssi = chip->ops->btc_get_bt_rssi(rtwdev, btinfo.hb0.rssi); - btc->dm.trx_info.bt_rssi = b->rssi; + bt->rssi_level = _update_bt_rssi_level(rtwdev, b->rssi); + btc->dm.trx_info.bt_rssi = bt->rssi_level; /* parse raw info high-Byte1 */ btinfo.val = bt->raw_info[BTC_BTINFO_H1]; @@ -5804,22 +6116,22 @@ void rtw89_btc_ntfy_radio_state(struct rtw89_dev *rtwdev, enum btc_rfctrl rf_sta chip->ops->btc_init_cfg(rtwdev); } else { rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_ALL, false); - if (rf_state == BTC_RFCTRL_WL_OFF) + if (rf_state == BTC_RFCTRL_FW_CTRL) + _write_scbd(rtwdev, BTC_WSCB_ACTIVE, false); + else if (rf_state == BTC_RFCTRL_WL_OFF) _write_scbd(rtwdev, BTC_WSCB_ALL, false); - else if (rf_state == BTC_RFCTRL_LPS_WL_ON && - wl->status.map.lps_pre != BTC_LPS_OFF) + else + _write_scbd(rtwdev, BTC_WSCB_ACTIVE, false); + + if (rf_state == BTC_RFCTRL_LPS_WL_ON && + wl->status.map.lps_pre != BTC_LPS_OFF) _update_bt_scbd(rtwdev, true); } btc->dm.cnt_dm[BTC_DCNT_BTCNT_HANG] = 0; - if (wl->status.map.lps_pre == BTC_LPS_OFF && - wl->status.map.lps_pre != wl->status.map.lps) - btc->dm.tdma_instant_excute = 1; - else - btc->dm.tdma_instant_excute = 0; + btc->dm.tdma_instant_excute = 1; _run_coex(rtwdev, BTC_RSN_NTFY_RADIO_STATE); - btc->dm.tdma_instant_excute = 0; wl->status.map.rf_off_pre = wl->status.map.rf_off; wl->status.map.lps_pre = wl->status.map.lps; } @@ -6058,6 +6370,13 @@ static void rtw89_btc_ntfy_wl_sta_iter(void *data, struct ieee80211_sta *sta) dm->trx_info.tx_tp = link_info_t->tx_throughput; dm->trx_info.rx_tp = link_info_t->rx_throughput; + /* Trigger coex-run if 0x10980 reg-value is diff with coex setup */ + if ((dm->wl_btg_rx_rb != dm->wl_btg_rx && + dm->wl_btg_rx_rb != BTC_BTGCTRL_BB_GNT_NOTFOUND) || + (dm->wl_pre_agc_rb != dm->wl_pre_agc && + dm->wl_pre_agc_rb != BTC_PREAGC_NOTFOUND)) + iter_data->is_sta_change = true; + if (is_sta_change) iter_data->is_sta_change = true; @@ -6443,8 +6762,9 @@ static void _show_bt_info(struct rtw89_dev *rtwdev, struct seq_file *m) bt_linfo->pan_desc.active ? "Y" : "N"); seq_printf(m, - " %-15s : rssi:%ddBm, tx_rate:%dM, %s%s%s", + " %-15s : rssi:%ddBm(lvl:%d), tx_rate:%dM, %s%s%s", "[link]", bt_linfo->rssi - 100, + bt->rssi_level, bt_linfo->tx_3m ? 3 : 2, bt_linfo->status.map.inq_pag ? " inq-page!!" : "", bt_linfo->status.map.acl_busy ? " acl_busy!!" : "", @@ -6553,6 +6873,8 @@ static void _show_bt_info(struct rtw89_dev *rtwdev, struct seq_file *m) case BTC_CXP_ ## e | BTC_POLICY_EXT_BIT: return #e #define CASE_BTC_SLOT_STR(e) case CXST_ ## e: return #e #define CASE_BTC_EVT_STR(e) case CXEVNT_## e: return #e +#define CASE_BTC_INIT(e) case BTC_MODE_## e: return #e +#define CASE_BTC_ANTPATH_STR(e) case BTC_ANT_##e: return #e static const char *steps_to_str(u16 step) { @@ -6633,8 +6955,9 @@ static const char *steps_to_str(u16 step) CASE_BTC_POLICY_STR(FIX_TD3060); CASE_BTC_POLICY_STR(FIX_TD2080); CASE_BTC_POLICY_STR(FIX_TDW1B1); - CASE_BTC_POLICY_STR(FIX_TD4020); CASE_BTC_POLICY_STR(FIX_TD4010ISO); + CASE_BTC_POLICY_STR(FIX_TD4010ISO_DL); + CASE_BTC_POLICY_STR(FIX_TD4010ISO_UL); CASE_BTC_POLICY_STR(PFIX_TD3030); CASE_BTC_POLICY_STR(PFIX_TD5050); CASE_BTC_POLICY_STR(PFIX_TD2030); @@ -6727,6 +7050,37 @@ static const char *id_to_evt(u32 id) } } +static const char *id_to_mode(u8 id) +{ + switch (id) { + CASE_BTC_INIT(NORMAL); + CASE_BTC_INIT(WL); + CASE_BTC_INIT(BT); + CASE_BTC_INIT(WLOFF); + default: + return "unknown"; + } +} + +static const char *id_to_ant(u32 id) +{ + switch (id) { + CASE_BTC_ANTPATH_STR(WPOWERON); + CASE_BTC_ANTPATH_STR(WINIT); + CASE_BTC_ANTPATH_STR(WONLY); + CASE_BTC_ANTPATH_STR(WOFF); + CASE_BTC_ANTPATH_STR(W2G); + CASE_BTC_ANTPATH_STR(W5G); + CASE_BTC_ANTPATH_STR(W25G); + CASE_BTC_ANTPATH_STR(FREERUN); + CASE_BTC_ANTPATH_STR(WRFK); + CASE_BTC_ANTPATH_STR(BRFK); + CASE_BTC_ANTPATH_STR(MAX); + default: + return "unknown"; + } +} + static void seq_print_segment(struct seq_file *m, const char *prefix, u16 *data, u8 len, u8 seg_len, u8 start_idx, u8 ring_len) @@ -6781,12 +7135,13 @@ static void _show_dm_info(struct rtw89_dev *rtwdev, struct seq_file *m) (btc->ctrl.manual ? "(Manual)" : "(Auto)")); seq_printf(m, - " %-15s : type:%s, reason:%s(), action:%s(), ant_path:%ld, run_cnt:%d\n", + " %-15s : type:%s, reason:%s(), action:%s(), ant_path:%s, init_mode:%s, run_cnt:%d\n", "[status]", module->ant.type == BTC_ANT_SHARED ? "shared" : "dedicated", steps_to_str(dm->run_reason), steps_to_str(dm->run_action | BTC_ACT_EXT_BIT), - FIELD_GET(GENMASK(7, 0), dm->set_ant_path), + id_to_ant(FIELD_GET(GENMASK(7, 0), dm->set_ant_path)), + id_to_mode(wl->coex_mode), dm->cnt_dm[BTC_DCNT_RUN]); _show_dm_step(rtwdev, m); @@ -7689,7 +8044,8 @@ static void _get_gnt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_coex_gnt *gnt struct rtw89_mac_ax_gnt *gnt; u32 val, status; - if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) { + if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || + chip->chip_id == RTL8851B) { rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_1, &val); rtw89_mac_read_lte(rtwdev, R_AX_GNT_VAL, &status); @@ -7751,27 +8107,25 @@ static void _show_mreg_v1(struct rtw89_dev *rtwdev, struct seq_file *m) bt->scbd, cx->cnt_bt[BTC_BCNT_SCBDREAD], cx->cnt_bt[BTC_BCNT_SCBDUPDATE]); - /* To avoid I/O if WL LPS or power-off */ - if (!wl->status.map.lps && !wl->status.map.rf_off) { - btc->dm.pta_owner = rtw89_mac_get_ctrl_path(rtwdev); + btc->dm.pta_owner = rtw89_mac_get_ctrl_path(rtwdev); + _get_gnt(rtwdev, &gnt_cfg); + + gnt = gnt_cfg.band[0]; + seq_printf(m, + " %-15s : pta_owner:%s, phy-0[gnt_wl:%s-%d/gnt_bt:%s-%d], ", + "[gnt_status]", + chip->chip_id == RTL8852C ? "HW" : + btc->dm.pta_owner == BTC_CTRL_BY_WL ? "WL" : "BT", + gnt.gnt_wl_sw_en ? "SW" : "HW", gnt.gnt_wl, + gnt.gnt_bt_sw_en ? "SW" : "HW", gnt.gnt_bt); + + gnt = gnt_cfg.band[1]; + seq_printf(m, "phy-1[gnt_wl:%s-%d/gnt_bt:%s-%d]\n", + gnt.gnt_wl_sw_en ? "SW" : "HW", + gnt.gnt_wl, + gnt.gnt_bt_sw_en ? "SW" : "HW", + gnt.gnt_bt); - _get_gnt(rtwdev, &gnt_cfg); - gnt = gnt_cfg.band[0]; - seq_printf(m, - " %-15s : pta_owner:%s, phy-0[gnt_wl:%s-%d/gnt_bt:%s-%d], ", - "[gnt_status]", - chip->chip_id == RTL8852C ? "HW" : - btc->dm.pta_owner == BTC_CTRL_BY_WL ? "WL" : "BT", - gnt.gnt_wl_sw_en ? "SW" : "HW", gnt.gnt_wl, - gnt.gnt_bt_sw_en ? "SW" : "HW", gnt.gnt_bt); - - gnt = gnt_cfg.band[1]; - seq_printf(m, "phy-1[gnt_wl:%s-%d/gnt_bt:%s-%d]\n", - gnt.gnt_wl_sw_en ? "SW" : "HW", - gnt.gnt_wl, - gnt.gnt_bt_sw_en ? "SW" : "HW", - gnt.gnt_bt); - } pcinfo = &pfwinfo->rpt_fbtc_mregval.cinfo; if (!pcinfo->valid) { rtw89_debug(rtwdev, RTW89_DBG_BTC, @@ -7855,27 +8209,25 @@ static void _show_mreg_v2(struct rtw89_dev *rtwdev, struct seq_file *m) bt->scbd, cx->cnt_bt[BTC_BCNT_SCBDREAD], cx->cnt_bt[BTC_BCNT_SCBDUPDATE]); - /* To avoid I/O if WL LPS or power-off */ - if (!wl->status.map.lps && !wl->status.map.rf_off) { - btc->dm.pta_owner = rtw89_mac_get_ctrl_path(rtwdev); + btc->dm.pta_owner = rtw89_mac_get_ctrl_path(rtwdev); + _get_gnt(rtwdev, &gnt_cfg); + + gnt = gnt_cfg.band[0]; + seq_printf(m, + " %-15s : pta_owner:%s, phy-0[gnt_wl:%s-%d/gnt_bt:%s-%d], ", + "[gnt_status]", + chip->chip_id == RTL8852C ? "HW" : + btc->dm.pta_owner == BTC_CTRL_BY_WL ? "WL" : "BT", + gnt.gnt_wl_sw_en ? "SW" : "HW", gnt.gnt_wl, + gnt.gnt_bt_sw_en ? "SW" : "HW", gnt.gnt_bt); + + gnt = gnt_cfg.band[1]; + seq_printf(m, "phy-1[gnt_wl:%s-%d/gnt_bt:%s-%d]\n", + gnt.gnt_wl_sw_en ? "SW" : "HW", + gnt.gnt_wl, + gnt.gnt_bt_sw_en ? "SW" : "HW", + gnt.gnt_bt); - _get_gnt(rtwdev, &gnt_cfg); - gnt = gnt_cfg.band[0]; - seq_printf(m, - " %-15s : pta_owner:%s, phy-0[gnt_wl:%s-%d/gnt_bt:%s-%d], ", - "[gnt_status]", - chip->chip_id == RTL8852C ? "HW" : - btc->dm.pta_owner == BTC_CTRL_BY_WL ? "WL" : "BT", - gnt.gnt_wl_sw_en ? "SW" : "HW", gnt.gnt_wl, - gnt.gnt_bt_sw_en ? "SW" : "HW", gnt.gnt_bt); - - gnt = gnt_cfg.band[1]; - seq_printf(m, "phy-1[gnt_wl:%s-%d/gnt_bt:%s-%d]\n", - gnt.gnt_wl_sw_en ? "SW" : "HW", - gnt.gnt_wl, - gnt.gnt_bt_sw_en ? "SW" : "HW", - gnt.gnt_bt); - } pcinfo = &pfwinfo->rpt_fbtc_mregval.cinfo; if (!pcinfo->valid) { rtw89_debug(rtwdev, RTW89_DBG_BTC, diff --git a/drivers/net/wireless/realtek/rtw89/coex.h b/drivers/net/wireless/realtek/rtw89/coex.h index e76153709793..46e25c6f88a6 100644 --- a/drivers/net/wireless/realtek/rtw89/coex.h +++ b/drivers/net/wireless/realtek/rtw89/coex.h @@ -142,6 +142,44 @@ enum btc_lps_state { BTC_LPS_RF_ON = 2 }; +#define R_BTC_BB_BTG_RX 0x980 +#define R_BTC_BB_PRE_AGC_S1 0x476C +#define R_BTC_BB_PRE_AGC_S0 0x4688 + +#define B_BTC_BB_GNT_MUX GENMASK(20, 17) +#define B_BTC_BB_PRE_AGC_MASK GENMASK(31, 24) +#define B_BTC_BB_PRE_AGC_VAL BIT(31) + +#define BTC_REG_NOTFOUND 0xff + +enum btc_ant_div_pos { + BTC_ANT_DIV_MAIN = 0, + BTC_ANT_DIV_AUX = 1, +}; + +enum btc_get_reg_status { + BTC_CSTATUS_TXDIV_POS = 0, + BTC_CSTATUS_RXDIV_POS = 1, + BTC_CSTATUS_BB_GNT_MUX = 2, + BTC_CSTATUS_BB_GNT_MUX_MON = 3, + BTC_CSTATUS_BB_PRE_AGC = 4, + BTC_CSTATUS_BB_PRE_AGC_MON = 5, +}; + +enum btc_preagc_type { + BTC_PREAGC_DISABLE, + BTC_PREAGC_ENABLE, + BTC_PREAGC_BB_FWCTRL, + BTC_PREAGC_NOTFOUND, +}; + +enum btc_btgctrl_type { + BTC_BTGCTRL_DISABLE, + BTC_BTGCTRL_ENABLE, + BTC_BTGCTRL_BB_GNT_FWCTRL, + BTC_BTGCTRL_BB_GNT_NOTFOUND, +}; + void rtw89_btc_ntfy_poweron(struct rtw89_dev *rtwdev); void rtw89_btc_ntfy_poweroff(struct rtw89_dev *rtwdev); void rtw89_btc_ntfy_init(struct rtw89_dev *rtwdev, u8 mode); diff --git a/drivers/net/wireless/realtek/rtw89/core.h b/drivers/net/wireless/realtek/rtw89/core.h index 21421980fd06..ea6df859ba15 100644 --- a/drivers/net/wireless/realtek/rtw89/core.h +++ b/drivers/net/wireless/realtek/rtw89/core.h @@ -1706,6 +1706,7 @@ struct rtw89_btc_wl_info { u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; u8 rssi_level; u8 cn_report; + u8 coex_mode; bool scbd_change; u32 scbd; @@ -1813,6 +1814,7 @@ struct rtw89_btc_bt_info { union rtw89_btc_bt_rfk_info_map rfk_info; u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ + u8 rssi_level; u32 scbd; u32 feature; @@ -1829,7 +1831,8 @@ struct rtw89_btc_bt_info { u32 hi_lna_rx: 1; u32 scan_rx_low_pri: 1; u32 scan_info_update: 1; - u32 rsvd: 20; + u32 lna_constrain: 3; + u32 rsvd: 17; }; struct rtw89_btc_cx { @@ -2307,12 +2310,6 @@ struct rtw89_btc_fbtc_fddt_cell_status { u8 state_phase; /* [0:3] train state, [4:7] train phase */ } __packed; -struct rtw89_btc_fbtc_fddt_cell_status_v5 { - s8 wl_tx_pwr; - s8 bt_tx_pwr; - s8 bt_rx_gain; -} __packed; - struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ u8 fver; u8 rsvd; @@ -2376,9 +2373,9 @@ struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; - struct rtw89_btc_fbtc_fddt_cell_status_v5 fddt_cells[FDD_TRAIN_WL_DIRECTION] - [FDD_TRAIN_WL_RSSI_LEVEL] - [FDD_TRAIN_BT_RSSI_LEVEL]; + struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] + [FDD_TRAIN_WL_RSSI_LEVEL] + [FDD_TRAIN_BT_RSSI_LEVEL]; __le32 except_map; } __packed; @@ -2511,18 +2508,22 @@ struct rtw89_btc_dm { u32 noisy_level: 3; u32 coex_info_map: 8; u32 bt_only: 1; - u32 wl_btg_rx: 1; + u32 wl_btg_rx: 2; u32 trx_para_level: 8; u32 wl_stb_chg: 1; u32 pta_owner: 1; + u32 tdma_instant_excute: 1; + u32 wl_btg_rx_rb: 2; u16 slot_dur[CXST_MAX]; u8 run_reason; u8 run_action; + u8 wl_pre_agc: 2; u8 wl_lna2: 1; + u8 wl_pre_agc_rb: 2; }; struct rtw89_btc_ctrl { diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c index 80ab5fdfdaa0..c485ef2cc3d3 100644 --- a/drivers/net/wireless/realtek/rtw89/mac.c +++ b/drivers/net/wireless/realtek/rtw89/mac.c @@ -5507,7 +5507,8 @@ bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) if (chip->chip_id == RTL8852C) return false; - else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B) + else if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || + chip->chip_id == RTL8851B) val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, B_AX_LTE_MUX_CTRL_PATH >> 24); diff --git a/drivers/net/wireless/realtek/rtw89/mac_be.c b/drivers/net/wireless/realtek/rtw89/mac_be.c index fa3f5ef289cb..be30c9346293 100644 --- a/drivers/net/wireless/realtek/rtw89/mac_be.c +++ b/drivers/net/wireless/realtek/rtw89/mac_be.c @@ -73,6 +73,11 @@ static int rtw89_mac_check_mac_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, return -EFAULT; } +static bool is_qta_poh(struct rtw89_dev *rtwdev) +{ + return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; +} + static void hfc_get_mix_info_be(struct rtw89_dev *rtwdev) { struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; @@ -566,6 +571,800 @@ static int rtw89_fwdl_check_path_ready_be(struct rtw89_dev *rtwdev, rtwdev, R_BE_WCPU_FW_CTRL); } +static int dmac_func_en_be(struct rtw89_dev *rtwdev) +{ + return 0; +} + +static int cmac_func_en_be(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) +{ + u32 reg; + + if (mac_idx > RTW89_MAC_1) + return -EINVAL; + + if (mac_idx == RTW89_MAC_0) + return 0; + + if (en) { + rtw89_write32_set(rtwdev, R_BE_AFE_CTRL1, B_BE_AFE_CTRL1_SET); + rtw89_write32_clr(rtwdev, R_BE_SYS_ISO_CTRL_EXTEND, B_BE_R_SYM_ISO_CMAC12PP); + rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_CMAC1_FEN); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx); + rtw89_write32_set(rtwdev, reg, B_BE_CK_EN_SET); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx); + rtw89_write32_set(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET); + + set_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); + } else { + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CMAC_FUNC_EN, mac_idx); + rtw89_write32_clr(rtwdev, reg, B_BE_CMAC_FUNC_EN_SET); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CK_EN, mac_idx); + rtw89_write32_clr(rtwdev, reg, B_BE_CK_EN_SET); + + rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_CMAC1_FEN); + rtw89_write32_set(rtwdev, R_BE_SYS_ISO_CTRL_EXTEND, B_BE_R_SYM_ISO_CMAC12PP); + rtw89_write32_clr(rtwdev, R_BE_AFE_CTRL1, B_BE_AFE_CTRL1_SET); + + clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); + } + + return 0; +} + +static int chip_func_en_be(struct rtw89_dev *rtwdev) +{ + return 0; +} + +static int sys_init_be(struct rtw89_dev *rtwdev) +{ + int ret; + + ret = dmac_func_en_be(rtwdev); + if (ret) + return ret; + + ret = cmac_func_en_be(rtwdev, RTW89_MAC_0, true); + if (ret) + return ret; + + ret = chip_func_en_be(rtwdev); + if (ret) + return ret; + + return ret; +} + +static int sta_sch_init_be(struct rtw89_dev *rtwdev) +{ + u32 p_val; + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); + if (ret) + return ret; + + rtw89_write8_set(rtwdev, R_BE_SS_CTRL, B_BE_SS_EN); + + ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_BE_SS_INIT_DONE, + 1, TRXCFG_WAIT_CNT, false, rtwdev, R_BE_SS_CTRL); + if (ret) { + rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); + return ret; + } + + rtw89_write32_set(rtwdev, R_BE_SS_CTRL, B_BE_WARM_INIT); + rtw89_write32_clr(rtwdev, R_BE_SS_CTRL, B_BE_BAND_TRIG_EN | B_BE_BAND1_TRIG_EN); + + return 0; +} + +static int mpdu_proc_init_be(struct rtw89_dev *rtwdev) +{ + u32 val32; + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); + if (ret) + return ret; + + rtw89_write32_set(rtwdev, R_BE_MPDU_PROC, B_BE_APPEND_FCS); + rtw89_write32(rtwdev, R_BE_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); + + val32 = rtw89_read32(rtwdev, R_BE_HDR_SHCUT_SETTING); + val32 |= (B_BE_TX_HW_SEQ_EN | B_BE_TX_HW_ACK_POLICY_EN | B_BE_TX_MAC_MPDU_PROC_EN); + val32 &= ~B_BE_TX_ADDR_MLD_TO_LIK; + rtw89_write32_set(rtwdev, R_BE_HDR_SHCUT_SETTING, val32); + + rtw89_write32(rtwdev, R_BE_RX_HDRTRNS, TRXCFG_MPDU_PROC_RX_HDR_CONV); + + val32 = rtw89_read32(rtwdev, R_BE_DISP_FWD_WLAN_0); + val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_DATA_MASK); + val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_MNG_MASK); + val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_0_CTL_MASK); + val32 = u32_replace_bits(val32, 1, B_BE_FWD_WLAN_CPU_TYPE_1_MASK); + rtw89_write32(rtwdev, R_BE_DISP_FWD_WLAN_0, val32); + + return 0; +} + +static int sec_eng_init_be(struct rtw89_dev *rtwdev) +{ + u32 val32; + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); + if (ret) + return ret; + + val32 = rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL); + val32 |= B_BE_CLK_EN_CGCMP | B_BE_CLK_EN_WAPI | B_BE_CLK_EN_WEP_TKIP | + B_BE_SEC_TX_ENC | B_BE_SEC_RX_DEC | + B_BE_MC_DEC | B_BE_BC_DEC | + B_BE_BMC_MGNT_DEC | B_BE_UC_MGNT_DEC; + val32 &= ~B_BE_SEC_PRE_ENQUE_TX; + rtw89_write32(rtwdev, R_BE_SEC_ENG_CTRL, val32); + + rtw89_write32_set(rtwdev, R_BE_SEC_MPDU_PROC, B_BE_APPEND_ICV | B_BE_APPEND_MIC); + + return 0; +} + +static int txpktctrl_init_be(struct rtw89_dev *rtwdev) +{ + struct rtw89_mac_dle_rsvd_qt_cfg qt_cfg; + u32 val32; + int ret; + + ret = rtw89_mac_get_dle_rsvd_qt_cfg(rtwdev, DLE_RSVD_QT_MPDU_INFO, &qt_cfg); + if (ret) { + rtw89_err(rtwdev, "get dle rsvd qt %d cfg fail %d\n", + DLE_RSVD_QT_MPDU_INFO, ret); + return ret; + } + + val32 = rtw89_read32(rtwdev, R_BE_TXPKTCTL_MPDUINFO_CFG); + val32 = u32_replace_bits(val32, qt_cfg.pktid, B_BE_MPDUINFO_PKTID_MASK); + val32 = u32_replace_bits(val32, MPDU_INFO_B1_OFST, B_BE_MPDUINFO_B1_BADDR_MASK); + val32 |= B_BE_MPDUINFO_FEN; + rtw89_write32(rtwdev, R_BE_TXPKTCTL_MPDUINFO_CFG, val32); + + return 0; +} + +static int mlo_init_be(struct rtw89_dev *rtwdev) +{ + u32 val32; + int ret; + + val32 = rtw89_read32(rtwdev, R_BE_MLO_INIT_CTL); + + val32 |= B_BE_MLO_TABLE_REINIT; + rtw89_write32(rtwdev, R_BE_MLO_INIT_CTL, val32); + val32 &= ~B_BE_MLO_TABLE_REINIT; + rtw89_write32(rtwdev, R_BE_MLO_INIT_CTL, val32); + + ret = read_poll_timeout_atomic(rtw89_read32, val32, + val32 & B_BE_MLO_TABLE_INIT_DONE, + 1, 1000, false, rtwdev, R_BE_MLO_INIT_CTL); + if (ret) + rtw89_err(rtwdev, "[MLO]%s: MLO init polling timeout\n", __func__); + + rtw89_write32_set(rtwdev, R_BE_SS_CTRL, B_BE_MLO_HW_CHGLINK_EN); + rtw89_write32_set(rtwdev, R_BE_CMAC_SHARE_ACQCHK_CFG_0, B_BE_R_MACID_ACQ_CHK_EN); + + return ret; +} + +static int dmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + int ret; + + ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); + if (ret) { + rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); + return ret; + } + + ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); + if (ret) { + rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); + return ret; + } + + ret = rtw89_mac_hfc_init(rtwdev, true, true, true); + if (ret) { + rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); + return ret; + } + + ret = sta_sch_init_be(rtwdev); + if (ret) { + rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); + return ret; + } + + ret = mpdu_proc_init_be(rtwdev); + if (ret) { + rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); + return ret; + } + + ret = sec_eng_init_be(rtwdev); + if (ret) { + rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); + return ret; + } + + ret = txpktctrl_init_be(rtwdev); + if (ret) { + rtw89_err(rtwdev, "[ERR]TX pkt ctrl init %d\n", ret); + return ret; + } + + ret = mlo_init_be(rtwdev); + if (ret) { + rtw89_err(rtwdev, "[ERR]MLO init %d\n", ret); + return ret; + } + + return ret; +} + +static int scheduler_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + u32 val32; + u32 reg; + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); + if (ret) + return ret; + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_HE_CTN_CHK_CCA_NAV, mac_idx); + val32 = B_BE_HE_CTN_CHK_CCA_P20 | B_BE_HE_CTN_CHK_EDCCA_P20 | + B_BE_HE_CTN_CHK_CCA_BITMAP | B_BE_HE_CTN_CHK_EDCCA_BITMAP | + B_BE_HE_CTN_CHK_NO_GNT_WL | B_BE_HE_CTN_CHK_BASIC_NAV | + B_BE_HE_CTN_CHK_INTRA_NAV | B_BE_HE_CTN_CHK_TX_NAV; + rtw89_write32(rtwdev, reg, val32); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_HE_SIFS_CHK_CCA_NAV, mac_idx); + val32 = B_BE_HE_SIFS_CHK_EDCCA_P20 | B_BE_HE_SIFS_CHK_EDCCA_BITMAP | + B_BE_HE_SIFS_CHK_NO_GNT_WL; + rtw89_write32(rtwdev, reg, val32); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TB_CHK_CCA_NAV, mac_idx); + val32 = B_BE_TB_CHK_EDCCA_BITMAP | B_BE_TB_CHK_NO_GNT_WL | B_BE_TB_CHK_BASIC_NAV; + rtw89_write32(rtwdev, reg, val32); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CCA_CFG_0, mac_idx); + rtw89_write32_clr(rtwdev, reg, B_BE_NO_GNT_WL_EN); + + if (is_qta_poh(rtwdev)) { + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PREBKF_CFG_0, mac_idx); + rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_MASK, + SCH_PREBKF_24US); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTN_CFG_0, mac_idx); + rtw89_write32_mask(rtwdev, reg, B_BE_PREBKF_TIME_NONAC_MASK, + SCH_PREBKF_24US); + } + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_EDCA_BCNQ_PARAM, mac_idx); + rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_CW_MASK, 0x32); + rtw89_write32_mask(rtwdev, reg, B_BE_BCNQ_AIFS_MASK, BCN_IFS_25US); + + return 0; +} + +static int addr_cam_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + u32 val32; + u16 val16; + u32 reg; + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); + if (ret) + return ret; + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_ADDR_CAM_CTRL, mac_idx); + val32 = rtw89_read32(rtwdev, reg); + val32 = u32_replace_bits(val32, ADDR_CAM_SERCH_RANGE, B_BE_ADDR_CAM_RANGE_MASK); + val32 |= B_BE_ADDR_CAM_EN; + if (mac_idx == RTW89_MAC_0) + val32 |= B_BE_ADDR_CAM_CLR; + rtw89_write32(rtwdev, reg, val32); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_ADDR_CAM_CTRL, mac_idx); + ret = read_poll_timeout_atomic(rtw89_read16, val16, !(val16 & B_BE_ADDR_CAM_CLR), + 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); + if (ret) + rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); + + return ret; +} + +static int rtw89_mac_typ_fltr_opt_be(struct rtw89_dev *rtwdev, + enum rtw89_machdr_frame_type type, + enum rtw89_mac_fwd_target fwd_target, + u8 mac_idx) +{ + u32 reg; + u32 val; + + switch (fwd_target) { + case RTW89_FWD_DONT_CARE: + val = RX_FLTR_FRAME_DROP_BE; + break; + case RTW89_FWD_TO_HOST: + case RTW89_FWD_TO_WLAN_CPU: + val = RX_FLTR_FRAME_ACCEPT_BE; + break; + default: + rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); + return -EINVAL; + } + + switch (type) { + case RTW89_MGNT: + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MGNT_FLTR, mac_idx); + break; + case RTW89_CTRL: + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_CTRL_FLTR, mac_idx); + break; + case RTW89_DATA: + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DATA_FLTR, mac_idx); + break; + default: + rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); + return -EINVAL; + } + rtw89_write32(rtwdev, reg, val); + + return 0; +} + +static int rx_fltr_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + u32 reg; + u32 val; + + rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_MGNT, RTW89_FWD_TO_HOST, mac_idx); + rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_CTRL, RTW89_FWD_TO_HOST, mac_idx); + rtw89_mac_typ_fltr_opt_be(rtwdev, RTW89_DATA, RTW89_FWD_TO_HOST, mac_idx); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_FLTR_OPT, mac_idx); + val = B_BE_A_BC_CAM_MATCH | B_BE_A_UC_CAM_MATCH | B_BE_A_MC | + B_BE_A_BC | B_BE_A_A1_MATCH | B_BE_SNIFFER_MODE | + u32_encode_bits(15, B_BE_UID_FILTER_MASK); + rtw89_write32(rtwdev, reg, val); + u32p_replace_bits(&rtwdev->hal.rx_fltr, 15, B_BE_UID_FILTER_MASK); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx); + val = B_BE_HE_SIGB_CRC_CHK | B_BE_VHT_MU_SIGB_CRC_CHK | + B_BE_VHT_SU_SIGB_CRC_CHK | B_BE_SIGA_CRC_CHK | + B_BE_LSIG_PARITY_CHK_EN | B_BE_CCK_SIG_CHK | B_BE_CCK_CRC_CHK; + rtw89_write16(rtwdev, reg, val); + + return 0; +} + +static int cca_ctrl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + return 0; +} + +static int nav_ctrl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + u32 val32; + u32 reg; + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_NAV_CTL, mac_idx); + + val32 = rtw89_read32(rtwdev, reg); + val32 &= ~B_BE_WMAC_PLCP_UP_NAV_EN; + val32 |= B_BE_WMAC_TF_UP_NAV_EN | B_BE_WMAC_NAV_UPPER_EN; + val32 = u32_replace_bits(val32, NAV_25MS, B_BE_WMAC_NAV_UPPER_MASK); + + rtw89_write32(rtwdev, reg, val32); + + return 0; +} + +static int spatial_reuse_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + u32 reg; + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); + if (ret) + return ret; + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_SR_CTRL, mac_idx); + rtw89_write8_clr(rtwdev, reg, B_BE_SR_EN | B_BE_SR_CTRL_PLCP_EN); + + return 0; +} + +static int tmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + u32 reg; + + rtw89_write32_clr(rtwdev, R_BE_TB_PPDU_CTRL, B_BE_QOSNULL_UPD_MUEDCA_EN); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMTX_TCR_BE_4, mac_idx); + rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK, 0x12); + rtw89_write32_mask(rtwdev, reg, B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK, 0xe); + + return 0; +} + +static int trxptcl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + const struct rtw89_chip_info *chip = rtwdev->chip; + const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; + struct rtw89_hal *hal = &rtwdev->hal; + u32 val32; + u32 reg; + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); + if (ret) + return ret; + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MAC_LOOPBACK, mac_idx); + val32 = rtw89_read32(rtwdev, reg); + val32 = u32_replace_bits(val32, S_BE_MACLBK_PLCP_DLY_DEF, + B_BE_MACLBK_PLCP_DLY_MASK); + val32 &= ~B_BE_MACLBK_EN; + rtw89_write32(rtwdev, reg, val32); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_0, mac_idx); + val32 = rtw89_read32(rtwdev, reg); + val32 = u32_replace_bits(val32, WMAC_SPEC_SIFS_CCK, + B_BE_WMAC_SPEC_SIFS_CCK_MASK); + val32 = u32_replace_bits(val32, WMAC_SPEC_SIFS_OFDM_1115E, + B_BE_WMAC_SPEC_SIFS_OFDM_MASK); + rtw89_write32(rtwdev, reg, val32); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_LEGACY, mac_idx); + rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_HE, mac_idx); + rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_RESP_HE_CHK_EDCCA); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC, mac_idx); + rtw89_write32_clr(rtwdev, reg, B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RXTRIG_TEST_USER_2, mac_idx); + rtw89_write32_set(rtwdev, reg, B_BE_RXTRIG_FCSCHK_EN); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_TRXPTCL_RESP_1, mac_idx); + val32 = rtw89_read32(rtwdev, reg); + val32 &= B_BE_FTM_RRSR_RATE_EN_MASK | B_BE_WMAC_RESP_DOPPLEB_BE_EN | + B_BE_WMAC_RESP_DCM_EN | B_BE_WMAC_RESP_REF_RATE_MASK; + rtw89_write32(rtwdev, reg, val32); + rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR1, mac_idx); + val32 = rtw89_read32(rtwdev, reg); + val32 &= B_BE_RRSR_RATE_EN_MASK | B_BE_RRSR_CCK_MASK | B_BE_RSC_MASK; + rtw89_write32(rtwdev, reg, val32); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR0, mac_idx); + val32 = rtw89_read32(rtwdev, reg); + val32 &= B_BE_RRSR_OFDM_MASK | B_BE_RRSR_HT_MASK | B_BE_RRSR_VHT_MASK | + B_BE_RRSR_HE_MASK; + rtw89_write32(rtwdev, reg, val32); + + if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV) { + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_RRSR1, mac_idx); + rtw89_write32_mask(rtwdev, reg, B_BE_RSC_MASK, 1); + } + + return 0; +} + +static int rst_bacam_be(struct rtw89_dev *rtwdev) +{ + u32 val; + int ret; + + rtw89_write32_mask(rtwdev, R_BE_RESPBA_CAM_CTRL, B_BE_BACAM_RST_MASK, + S_BE_BACAM_RST_ALL); + + ret = read_poll_timeout_atomic(rtw89_read32_mask, val, val == S_BE_BACAM_RST_DONE, + 1, 1000, false, + rtwdev, R_BE_RESPBA_CAM_CTRL, B_BE_BACAM_RST_MASK); + if (ret) + rtw89_err(rtwdev, "[ERR]bacam rst timeout\n"); + + return ret; +} + +#define PLD_RLS_MAX_PG 127 +#define RX_MAX_LEN_UNIT 512 +#define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) + +static int rmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + u32 rx_min_qta, rx_max_len, rx_max_pg; + u16 val16; + u32 reg; + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); + if (ret) + return ret; + + if (mac_idx == RTW89_MAC_0) { + ret = rst_bacam_be(rtwdev); + if (ret) + return ret; + } + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_DLK_PROTECT_CTL, mac_idx); + val16 = rtw89_read16(rtwdev, reg); + val16 = u16_replace_bits(val16, TRXCFG_RMAC_DATA_TO, B_BE_RX_DLK_DATA_TIME_MASK); + val16 = u16_replace_bits(val16, TRXCFG_RMAC_CCA_TO, B_BE_RX_DLK_CCA_TIME_MASK); + val16 |= B_BE_RX_DLK_RST_EN; + rtw89_write16(rtwdev, reg, val16); + + if (mac_idx == RTW89_MAC_0) + rx_min_qta = rtwdev->mac.dle_info.c0_rx_qta; + else + rx_min_qta = rtwdev->mac.dle_info.c1_rx_qta; + rx_max_pg = min_t(u32, rx_min_qta, PLD_RLS_MAX_PG); + rx_max_len = rx_max_pg * rtwdev->mac.dle_info.ple_pg_size; + rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); + rx_max_len /= RX_MAX_LEN_UNIT; + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_FLTR_OPT, mac_idx); + rtw89_write32_mask(rtwdev, reg, B_BE_RX_MPDU_MAX_LEN_MASK, rx_max_len); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PLCP_HDR_FLTR, mac_idx); + rtw89_write8_clr(rtwdev, reg, B_BE_VHT_SU_SIGB_CRC_CHK); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RCR, mac_idx); + rtw89_write16_set(rtwdev, reg, B_BE_BUSY_CHKSN); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_PLCP_EXT_OPTION_1, mac_idx); + rtw89_write16_set(rtwdev, reg, B_BE_PLCP_SU_PSDU_LEN_SRC); + + return 0; +} + +static int resp_pktctl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + struct rtw89_mac_dle_rsvd_qt_cfg qt_cfg; + enum rtw89_mac_dle_rsvd_qt_type type; + u32 reg; + int ret; + + if (mac_idx == RTW89_MAC_1) + type = DLE_RSVD_QT_B1_CSI; + else + type = DLE_RSVD_QT_B0_CSI; + + ret = rtw89_mac_get_dle_rsvd_qt_cfg(rtwdev, type, &qt_cfg); + if (ret) { + rtw89_err(rtwdev, "get dle rsvd qt %d cfg fail %d\n", type, ret); + return ret; + } + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RESP_CSI_RESERVED_PAGE, mac_idx); + rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_START_PAGE_MASK, qt_cfg.pktid); + rtw89_write32_mask(rtwdev, reg, B_BE_CSI_RESERVED_PAGE_NUM_MASK, qt_cfg.pg_num); + + return 0; +} + +static int cmac_com_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + u32 val32; + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); + if (ret) + return ret; + + if (mac_idx == RTW89_MAC_0) { + val32 = rtw89_read32(rtwdev, R_BE_TX_SUB_BAND_VALUE); + val32 = u32_replace_bits(val32, S_BE_TXSB_20M_8, B_BE_TXSB_20M_MASK); + val32 = u32_replace_bits(val32, S_BE_TXSB_40M_4, B_BE_TXSB_40M_MASK); + val32 = u32_replace_bits(val32, S_BE_TXSB_80M_2, B_BE_TXSB_80M_MASK); + val32 = u32_replace_bits(val32, S_BE_TXSB_160M_1, B_BE_TXSB_160M_MASK); + rtw89_write32(rtwdev, R_BE_TX_SUB_BAND_VALUE, val32); + } else { + val32 = rtw89_read32(rtwdev, R_BE_TX_SUB_BAND_VALUE_C1); + val32 = u32_replace_bits(val32, S_BE_TXSB_20M_2, B_BE_TXSB_20M_MASK); + val32 = u32_replace_bits(val32, S_BE_TXSB_40M_1, B_BE_TXSB_40M_MASK); + val32 = u32_replace_bits(val32, S_BE_TXSB_80M_0, B_BE_TXSB_80M_MASK); + val32 = u32_replace_bits(val32, S_BE_TXSB_160M_0, B_BE_TXSB_160M_MASK); + rtw89_write32(rtwdev, R_BE_TX_SUB_BAND_VALUE_C1, val32); + } + + return 0; +} + +static int ptcl_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + u32 val32; + u8 val8; + u32 reg; + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); + if (ret) + return ret; + + if (is_qta_poh(rtwdev)) { + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_SIFS_SETTING, mac_idx); + val32 = rtw89_read32(rtwdev, reg); + val32 = u32_replace_bits(val32, S_AX_CTS2S_TH_1K, + B_BE_HW_CTS2SELF_PKT_LEN_TH_MASK); + val32 = u32_replace_bits(val32, S_AX_CTS2S_TH_SEC_256B, + B_BE_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); + val32 |= B_BE_HW_CTS2SELF_EN; + rtw89_write32(rtwdev, reg, val32); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_FSM_MON, mac_idx); + val32 = rtw89_read32(rtwdev, reg); + val32 = u32_replace_bits(val32, S_AX_PTCL_TO_2MS, + B_BE_PTCL_TX_ARB_TO_THR_MASK); + val32 &= ~B_BE_PTCL_TX_ARB_TO_MODE; + rtw89_write32(rtwdev, reg, val32); + } + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_COMMON_SETTING_0, mac_idx); + val8 = rtw89_read8(rtwdev, reg); + val8 |= B_BE_CMAC_TX_MODE_0 | B_BE_CMAC_TX_MODE_1; + val8 &= ~(B_BE_PTCL_TRIGGER_SS_EN_0 | + B_BE_PTCL_TRIGGER_SS_EN_1 | + B_BE_PTCL_TRIGGER_SS_EN_UL); + rtw89_write8(rtwdev, reg, val8); + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_AMPDU_AGG_LIMIT, mac_idx); + rtw89_write32_mask(rtwdev, reg, B_BE_AMPDU_MAX_TIME_MASK, AMPDU_MAX_TIME); + + return 0; +} + +static int cmac_dma_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + u32 val32; + u32 reg; + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); + if (ret) + return ret; + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_RX_CTRL_1, mac_idx); + + val32 = rtw89_read32(rtwdev, reg); + val32 = u32_replace_bits(val32, WLCPU_RXCH2_QID, + B_BE_RXDMA_TXRPT_QUEUE_ID_SW_MASK); + val32 = u32_replace_bits(val32, WLCPU_RXCH2_QID, + B_BE_RXDMA_F2PCMDRPT_QUEUE_ID_SW_MASK); + rtw89_write32(rtwdev, reg, val32); + + return 0; +} + +static int cmac_init_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + int ret; + + ret = scheduler_init_be(rtwdev, mac_idx); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); + return ret; + } + + ret = addr_cam_init_be(rtwdev, mac_idx); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, + ret); + return ret; + } + + ret = rx_fltr_init_be(rtwdev, mac_idx); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, + ret); + return ret; + } + + ret = cca_ctrl_init_be(rtwdev, mac_idx); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, + ret); + return ret; + } + + ret = nav_ctrl_init_be(rtwdev, mac_idx); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, + ret); + return ret; + } + + ret = spatial_reuse_init_be(rtwdev, mac_idx); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", + mac_idx, ret); + return ret; + } + + ret = tmac_init_be(rtwdev, mac_idx); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); + return ret; + } + + ret = trxptcl_init_be(rtwdev, mac_idx); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); + return ret; + } + + ret = rmac_init_be(rtwdev, mac_idx); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); + return ret; + } + + ret = resp_pktctl_init_be(rtwdev, mac_idx); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d resp pktctl init %d\n", mac_idx, ret); + return ret; + } + + ret = cmac_com_init_be(rtwdev, mac_idx); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); + return ret; + } + + ret = ptcl_init_be(rtwdev, mac_idx); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); + return ret; + } + + ret = cmac_dma_init_be(rtwdev, mac_idx); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); + return ret; + } + + return ret; +} + +static int tx_idle_poll_band_be(struct rtw89_dev *rtwdev, u8 mac_idx) +{ + u32 reg; + u8 val8; + int ret; + + ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); + if (ret) + return ret; + + reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PTCL_TX_CTN_SEL, mac_idx); + + ret = read_poll_timeout_atomic(rtw89_read8, val8, !(val8 & B_BE_PTCL_BUSY), + 30, 66000, false, rtwdev, reg); + + return ret; +} + static int dle_buf_req_be(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) { u32 val, reg; @@ -650,6 +1449,275 @@ static int set_cpuio_be(struct rtw89_dev *rtwdev, return 0; } +static int preload_init_be(struct rtw89_dev *rtwdev, u8 mac_idx, + enum rtw89_qta_mode mode) +{ + u32 max_preld_size, min_rsvd_size; + u32 val32; + u32 reg; + + max_preld_size = mac_idx == RTW89_MAC_0 ? + PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM; + max_preld_size *= PRELD_AMSDU_SIZE; + + reg = mac_idx == RTW89_MAC_0 ? R_BE_TXPKTCTL_B0_PRELD_CFG0 : + R_BE_TXPKTCTL_B1_PRELD_CFG0; + val32 = rtw89_read32(rtwdev, reg); + val32 = u32_replace_bits(val32, max_preld_size, B_BE_B0_PRELD_USEMAXSZ_MASK); + val32 |= B_BE_B0_PRELD_FEN; + rtw89_write32(rtwdev, reg, val32); + + min_rsvd_size = PRELD_AMSDU_SIZE; + reg = mac_idx == RTW89_MAC_0 ? R_BE_TXPKTCTL_B0_PRELD_CFG1 : + R_BE_TXPKTCTL_B1_PRELD_CFG1; + val32 = rtw89_read32(rtwdev, reg); + val32 = u32_replace_bits(val32, PRELD_NEXT_WND, B_BE_B0_PRELD_NXT_TXENDWIN_MASK); + val32 = u32_replace_bits(val32, min_rsvd_size, B_BE_B0_PRELD_NXT_RSVMINSZ_MASK); + rtw89_write32(rtwdev, reg, val32); + + return 0; +} + +static int dbcc_bb_ctrl_be(struct rtw89_dev *rtwdev, bool bb1_en) +{ + return 0; +} + +static int enable_imr_be(struct rtw89_dev *rtwdev, u8 mac_idx, + enum rtw89_mac_hwmod_sel sel) +{ + const struct rtw89_chip_info *chip = rtwdev->chip; + const struct rtw89_imr_table *table; + const struct rtw89_reg_imr *reg; + u32 addr; + u32 val; + int i; + + if (sel == RTW89_DMAC_SEL) + table = chip->imr_dmac_table; + else if (sel == RTW89_CMAC_SEL) + table = chip->imr_cmac_table; + else + return -EINVAL; + + for (i = 0; i < table->n_regs; i++) { + reg = &table->regs[i]; + addr = rtw89_mac_reg_by_idx(rtwdev, reg->addr, mac_idx); + + val = rtw89_read32(rtwdev, addr); + val &= ~reg->clr; + val |= reg->set; + rtw89_write32(rtwdev, addr, val); + } + + return 0; +} + +static void err_imr_ctrl_be(struct rtw89_dev *rtwdev, bool en) +{ + u32 v32_dmac = en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS; + u32 v32_cmac0 = en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS; + u32 v32_cmac1 = en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS; + + v32_dmac &= ~B_BE_DMAC_NOTX_ERR_INT_EN; + + rtw89_write32(rtwdev, R_BE_DMAC_ERR_IMR, v32_dmac); + rtw89_write32(rtwdev, R_BE_CMAC_ERR_IMR, v32_cmac0); + + if (rtwdev->dbcc_en) + rtw89_write32(rtwdev, R_BE_CMAC_ERR_IMR_C1, v32_cmac1); +} + +static int band1_enable_be(struct rtw89_dev *rtwdev) +{ + int ret; + + ret = tx_idle_poll_band_be(rtwdev, RTW89_MAC_0); + if (ret) { + rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); + return ret; + } + + ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode); + if (ret) { + rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); + return ret; + } + + ret = preload_init_be(rtwdev, RTW89_MAC_1, rtwdev->mac.qta_mode); + if (ret) { + rtw89_err(rtwdev, "[ERR]preload init B1 %d\n", ret); + return ret; + } + + ret = cmac_func_en_be(rtwdev, RTW89_MAC_1, true); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d func en %d\n", RTW89_MAC_1, ret); + return ret; + } + + ret = cmac_init_be(rtwdev, RTW89_MAC_1); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", RTW89_MAC_1, ret); + return ret; + } + + ret = dbcc_bb_ctrl_be(rtwdev, true); + if (ret) { + rtw89_err(rtwdev, "[ERR]enable bb 1 %d\n", ret); + return ret; + } + + ret = enable_imr_be(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); + if (ret) { + rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); + return ret; + } + + return 0; +} + +static int band1_disable_be(struct rtw89_dev *rtwdev) +{ + int ret; + + ret = dbcc_bb_ctrl_be(rtwdev, false); + if (ret) { + rtw89_err(rtwdev, "[ERR]disable bb 1 %d\n", ret); + return ret; + } + + ret = cmac_func_en_be(rtwdev, RTW89_MAC_1, false); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d func dis %d\n", RTW89_MAC_1, ret); + return ret; + } + + ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode); + if (ret) { + rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); + return ret; + } + + return 0; +} + +static int dbcc_enable_be(struct rtw89_dev *rtwdev, bool enable) +{ + int ret; + + if (enable) { + ret = band1_enable_be(rtwdev); + if (ret) { + rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); + return ret; + } + + if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) { + ret = rtw89_fw_h2c_notify_dbcc(rtwdev, true); + if (ret) { + rtw89_err(rtwdev, "%s:[ERR]notfify dbcc1 fail %d\n", + __func__, ret); + return ret; + } + } + } else { + if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) { + ret = rtw89_fw_h2c_notify_dbcc(rtwdev, false); + if (ret) { + rtw89_err(rtwdev, "%s:[ERR]notfify dbcc1 fail %d\n", + __func__, ret); + return ret; + } + } + + ret = band1_disable_be(rtwdev); + if (ret) { + rtw89_err(rtwdev, "[ERR] band1_disable %d\n", ret); + return ret; + } + } + + return 0; +} + +static int set_host_rpr_be(struct rtw89_dev *rtwdev) +{ + u32 val32; + u32 mode; + u32 fltr; + bool poh; + + poh = is_qta_poh(rtwdev); + + if (poh) { + mode = RTW89_RPR_MODE_POH; + fltr = S_BE_WDRLS_FLTR_TXOK | S_BE_WDRLS_FLTR_RTYLMT | + S_BE_WDRLS_FLTR_LIFTIM | S_BE_WDRLS_FLTR_MACID; + } else { + mode = RTW89_RPR_MODE_STF; + fltr = 0; + } + + rtw89_write32_mask(rtwdev, R_BE_WDRLS_CFG, B_BE_WDRLS_MODE_MASK, mode); + + val32 = rtw89_read32(rtwdev, R_BE_RLSRPT0_CFG1); + val32 = u32_replace_bits(val32, fltr, B_BE_RLSRPT0_FLTR_MAP_MASK); + val32 = u32_replace_bits(val32, 30, B_BE_RLSRPT0_AGGNUM_MASK); + val32 = u32_replace_bits(val32, 255, B_BE_RLSRPT0_TO_MASK); + rtw89_write32(rtwdev, R_BE_RLSRPT0_CFG1, val32); + + return 0; +} + +static int trx_init_be(struct rtw89_dev *rtwdev) +{ + enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; + int ret; + + ret = dmac_init_be(rtwdev, 0); + if (ret) { + rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); + return ret; + } + + ret = cmac_init_be(rtwdev, 0); + if (ret) { + rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); + return ret; + } + + if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { + ret = dbcc_enable_be(rtwdev, true); + if (ret) { + rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); + return ret; + } + } + + ret = enable_imr_be(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); + if (ret) { + rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); + return ret; + } + + ret = enable_imr_be(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); + if (ret) { + rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); + return ret; + } + + err_imr_ctrl_be(rtwdev, true); + + ret = set_host_rpr_be(rtwdev); + if (ret) { + rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); + return ret; + } + + return 0; +} + static bool rtw89_mac_get_txpwr_cr_be(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u32 reg_base, u32 *cr) @@ -1162,12 +2230,16 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = { }, .check_mac_en = rtw89_mac_check_mac_en_be, + .sys_init = sys_init_be, + .trx_init = trx_init_be, .hci_func_en = rtw89_mac_hci_func_en_be, .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_be, .dle_func_en = dle_func_en_be, .dle_clk_en = dle_clk_en_be, .bf_assoc = rtw89_mac_bf_assoc_be, + .typ_fltr_opt = rtw89_mac_typ_fltr_opt_be, + .dle_mix_cfg = dle_mix_cfg_be, .chk_dle_rdy = chk_dle_rdy_be, .dle_buf_req = dle_buf_req_be, diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h index 65d8a0f36700..8456e2b0c14f 100644 --- a/drivers/net/wireless/realtek/rtw89/reg.h +++ b/drivers/net/wireless/realtek/rtw89/reg.h @@ -4924,6 +4924,24 @@ B_BE_CR_WRFF_OVERFLOW_ERR_INT_EN | \ B_BE_CR_WRFF_UNDERFLOW_ERR_INT_EN) +#define R_BE_DISP_FWD_WLAN_0 0x8938 +#define B_BE_FWD_WLAN_CPU_TYPE_13_MASK GENMASK(31, 30) +#define B_BE_FWD_WLAN_CPU_TYPE_12_MASK GENMASK(29, 28) +#define B_BE_FWD_WLAN_CPU_TYPE_11_MASK GENMASK(27, 26) +#define B_BE_FWD_WLAN_CPU_TYPE_10_MASK GENMASK(25, 24) +#define B_BE_FWD_WLAN_CPU_TYPE_9_MASK GENMASK(23, 22) +#define B_BE_FWD_WLAN_CPU_TYPE_8_MASK GENMASK(21, 20) +#define B_BE_FWD_WLAN_CPU_TYPE_7_MASK GENMASK(19, 18) +#define B_BE_FWD_WLAN_CPU_TYPE_6_MASK GENMASK(17, 16) +#define B_BE_FWD_WLAN_CPU_TYPE_5_MASK GENMASK(15, 14) +#define B_BE_FWD_WLAN_CPU_TYPE_4_MASK GENMASK(13, 12) +#define B_BE_FWD_WLAN_CPU_TYPE_3_MASK GENMASK(11, 10) +#define B_BE_FWD_WLAN_CPU_TYPE_2_MASK GENMASK(9, 8) +#define B_BE_FWD_WLAN_CPU_TYPE_1_MASK GENMASK(7, 6) +#define B_BE_FWD_WLAN_CPU_TYPE_0_CTL_MASK GENMASK(5, 4) +#define B_BE_FWD_WLAN_CPU_TYPE_0_MNG_MASK GENMASK(3, 2) +#define B_BE_FWD_WLAN_CPU_TYPE_0_DATA_MASK GENMASK(1, 0) + #define R_BE_WDE_PKTBUF_CFG 0x8C08 #define B_BE_WDE_FREE_PAGE_NUM_MASK GENMASK(28, 16) #define B_BE_WDE_START_BOUND_MASK GENMASK(14, 8) @@ -5387,11 +5405,47 @@ #define B_BE_PKTIN_ERR_IMR_SET (B_BE_SW_MERGE_ERR_INT_EN | \ B_BE_GET_NULL_PKTID_ERR_INT_EN) +#define R_BE_HDR_SHCUT_SETTING 0x9B00 +#define B_BE_TX_ADDR_MLD_TO_LIK BIT(4) +#define B_BE_TX_HW_SEC_HDR_EN BIT(3) +#define B_BE_TX_MAC_MPDU_PROC_EN BIT(2) +#define B_BE_TX_HW_ACK_POLICY_EN BIT(1) +#define B_BE_TX_HW_SEQ_EN BIT(0) + #define R_BE_MPDU_TX_ERR_IMR 0x9BF4 #define B_BE_TX_TIMEOUT_ERR_EN BIT(0) #define B_BE_MPDU_TX_ERR_IMR_CLR B_BE_TX_TIMEOUT_ERR_EN #define B_BE_MPDU_TX_ERR_IMR_SET 0 +#define R_BE_MPDU_PROC 0x9C00 +#define B_BE_PORT_SEL BIT(29) +#define B_BE_WPKT_WLANCPU_QSEL_MASK GENMASK(28, 27) +#define B_BE_WPKT_DATACPU_QSEL_MASK GENMASK(26, 25) +#define B_BE_WPKT_FW_RLS BIT(24) +#define B_BE_FWD_RPKT_MASK GENMASK(23, 16) +#define B_BE_FWD_WPKT_MASK GENMASK(15, 8) +#define B_BE_RXFWD_PRIO_MASK GENMASK(5, 4) +#define B_BE_RXFWD_EN BIT(3) +#define B_BE_DROP_NONDMA_PPDU BIT(2) +#define B_BE_APPEND_FCS BIT(0) + +#define R_BE_CUT_AMSDU_CTRL 0x9C94 +#define B_BE_EN_CUT_AMSDU BIT(31) +#define B_BE_CUT_AMSDU_CHKLEN_EN BIT(30) +#define B_BE_CA_CHK_ADDRCAM_EN BIT(29) +#define B_BE_MPDU_CUT_CTRL_EN BIT(24) +#define B_BE_CUT_AMSDU_CHKLEN_L_TH_MASK GENMASK(23, 16) +#define B_BE_CUT_AMSDU_CHKLEN_H_TH_MASK GENMASK(15, 0) + +#define R_BE_RX_HDRTRNS 0x9CC0 +#define B_BE_RX_MGN_MLD_ADDR_EN BIT(6) +#define B_BE_HDR_INFO_MASK GENMASK(5, 4) +#define B_BE_HC_ADDR_HIT_EN BIT(3) +#define B_BE_RX_ADDR_LINK_TO_MLO BIT(2) +#define B_BE_HDR_CNV BIT(1) +#define B_BE_RX_HDR_CNV_EN BIT(0) +#define TRXCFG_MPDU_PROC_RX_HDR_CONV 0x00000000 + #define R_BE_MPDU_RX_ERR_IMR 0x9CF4 #define B_BE_LEN_ERR_IMR BIT(3) #define B_BE_TIMEOUT_ERR_IMR BIT(1) @@ -5472,6 +5526,22 @@ #define B_BE_RX_HANG_ERROR BIT(1) #define B_BE_TX_HANG_ERROR BIT(0) +#define R_BE_TXPKTCTL_MPDUINFO_CFG 0x9F10 +#define B_BE_MPDUINFO_FEN BIT(31) +#define B_BE_MPDUINFO_PKTID_MASK GENMASK(27, 16) +#define B_BE_MPDUINFO_B1_BADDR_MASK GENMASK(5, 0) +#define MPDU_INFO_B1_OFST 18 + +#define R_BE_TXPKTCTL_B0_PRELD_CFG0 0x9F48 +#define B_BE_B0_PRELD_FEN BIT(31) +#define B_BE_B0_PRELD_USEMAXSZ_MASK GENMASK(25, 16) +#define B_BE_B0_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8) +#define B_BE_B0_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0) + +#define R_BE_TXPKTCTL_B0_PRELD_CFG1 0x9F4C +#define B_BE_B0_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8) +#define B_BE_B0_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0) + #define R_BE_TXPKTCTL_B0_ERRFLAG_IMR 0x9F78 #define B_BE_B0_IMR_DBG_USRCTL_RLSBMPLEN BIT(25) #define B_BE_B0_IMR_DBG_USRCTL_RDNRLSCMD BIT(24) @@ -5502,6 +5572,16 @@ B_BE_B0_IMR_ERR_PRELD_RLSPKTSZERR | \ B_BE_B0_IMR_ERR_PRELD_ENTNUMCFG) +#define R_BE_TXPKTCTL_B1_PRELD_CFG0 0x9F88 +#define B_BE_B1_PRELD_FEN BIT(31) +#define B_BE_B1_PRELD_USEMAXSZ_MASK GENMASK(25, 16) +#define B_BE_B1_PRELD_CAM_G1ENTNUM_MASK GENMASK(12, 8) +#define B_BE_B1_PRELD_CAM_G0ENTNUM_MASK GENMASK(4, 0) + +#define R_BE_TXPKTCTL_B1_PRELD_CFG1 0x9F8C +#define B_BE_B1_PRELD_NXT_TXENDWIN_MASK GENMASK(11, 8) +#define B_BE_B1_PRELD_NXT_RSVMINSZ_MASK GENMASK(7, 0) + #define R_BE_TXPKTCTL_B1_ERRFLAG_IMR 0x9FB8 #define B_BE_B1_IMR_DBG_USRCTL_RLSBMPLEN BIT(25) #define B_BE_B1_IMR_DBG_USRCTL_RDNRLSCMD BIT(24) @@ -5532,6 +5612,12 @@ B_BE_B1_IMR_ERR_PRELD_RLSPKTSZERR | \ B_BE_B1_IMR_ERR_PRELD_ENTNUMCFG) +#define R_BE_MLO_INIT_CTL 0xA114 +#define B_BE_MLO_TABLE_INIT_DONE BIT(31) +#define B_BE_MLO_TABLE_CLR_DONE BIT(30) +#define B_BE_MLO_TABLE_REINIT BIT(23) +#define B_BE_MLO_TABLE_HW_FLAG_CLR BIT(22) + #define R_BE_MLO_ERR_IDCT_IMR 0xA128 #define B_BE_MLO_ERR_IDCT_IMR_0 BIT(31) #define B_BE_MLO_ERR_IDCT_IMR_1 BIT(30) @@ -5561,6 +5647,30 @@ #define B_BE_PLRLS_CTL_EVT01_ISR BIT(1) #define B_BE_PLRLS_CTL_FRZTO_ISR BIT(0) +#define R_BE_SS_CTRL 0xA310 +#define B_BE_SS_INIT_DONE BIT(31) +#define B_BE_WDE_STA_DIS BIT(30) +#define B_BE_WARM_INIT BIT(29) +#define B_BE_BAND_TRIG_EN BIT(28) +#define B_BE_RMAC_REQ_DIS BIT(27) +#define B_BE_DLYTX_SEL_MASK GENMASK(25, 24) +#define B_BE_WMM3_SWITCH_MASK GENMASK(23, 22) +#define B_BE_WMM2_SWITCH_MASK GENMASK(21, 20) +#define B_BE_WMM1_SWITCH_MASK GENMASK(19, 18) +#define B_BE_WMM0_SWITCH_MASK GENMASK(17, 16) +#define B_BE_STA_OPTION_CR BIT(15) +#define B_BE_EMLSR_STA_EMPTY_EN BIT(11) +#define B_BE_MLO_HW_CHGLINK_EN BIT(10) +#define B_BE_BAND1_TRIG_EN BIT(9) +#define B_BE_RMAC1_REQ_DIS BIT(8) +#define B_BE_MRT_SRAM_EN BIT(7) +#define B_BE_MRT_INIT_EN BIT(6) +#define B_BE_AVG_LENG_EN BIT(5) +#define B_BE_AVG_INIT_EN BIT(4) +#define B_BE_LENG_INIT_EN BIT(2) +#define B_BE_PMPA_INIT_EN BIT(1) +#define B_BE_SS_EN BIT(0) + #define R_BE_INTERRUPT_MASK_REG 0xA3F0 #define B_BE_PLE_B_PKTID_ERR_IMR BIT(2) #define B_BE_RPT_TIMEOUT_IMR BIT(1) @@ -5705,6 +5815,13 @@ #define B_BE_ADDRSRCH_EN BIT(1) #define B_BE_BTCOEX_EN BIT(0) +#define R_BE_CMAC_SHARE_ACQCHK_CFG_0 0x0E010 +#define B_BE_ACQCHK_ERR_FLAG_MASK GENMASK(31, 24) +#define B_BE_R_ACQCHK_ENTRY_IDX_SEL_MASK GENMASK(7, 4) +#define B_BE_MACID_ACQ_GRP1_CLR_P BIT(3) +#define B_BE_MACID_ACQ_GRP0_CLR_P BIT(2) +#define B_BE_R_MACID_ACQ_CHK_EN BIT(0) + #define R_BE_CMAC_FUNC_EN 0x10000 #define R_BE_CMAC_FUNC_EN_C1 0x14000 #define B_BE_CMAC_CRPRT BIT(31) @@ -5756,6 +5873,40 @@ B_BE_RMAC_CKEN | B_BE_TXTIME_CKEN | B_BE_RESP_PKTCTL_CKEN | \ B_BE_SIGB_CKEN) +#define R_BE_TX_SUB_BAND_VALUE 0x10088 +#define R_BE_TX_SUB_BAND_VALUE_C1 0x14088 +#define B_BE_PRI20_BITMAP_MASK GENMASK(31, 16) +#define BE_PRI20_BITMAP_MAX 15 +#define B_BE_TXSB_160M_MASK GENMASK(15, 12) +#define S_BE_TXSB_160M_0 0 +#define S_BE_TXSB_160M_1 1 +#define B_BE_TXSB_80M_MASK GENMASK(11, 8) +#define S_BE_TXSB_80M_0 0 +#define S_BE_TXSB_80M_2 2 +#define S_BE_TXSB_80M_4 4 +#define B_BE_TXSB_40M_MASK GENMASK(7, 4) +#define S_BE_TXSB_40M_0 0 +#define S_BE_TXSB_40M_1 1 +#define S_BE_TXSB_40M_4 4 +#define B_BE_TXSB_20M_MASK GENMASK(3, 0) +#define S_BE_TXSB_20M_8 8 +#define S_BE_TXSB_20M_4 4 +#define S_BE_TXSB_20M_2 2 + +#define R_BE_PTCL_RRSR0 0x1008C +#define R_BE_PTCL_RRSR0_C1 0x1408C +#define B_BE_RRSR_HE_MASK GENMASK(31, 24) +#define B_BE_RRSR_VHT_MASK GENMASK(23, 16) +#define B_BE_RRSR_HT_MASK GENMASK(15, 8) +#define B_BE_RRSR_OFDM_MASK GENMASK(7, 0) + +#define R_BE_PTCL_RRSR1 0x10090 +#define R_BE_PTCL_RRSR1_C1 0x14090 +#define B_BE_RRSR_EHT_MASK GENMASK(23, 16) +#define B_BE_RRSR_RATE_EN_MASK GENMASK(12, 8) +#define B_BE_RSC_MASK GENMASK(7, 6) +#define B_BE_RRSR_CCK_MASK GENMASK(3, 0) + #define R_BE_CMAC_ERR_IMR 0x10160 #define R_BE_CMAC_ERR_IMR_C1 0x14160 #define B_BE_CMAC_FW_ERR_IDCT_EN BIT(16) @@ -5843,6 +5994,55 @@ #define B_BE_P0_SYNC_PORT_SRC_SEL_MASK GENMASK(26, 24) #define B_BE_P0_TSFTR_SYNC_OFFSET_MASK GENMASK(18, 0) +#define R_BE_EDCA_BCNQ_PARAM 0x10324 +#define R_BE_EDCA_BCNQ_PARAM_C1 0x14324 +#define B_BE_BCNQ_CW_MASK GENMASK(31, 24) +#define B_BE_BCNQ_AIFS_MASK GENMASK(23, 16) +#define BCN_IFS_25US 0x19 +#define B_BE_PIFS_MASK GENMASK(15, 8) +#define B_BE_FORCE_BCN_IFS_MASK GENMASK(7, 0) + +#define R_BE_PREBKF_CFG_0 0x10338 +#define R_BE_PREBKF_CFG_0_C1 0x14338 +#define B_BE_100NS_TIME_MASK GENMASK(28, 24) +#define B_BE_RX_AIR_END_TIME_MASK GENMASK(22, 16) +#define B_BE_MACTX_LATENCY_MASK GENMASK(10, 8) +#define B_BE_PREBKF_TIME_MASK GENMASK(4, 0) + +#define R_BE_CCA_CFG_0 0x10340 +#define R_BE_CCA_CFG_0_C1 0x14340 +#define B_BE_R_SIFS_AGGR_TIME_V1_MASK GENMASK(31, 24) +#define B_BE_EDCCA_SEC160_EN BIT(23) +#define B_BE_EDCCA_SEC80_EN BIT(22) +#define B_BE_EDCCA_SEC40_EN BIT(21) +#define B_BE_EDCCA_SEC20_EN BIT(20) +#define B_BE_SEC160_EN BIT(19) +#define B_BE_CCA_BITMAP_EN BIT(18) +#define B_BE_TXPKTCTL_RST_EDCA_EN BIT(17) +#define B_BE_WMAC_RST_EDCA_EN BIT(16) +#define B_BE_TXFAIL_BRK_TXOP_EN BIT(11) +#define B_BE_EDCCA_PER20_BITMAP_SIFS_EN BIT(10) +#define B_BE_NO_GNT_WL_BRK_TXOP_EN BIT(9) +#define B_BE_NAV_BRK_TXOP_EN BIT(8) +#define B_BE_TX_NAV_EN BIT(7) +#define B_BE_BCN_IGNORE_EDCCA BIT(6) +#define B_BE_NO_GNT_WL_EN BIT(5) +#define B_BE_EDCCA_EN BIT(4) +#define B_BE_SEC80_EN BIT(3) +#define B_BE_SEC40_EN BIT(2) +#define B_BE_SEC20_EN BIT(1) +#define B_BE_CCA_EN BIT(0) + +#define R_BE_CTN_CFG_0 0x1034C +#define R_BE_CTN_CFG_0_C1 0x1434C +#define B_BE_OTHER_LINK_BKF_BLK_TX_THD_MASK GENMASK(30, 24) +#define B_BE_CCK_SIFS_COMP_MASK GENMASK(22, 16) +#define B_BE_PIFS_TIMEUNIT_MASK GENMASK(15, 14) +#define B_BE_PREBKF_TIME_NONAC_MASK GENMASK(12, 8) +#define B_BE_SR_TX_EN BIT(2) +#define B_BE_NAV_BLK_MGQ BIT(1) +#define B_BE_NAV_BLK_HGQ BIT(0) + #define R_BE_MUEDCA_BE_PARAM_0 0x10350 #define R_BE_MUEDCA_BK_PARAM_0 0x10354 #define R_BE_MUEDCA_VI_PARAM_0 0x10358 @@ -5855,6 +6055,63 @@ #define B_BE_SET_MUEDCATIMER_TF_0 BIT(4) #define B_BE_MUEDCA_EN_0 BIT(0) +#define R_BE_TB_CHK_CCA_NAV 0x103AC +#define R_BE_TB_CHK_CCA_NAV_C1 0x143AC +#define B_BE_TB_CHK_TX_NAV BIT(15) +#define B_BE_TB_CHK_INTRA_NAV BIT(14) +#define B_BE_TB_CHK_BASIC_NAV BIT(13) +#define B_BE_TB_CHK_NO_GNT_WL BIT(12) +#define B_BE_TB_CHK_EDCCA_S160 BIT(11) +#define B_BE_TB_CHK_EDCCA_S80 BIT(10) +#define B_BE_TB_CHK_EDCCA_S40 BIT(9) +#define B_BE_TB_CHK_EDCCA_S20 BIT(8) +#define B_BE_TB_CHK_CCA_S160 BIT(7) +#define B_BE_TB_CHK_CCA_S80 BIT(6) +#define B_BE_TB_CHK_CCA_S40 BIT(5) +#define B_BE_TB_CHK_CCA_S20 BIT(4) +#define B_BE_TB_CHK_EDCCA_BITMAP BIT(3) +#define B_BE_TB_CHK_CCA_BITMAP BIT(2) +#define B_BE_TB_CHK_EDCCA_P20 BIT(1) +#define B_BE_TB_CHK_CCA_P20 BIT(0) + +#define R_BE_HE_SIFS_CHK_CCA_NAV 0x103B4 +#define R_BE_HE_SIFS_CHK_CCA_NAV_C1 0x143B4 +#define B_BE_HE_SIFS_CHK_TX_NAV BIT(15) +#define B_BE_HE_SIFS_CHK_INTRA_NAV BIT(14) +#define B_BE_HE_SIFS_CHK_BASIC_NAV BIT(13) +#define B_BE_HE_SIFS_CHK_NO_GNT_WL BIT(12) +#define B_BE_HE_SIFS_CHK_EDCCA_S160 BIT(11) +#define B_BE_HE_SIFS_CHK_EDCCA_S80 BIT(10) +#define B_BE_HE_SIFS_CHK_EDCCA_S40 BIT(9) +#define B_BE_HE_SIFS_CHK_EDCCA_S20 BIT(8) +#define B_BE_HE_SIFS_CHK_CCA_S160 BIT(7) +#define B_BE_HE_SIFS_CHK_CCA_S80 BIT(6) +#define B_BE_HE_SIFS_CHK_CCA_S40 BIT(5) +#define B_BE_HE_SIFS_CHK_CCA_S20 BIT(4) +#define B_BE_HE_SIFS_CHK_EDCCA_BITMAP BIT(3) +#define B_BE_HE_SIFS_CHK_CCA_BITMAP BIT(2) +#define B_BE_HE_SIFS_CHK_EDCCA_P20 BIT(1) +#define B_BE_HE_SIFS_CHK_CCA_P20 BIT(0) + +#define R_BE_HE_CTN_CHK_CCA_NAV 0x103C4 +#define R_BE_HE_CTN_CHK_CCA_NAV_C1 0x143C4 +#define B_BE_HE_CTN_CHK_TX_NAV BIT(15) +#define B_BE_HE_CTN_CHK_INTRA_NAV BIT(14) +#define B_BE_HE_CTN_CHK_BASIC_NAV BIT(13) +#define B_BE_HE_CTN_CHK_NO_GNT_WL BIT(12) +#define B_BE_HE_CTN_CHK_EDCCA_S160 BIT(11) +#define B_BE_HE_CTN_CHK_EDCCA_S80 BIT(10) +#define B_BE_HE_CTN_CHK_EDCCA_S40 BIT(9) +#define B_BE_HE_CTN_CHK_EDCCA_S20 BIT(8) +#define B_BE_HE_CTN_CHK_CCA_S160 BIT(7) +#define B_BE_HE_CTN_CHK_CCA_S80 BIT(6) +#define B_BE_HE_CTN_CHK_CCA_S40 BIT(5) +#define B_BE_HE_CTN_CHK_CCA_S20 BIT(4) +#define B_BE_HE_CTN_CHK_EDCCA_BITMAP BIT(3) +#define B_BE_HE_CTN_CHK_CCA_BITMAP BIT(2) +#define B_BE_HE_CTN_CHK_EDCCA_P20 BIT(1) +#define B_BE_HE_CTN_CHK_CCA_P20 BIT(0) + #define R_BE_SCHEDULE_ERR_IMR 0x103E8 #define R_BE_SCHEDULE_ERR_IMR_C1 0x143E8 #define B_BE_FSM_TIMEOUT_ERR_INT_EN BIT(0) @@ -5980,12 +6237,51 @@ #define R_BE_PORT_HGQ_WINDOW_CFG 0x105A0 #define R_BE_PORT_HGQ_WINDOW_CFG_C1 0x145A0 +#define R_BE_PTCL_COMMON_SETTING_0 0x10800 +#define R_BE_PTCL_COMMON_SETTING_0_C1 0x14800 +#define B_BE_PCIE_MODE_MASK GENMASK(15, 14) +#define B_BE_CPUMGQ_LIFETIME_EN BIT(8) +#define B_BE_MGQ_LIFETIME_EN BIT(7) +#define B_BE_LIFETIME_EN BIT(6) +#define B_BE_DIS_PTCL_CLK_GATING BIT(5) +#define B_BE_PTCL_TRIGGER_SS_EN_UL BIT(4) +#define B_BE_PTCL_TRIGGER_SS_EN_1 BIT(3) +#define B_BE_PTCL_TRIGGER_SS_EN_0 BIT(2) +#define B_BE_CMAC_TX_MODE_1 BIT(1) +#define B_BE_CMAC_TX_MODE_0 BIT(0) + +#define R_BE_TB_PPDU_CTRL 0x1080C +#define R_BE_TB_PPDU_CTRL_C1 0x1480C +#define B_BE_TB_PPDU_BK_DIS BIT(15) +#define B_BE_TB_PPDU_BE_DIS BIT(14) +#define B_BE_TB_PPDU_VI_DIS BIT(13) +#define B_BE_TB_PPDU_VO_DIS BIT(12) +#define B_BE_QOSNULL_UPD_MUEDCA_EN BIT(3) +#define B_BE_TB_BYPASS_TXPWR BIT(2) +#define B_BE_SW_PREFER_AC_MASK GENMASK(1, 0) + +#define R_BE_AMPDU_AGG_LIMIT 0x10810 +#define R_BE_AMPDU_AGG_LIMIT_C1 0x14810 +#define B_BE_AMPDU_MAX_TIME_MASK GENMASK(31, 24) +#define AMPDU_MAX_TIME 0x9E +#define B_BE_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16) +#define B_BE_RTS_MAX_AGG_NUM_MASK GENMASK(15, 8) +#define B_BE_MAX_AGG_NUM_MASK GENMASK(7, 0) + #define R_BE_AGG_LEN_HT_0 0x10814 #define R_BE_AGG_LEN_HT_0_C1 0x14814 #define B_BE_AMPDU_MAX_LEN_HT_MASK GENMASK(31, 16) #define B_BE_RTS_TXTIME_TH_MASK GENMASK(15, 8) #define B_BE_RTS_LEN_TH_MASK GENMASK(7, 0) +#define R_BE_SIFS_SETTING 0x10824 +#define R_BE_SIFS_SETTING_C1 0x14824 +#define B_BE_HW_CTS2SELF_PKT_LEN_TH_MASK GENMASK(31, 24) +#define B_BE_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK GENMASK(23, 18) +#define B_BE_HW_CTS2SELF_EN BIT(16) +#define B_BE_SPEC_SIFS_OFDM_PTCL_MASK GENMASK(15, 8) +#define B_BE_SPEC_SIFS_CCK_PTCL_MASK GENMASK(7, 0) + #define R_BE_MBSSID_DROP_0 0x1083C #define R_BE_MBSSID_DROP_0_C1 0x1483C #define B_BE_GI_LTF_FB_SEL BIT(30) @@ -6084,6 +6380,24 @@ #define B_BE_TXPRT_FULL_DROP_ERR BIT(9) #define B_BE_F2PCMDRPT_FULL_DROP_ERR BIT(8) +#define R_BE_PTCL_FSM_MON 0x108E8 +#define R_BE_PTCL_FSM_MON_C1 0x148E8 +#define B_BE_PTCL_FSM2_TO_MODE BIT(30) +#define B_BE_PTCL_FSM2_TO_THR_MASK GENMASK(29, 24) +#define B_BE_PTCL_FSM1_TO_MODE BIT(22) +#define B_BE_PTCL_FSM1_TO_THR_MASK GENMASK(21, 16) +#define B_BE_PTCL_FSM0_TO_MODE BIT(14) +#define B_BE_PTCL_FSM0_TO_THR_MASK GENMASK(13, 8) +#define B_BE_PTCL_TX_ARB_TO_MODE BIT(6) +#define B_BE_PTCL_TX_ARB_TO_THR_MASK GENMASK(5, 0) + +#define R_BE_PTCL_TX_CTN_SEL 0x108EC +#define R_BE_PTCL_TX_CTN_SEL_C1 0x148EC +#define B_BE_PTCL_TXOP_STAT BIT(8) +#define B_BE_PTCL_BUSY BIT(7) +#define B_BE_PTCL_DROP BIT(5) +#define B_BE_PTCL_TX_QUEUE_IDX_MASK GENMASK(4, 0) + #define R_BE_RX_ERROR_FLAG 0x10C00 #define R_BE_RX_ERROR_FLAG_C1 0x14C00 #define B_BE_RX_CSI_NOT_RELEASE_ERROR BIT(31) @@ -6198,6 +6512,15 @@ B_BE_RX_RU0_FSM_HANG_ERROR_IMR | \ B_BE_RX_GET_NULL_PKT_ERROR_IMR) +#define R_BE_RX_CTRL_1 0x10C0C +#define R_BE_RX_CTRL_1_C1 0x14C0C +#define B_BE_RXDMA_TXRPT_QUEUE_ID_SW_MASK GENMASK(30, 25) +#define B_BE_RXDMA_F2PCMDRPT_QUEUE_ID_SW_MASK GENMASK(23, 18) +#define B_BE_RXDMA_TXRPT_PORT_ID_SW_MASK GENMASK(17, 14) +#define B_BE_RXDMA_F2PCMDRPT_PORT_ID_SW_MASK GENMASK(13, 10) +#define B_BE_DBG_SEL_MASK GENMASK(1, 0) +#define WLCPU_RXCH2_QID 0xA + #define R_BE_TX_ERROR_FLAG 0x10C6C #define R_BE_TX_ERROR_FLAG_C1 0x14C6C #define B_BE_TX_RU0_FSM_HANG_ERROR BIT(31) @@ -6353,6 +6676,15 @@ #define B_BE_UPD_HGQMD BIT(1) #define B_BE_UPD_TIMIE BIT(0) +#define R_BE_WMTX_TCR_BE_4 0x10E2C +#define R_BE_WMTX_TCR_BE_4_C1 0x14E2C +#define B_BE_UL_EHT_MUMIMO_LTF_MODE BIT(30) +#define B_BE_UL_HE_MUMIMO_LTF_MODE BIT(29) +#define B_BE_EHT_HE_PPDU_4XLTF_ZLD_USTIMER_MASK GENMASK(28, 24) +#define B_BE_EHT_HE_PPDU_2XLTF_ZLD_USTIMER_MASK GENMASK(20, 16) +#define B_BE_NON_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(12, 8) +#define B_BE_LEGACY_PPDU_ZLD_USTIMER_MASK GENMASK(4, 0) + #define R_BE_RSP_CHK_SIG 0x11000 #define R_BE_RSP_CHK_SIG_C1 0x15000 #define B_BE_RSP_STATIC_RTS_CHK_SERV_BW_EN BIT(30) @@ -6385,6 +6717,46 @@ #define WMAC_SPEC_SIFS_OFDM_1115E 0x11 #define B_BE_WMAC_SPEC_SIFS_CCK_MASK GENMASK(7, 0) +#define R_BE_TRXPTCL_RESP_1 0x11008 +#define R_BE_TRXPTCL_RESP_1_C1 0x15008 +#define B_BE_WMAC_RESP_SR_MODE_EN BIT(31) +#define B_BE_FTM_RRSR_RATE_EN_MASK GENMASK(28, 24) +#define B_BE_NESS_MASK GENMASK(23, 22) +#define B_BE_WMAC_RESP_DOPPLEB_BE_EN BIT(21) +#define B_BE_WMAC_RESP_DCM_EN BIT(20) +#define B_BE_WMAC_CLR_ABORT_RESP_TX_CNT BIT(15) +#define B_BE_WMAC_RESP_REF_RATE_SEL BIT(12) +#define B_BE_WMAC_RESP_REF_RATE_MASK GENMASK(11, 0) + +#define R_BE_MAC_LOOPBACK 0x11020 +#define R_BE_MAC_LOOPBACK_C1 0x15020 +#define B_BE_MACLBK_DIS_GCLK BIT(30) +#define B_BE_MACLBK_STS_EN BIT(29) +#define B_BE_MACLBK_RDY_PERIOD_MASK GENMASK(28, 17) +#define B_BE_MACLBK_PLCP_DLY_MASK GENMASK(16, 8) +#define S_BE_MACLBK_PLCP_DLY_DEF 0x28 +#define B_BE_MACLBK_RDY_NUM_MASK GENMASK(7, 3) +#define B_BE_MACLBK_EN BIT(0) + +#define R_BE_WMAC_NAV_CTL 0x11080 +#define R_BE_WMAC_NAV_CTL_C1 0x15080 +#define B_BE_WMAC_NAV_UPPER_EN BIT(26) +#define B_BE_WMAC_0P125US_TIMER_MASK GENMASK(25, 18) +#define B_BE_WMAC_PLCP_UP_NAV_EN BIT(17) +#define B_BE_WMAC_TF_UP_NAV_EN BIT(16) +#define B_BE_WMAC_NAV_UPPER_MASK GENMASK(15, 8) +#define NAV_25MS 0xC4 +#define B_BE_WMAC_RTS_RST_DUR_MASK GENMASK(7, 0) + +#define R_BE_RXTRIG_TEST_USER_2 0x110B0 +#define R_BE_RXTRIG_TEST_USER_2_C1 0x150B0 +#define B_BE_RXTRIG_MACID_MASK GENMASK(31, 24) +#define B_BE_RXTRIG_RU26_DIS BIT(21) +#define B_BE_RXTRIG_FCSCHK_EN BIT(20) +#define B_BE_RXTRIG_PORT_SEL_MASK GENMASK(19, 17) +#define B_BE_RXTRIG_EN BIT(16) +#define B_BE_RXTRIG_USERINFO_2_MASK GENMASK(15, 0) + #define R_BE_TRXPTCL_ERROR_INDICA_MASK 0x110BC #define R_BE_TRXPTCL_ERROR_INDICA_MASK_C1 0x150BC #define B_BE_WMAC_FTM_TIMEOUT_MODE BIT(30) @@ -6526,6 +6898,103 @@ #define B_BE_BFMEE_HT_CSI_RATE_MASK GENMASK(7, 0) #define CSI_INIT_RATE_EHT 0x3 +#define R_BE_WMAC_ACK_BA_RESP_LEGACY 0x11200 +#define R_BE_WMAC_ACK_BA_RESP_LEGACY_C1 0x15200 +#define B_BE_ACK_BA_RESP_LEGACY_CHK_NSTR BIT(16) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_TX_NAV BIT(15) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_INTRA_NAV BIT(14) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_BASIC_NAV BIT(13) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_BTCCA BIT(12) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA160 BIT(11) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA80 BIT(10) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA40 BIT(9) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_EDCCA20 BIT(8) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA_PER20_BMP BIT(7) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_CCA_PER20_BMP BIT(6) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA160 BIT(5) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA80 BIT(4) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA40 BIT(3) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_SEC_CCA20 BIT(2) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_EDCCA BIT(1) +#define B_BE_ACK_BA_RESP_LEGACY_CHK_CCA BIT(0) + +#define R_BE_WMAC_ACK_BA_RESP_HE 0x11204 +#define R_BE_WMAC_ACK_BA_RESP_HE_C1 0x15204 +#define B_BE_ACK_BA_RESP_HE_CHK_NSTR BIT(16) +#define B_BE_ACK_BA_RESP_HE_CHK_TX_NAV BIT(15) +#define B_BE_ACK_BA_RESP_HE_CHK_INTRA_NAV BIT(14) +#define B_BE_ACK_BA_RESP_HE_CHK_BASIC_NAV BIT(13) +#define B_BE_ACK_BA_RESP_HE_CHK_BTCCA BIT(12) +#define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA160 BIT(11) +#define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA80 BIT(10) +#define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA40 BIT(9) +#define B_BE_ACK_BA_RESP_HE_CHK_SEC_EDCCA20 BIT(8) +#define B_BE_ACK_BA_RESP_HE_CHK_EDCCA_PER20_BMP BIT(7) +#define B_BE_ACK_BA_RESP_HE_CHK_CCA_PER20_BMP BIT(6) +#define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA160 BIT(5) +#define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA80 BIT(4) +#define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA40 BIT(3) +#define B_BE_ACK_BA_RESP_HE_CHK_SEC_CCA20 BIT(2) +#define B_BE_ACK_BA_RESP_HE_CHK_EDCCA BIT(1) +#define B_BE_ACK_BA_RESP_HE_CHK_CCA BIT(0) + +#define R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC 0x11208 +#define R_BE_WMAC_ACK_BA_RESP_EHT_LEG_PUNC_C1 0x15208 +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_NSTR BIT(16) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_TX_NAV BIT(15) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_INTRA_NAV BIT(14) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_BASIC_NAV BIT(13) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_BTCCA BIT(12) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA160 BIT(11) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA80 BIT(10) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA40 BIT(9) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_EDCCA20 BIT(8) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA_PER20_BMP BIT(7) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_CCA_PER20_BMP BIT(6) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA160 BIT(5) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA80 BIT(4) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA40 BIT(3) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_SEC_CCA20 BIT(2) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_EDCCA BIT(1) +#define B_BE_ACK_BA_EHT_LEG_PUNC_CHK_CCA BIT(0) + +#define R_BE_RCR 0x11400 +#define R_BE_RCR_C1 0x15400 +#define B_BE_BUSY_CHKSN BIT(15) +#define B_BE_DYN_CHEN BIT(14) +#define B_BE_AUTO_RST BIT(13) +#define B_BE_TIMER_SEL BIT(12) +#define B_BE_STOP_RX_IN BIT(11) +#define B_BE_PSR_RDY_CHKDIS BIT(10) +#define B_BE_DRV_INFO_SZ_MASK GENMASK(9, 8) +#define B_BE_HDR_CNV_SZ_MASK GENMASK(7, 6) +#define B_BE_PHY_RPT_SZ_MASK GENMASK(5, 4) +#define B_BE_CH_EN BIT(0) + +#define R_BE_DLK_PROTECT_CTL 0x11402 +#define R_BE_DLK_PROTECT_CTL_C1 0x15402 +#define B_BE_RX_DLK_CCA_TIME_MASK GENMASK(15, 8) +#define TRXCFG_RMAC_CCA_TO 32 +#define B_BE_RX_DLK_DATA_TIME_MASK GENMASK(7, 4) +#define TRXCFG_RMAC_DATA_TO 15 +#define B_BE_RX_DLK_RST_FSM BIT(3) +#define B_BE_RX_DLK_RST_SKIPDMA BIT(2) +#define B_BE_RX_DLK_RST_EN BIT(1) +#define B_BE_RX_DLK_INT_EN BIT(0) + +#define R_BE_PLCP_HDR_FLTR 0x11404 +#define R_BE_PLCP_HDR_FLTR_C1 0x15404 +#define B_BE_PLCP_RXFA_RESET_TYPE_MASK GENMASK(15, 12) +#define B_BE_PLCP_RXFA_RESET_EN BIT(11) +#define B_BE_DIS_CHK_MIN_LEN BIT(8) +#define B_BE_HE_SIGB_CRC_CHK BIT(6) +#define B_BE_VHT_MU_SIGB_CRC_CHK BIT(5) +#define B_BE_VHT_SU_SIGB_CRC_CHK BIT(4) +#define B_BE_SIGA_CRC_CHK BIT(3) +#define B_BE_LSIG_PARITY_CHK_EN BIT(2) +#define B_BE_CCK_SIG_CHK BIT(1) +#define B_BE_CCK_CRC_CHK BIT(0) + #define R_BE_RX_FLTR_OPT 0x11420 #define R_BE_RX_FLTR_OPT_C1 0x15420 #define B_BE_UID_FILTER_MASK GENMASK(31, 24) @@ -6545,6 +7014,55 @@ #define B_BE_A_A1_MATCH BIT(1) #define B_BE_SNIFFER_MODE BIT(0) +#define R_BE_CTRL_FLTR 0x11424 +#define R_BE_CTRL_FLTR_C1 0x15424 +#define B_BE_CTRL_STYPE_MASK GENMASK(15, 0) +#define RX_FLTR_FRAME_DROP_BE 0x0000 +#define RX_FLTR_FRAME_ACCEPT_BE 0xFFFF + +#define R_BE_MGNT_FLTR 0x11428 +#define R_BE_MGNT_FLTR_C1 0x15428 +#define B_BE_MGNT_STYPE_MASK GENMASK(15, 0) + +#define R_BE_DATA_FLTR 0x1142C +#define R_BE_DATA_FLTR_C1 0x1542C +#define B_BE_DATA_STYPE_MASK GENMASK(15, 0) + +#define R_BE_ADDR_CAM_CTRL 0x11434 +#define R_BE_ADDR_CAM_CTRL_C1 0x15434 +#define B_BE_ADDR_CAM_RANGE_MASK GENMASK(23, 16) +#define ADDR_CAM_SERCH_RANGE 0x7f +#define B_BE_ADDR_CAM_CMPLIMT_MASK GENMASK(15, 12) +#define B_BE_ADDR_CAM_IORST BIT(10) +#define B_BE_DIS_ADDR_CLK_GATED BIT(9) +#define B_BE_ADDR_CAM_CLR BIT(8) +#define B_BE_ADDR_CAM_A2_B0_CHK BIT(2) +#define B_BE_ADDR_CAM_SRCH_PERPKT BIT(1) +#define B_BE_ADDR_CAM_EN BIT(0) + +#define R_BE_RESPBA_CAM_CTRL 0x1143C +#define R_BE_RESPBA_CAM_CTRL_C1 0x1543C +#define B_BE_BACAM_SKIP_ALL_QOSNULL BIT(24) +#define B_BE_BACAM_STD_SSN_SEL BIT(20) +#define B_BE_BACAM_TEMP_SZ_MASK GENMASK(17, 16) +#define B_BE_BACAM_RST_IDX_MASK GENMASK(15, 8) +#define B_BE_BACAM_SHIFT_POLL BIT(7) +#define B_BE_BACAM_IORST BIT(6) +#define B_BE_BACAM_GCK_DIS BIT(5) +#define B_BE_COMPL_VAL BIT(3) +#define B_BE_SSN_SEL BIT(2) +#define B_BE_BACAM_RST_MASK GENMASK(1, 0) +#define S_BE_BACAM_RST_DONE 0 +#define S_BE_BACAM_RST_ENT 1 +#define S_BE_BACAM_RST_ALL 2 + +#define R_BE_RX_SR_CTRL 0x1144A +#define R_BE_RX_SR_CTRL_C1 0x1544A +#define B_BE_SR_OP_MODE_MASK GENMASK(5, 4) +#define B_BE_SRG_CHK_EN BIT(2) +#define B_BE_SR_CTRL_PLCP_EN BIT(1) +#define B_BE_SR_EN BIT(0) + #define R_BE_CSIRPT_OPTION 0x11464 #define R_BE_CSIRPT_OPTION_C1 0x15464 #define B_BE_CSIPRT_EHTSU_AID_EN BIT(26) @@ -6590,6 +7108,29 @@ B_BE_RX_ERR_STS_ACT_TO_MSK | \ B_BE_RX_ERR_TRIG_ACT_TO_MSK) +#define R_BE_RX_PLCP_EXT_OPTION_1 0x11514 +#define R_BE_RX_PLCP_EXT_OPTION_1_C1 0x15514 +#define B_BE_PLCP_CLOSE_RX_UNSPUUORT BIT(19) +#define B_BE_PLCP_CLOSE_RX_BB_BRK BIT(18) +#define B_BE_PLCP_CLOSE_RX_PSDU_PRES BIT(17) +#define B_BE_PLCP_CLOSE_RX_NDP BIT(16) +#define B_BE_PLCP_NSS_SRC BIT(11) +#define B_BE_PLCP_DOPPLEB_BE_SRC BIT(10) +#define B_BE_PLCP_STBC_SRC BIT(9) +#define B_BE_PLCP_SU_PSDU_LEN_SRC BIT(8) +#define B_BE_PLCP_RXSB_SRC BIT(7) +#define B_BE_PLCP_BW_SRC_MASK GENMASK(6, 5) +#define B_BE_PLCP_GILTF_SRC BIT(4) +#define B_BE_PLCP_NSTS_SRC BIT(3) +#define B_BE_PLCP_MCS_SRC BIT(2) +#define B_BE_PLCP_CH20_WIDATA_SRC BIT(1) +#define B_BE_PLCP_PPDU_TYPE_SRC BIT(0) + +#define R_BE_RESP_CSI_RESERVED_PAGE 0x11810 +#define R_BE_RESP_CSI_RESERVED_PAGE_C1 0x15810 +#define B_BE_CSI_RESERVED_PAGE_NUM_MASK GENMASK(27, 16) +#define B_BE_CSI_RESERVED_START_PAGE_MASK GENMASK(11, 0) + #define R_BE_RESP_IMR 0x11884 #define R_BE_RESP_IMR_C1 0x15884 #define B_BE_RESP_TBL_FLAG_ERR_ISR_EN BIT(17) |