diff options
Diffstat (limited to 'drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h')
| -rw-r--r-- | drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 19 |
1 files changed, 8 insertions, 11 deletions
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h index c8515f506872..bf36399d0057 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h @@ -7,13 +7,11 @@ #define QCOM_PHY_QMP_PCS_V2_H_ /* Only for QMP V2 PHY - PCS registers */ +#define QPHY_V2_PCS_SW_RESET 0x000 #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004 +#define QPHY_V2_PCS_START_CONTROL 0x008 #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024 #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028 -#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034 -#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x038 -#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x03c -#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x040 #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054 #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058 #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060 @@ -30,17 +28,16 @@ #define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8 #define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc #define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0 - -/* UFS only ? */ -#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc -#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c -#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140 -#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148 -#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154 +#define QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL 0x0d4 +#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0d8 +#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_STATUS 0x178 +#define QPHY_V2_PCS_USB_PCS_STATUS 0x17c /* USB */ #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 #define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac #define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 +#define QPHY_V2_PCS_PCI_PCS_STATUS 0x174 /* PCI */ + #endif |