diff options
Diffstat (limited to 'drivers/pinctrl/renesas/pfc-r8a77980.c')
| -rw-r--r-- | drivers/pinctrl/renesas/pfc-r8a77980.c | 49 |
1 files changed, 33 insertions, 16 deletions
diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c index ac03309c5c0c..384faa0d6937 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -19,10 +19,10 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ - PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ - PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) @@ -35,7 +35,9 @@ PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ - PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(VDDQ_AVB, "VDDQ_AVB", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33), \ + PIN_NOGP_CFG(VDDQ_GE, "VDDQ_GE", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33) /* * F_() : just information @@ -2813,7 +2815,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_1 MOD_SEL0_0 )) }, - { }, + { /* sentinel */ } }; enum ioctrl_regs { @@ -2830,31 +2832,46 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { [POCCTRL2] = { 0xe6060388, }, [POCCTRL3] = { 0xe606038c, }, [TDSELCTRL] = { 0xe60603c0, }, - { /* sentinel */ }, + { /* sentinel */ } }; static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = pin & 0x1f; - *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; - if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21)) + switch (pin) { + case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21): + *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; return bit; - else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9)) + + case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9): + *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; return bit + 22; - *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; - if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16)) + case RCAR_GP_PIN(2, 10) ... RCAR_GP_PIN(2, 16): + *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; return bit - 10; - if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) || - (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))) + + case RCAR_GP_PIN(2, 17) ... RCAR_GP_PIN(2, 24): + case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 16): + *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg; return bit + 7; - *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg; - if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29)) + case RCAR_GP_PIN(2, 25) ... RCAR_GP_PIN(2, 29): + *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg; return pin - 25; - return -EINVAL; + case PIN_VDDQ_AVB: + *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg; + return 0; + + case PIN_VDDQ_GE: + *pocctrl = pinmux_ioctrl_regs[POCCTRL3].reg; + return 1; + + default: + return -EINVAL; + } } static const struct pinmux_bias_reg pinmux_bias_regs[] = { |