diff options
Diffstat (limited to 'drivers/soc/fsl/qe/ucc_slow.c')
| -rw-r--r-- | drivers/soc/fsl/qe/ucc_slow.c | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/drivers/soc/fsl/qe/ucc_slow.c b/drivers/soc/fsl/qe/ucc_slow.c index 7e11be41ab62..d5ac1ac0ed3c 100644 --- a/drivers/soc/fsl/qe/ucc_slow.c +++ b/drivers/soc/fsl/qe/ucc_slow.c @@ -78,7 +78,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode) us_regs = uccs->us_regs; /* Enable reception and/or transmission on this UCC. */ - gumr_l = qe_ioread32be(&us_regs->gumr_l); + gumr_l = ioread32be(&us_regs->gumr_l); if (mode & COMM_DIR_TX) { gumr_l |= UCC_SLOW_GUMR_L_ENT; uccs->enabled_tx = 1; @@ -87,7 +87,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode) gumr_l |= UCC_SLOW_GUMR_L_ENR; uccs->enabled_rx = 1; } - qe_iowrite32be(gumr_l, &us_regs->gumr_l); + iowrite32be(gumr_l, &us_regs->gumr_l); } EXPORT_SYMBOL(ucc_slow_enable); @@ -99,7 +99,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode) us_regs = uccs->us_regs; /* Disable reception and/or transmission on this UCC. */ - gumr_l = qe_ioread32be(&us_regs->gumr_l); + gumr_l = ioread32be(&us_regs->gumr_l); if (mode & COMM_DIR_TX) { gumr_l &= ~UCC_SLOW_GUMR_L_ENT; uccs->enabled_tx = 0; @@ -108,7 +108,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode) gumr_l &= ~UCC_SLOW_GUMR_L_ENR; uccs->enabled_rx = 0; } - qe_iowrite32be(gumr_l, &us_regs->gumr_l); + iowrite32be(gumr_l, &us_regs->gumr_l); } EXPORT_SYMBOL(ucc_slow_disable); @@ -194,7 +194,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc return ret; } - qe_iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr); + iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr); INIT_LIST_HEAD(&uccs->confQ); @@ -222,27 +222,27 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset); for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) { /* clear bd buffer */ - qe_iowrite32be(0, &bd->buf); + iowrite32be(0, &bd->buf); /* set bd status and length */ - qe_iowrite32be(0, (u32 __iomem *)bd); + iowrite32be(0, (u32 __iomem *)bd); bd++; } /* for last BD set Wrap bit */ - qe_iowrite32be(0, &bd->buf); - qe_iowrite32be(T_W, (u32 __iomem *)bd); + iowrite32be(0, &bd->buf); + iowrite32be(T_W, (u32 __iomem *)bd); /* Init Rx bds */ bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset); for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) { /* set bd status and length */ - qe_iowrite32be(0, (u32 __iomem *)bd); + iowrite32be(0, (u32 __iomem *)bd); /* clear bd buffer */ - qe_iowrite32be(0, &bd->buf); + iowrite32be(0, &bd->buf); bd++; } /* for last BD set Wrap bit */ - qe_iowrite32be(R_W, (u32 __iomem *)bd); - qe_iowrite32be(0, &bd->buf); + iowrite32be(R_W, (u32 __iomem *)bd); + iowrite32be(0, &bd->buf); /* Set GUMR (For more details see the hardware spec.). */ /* gumr_h */ @@ -263,7 +263,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc gumr |= UCC_SLOW_GUMR_H_TXSY; if (us_info->rtsm) gumr |= UCC_SLOW_GUMR_H_RTSM; - qe_iowrite32be(gumr, &us_regs->gumr_h); + iowrite32be(gumr, &us_regs->gumr_h); /* gumr_l */ gumr = (u32)us_info->tdcr | (u32)us_info->rdcr | (u32)us_info->tenc | @@ -276,18 +276,18 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc gumr |= UCC_SLOW_GUMR_L_TINV; if (us_info->tend) gumr |= UCC_SLOW_GUMR_L_TEND; - qe_iowrite32be(gumr, &us_regs->gumr_l); + iowrite32be(gumr, &us_regs->gumr_l); /* Function code registers */ /* if the data is in cachable memory, the 'global' */ /* in the function code should be set. */ - qe_iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->tbmr); - qe_iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->rbmr); + iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->tbmr); + iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->rbmr); /* rbase, tbase are offsets from MURAM base */ - qe_iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase); - qe_iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase); + iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase); + iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase); /* Mux clocking */ /* Grant Support */ @@ -317,14 +317,14 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc } /* Set interrupt mask register at UCC level. */ - qe_iowrite16be(us_info->uccm_mask, &us_regs->uccm); + iowrite16be(us_info->uccm_mask, &us_regs->uccm); /* First, clear anything pending at UCC level, * otherwise, old garbage may come through * as soon as the dam is opened. */ /* Writing '1' clears */ - qe_iowrite16be(0xffff, &us_regs->ucce); + iowrite16be(0xffff, &us_regs->ucce); /* Issue QE Init command */ if (us_info->init_tx && us_info->init_rx) |