diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/samsung/clk-cpu.c | 40 |
1 files changed, 26 insertions, 14 deletions
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index 635ab8cc54a2..eb2b67d08f89 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -44,6 +44,16 @@ typedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *ndata, struct exynos_cpuclk *cpuclk); /** + * struct exynos_cpuclk_chip - Chip specific data for CPU clock + * @pre_rate_cb: callback to run before CPU clock rate change + * @post_rate_cb: callback to run after CPU clock rate change + */ +struct exynos_cpuclk_chip { + exynos_rate_change_fn_t pre_rate_cb; + exynos_rate_change_fn_t post_rate_cb; +}; + +/** * struct exynos_cpuclk - information about clock supplied to a CPU core * @hw: handle between CCF and CPU clock * @alt_parent: alternate parent clock to use when switching the speed @@ -55,8 +65,7 @@ typedef int (*exynos_rate_change_fn_t)(struct clk_notifier_data *ndata, * @clk_nb: clock notifier registered for changes in clock speed of the * primary parent clock * @flags: configuration flags for the CPU clock - * @pre_rate_cb: callback to run before CPU clock rate change - * @post_rate_cb: callback to run after CPU clock rate change + * @chip: chip-specific data for the CPU clock * * This structure holds information required for programming the CPU clock for * various clock speeds. @@ -70,9 +79,7 @@ struct exynos_cpuclk { const unsigned long num_cfgs; struct notifier_block clk_nb; unsigned long flags; - - exynos_rate_change_fn_t pre_rate_cb; - exynos_rate_change_fn_t post_rate_cb; + const struct exynos_cpuclk_chip *chip; }; /* ---- Common code --------------------------------------------------------- */ @@ -420,13 +427,24 @@ static int exynos_cpuclk_notifier_cb(struct notifier_block *nb, cpuclk = container_of(nb, struct exynos_cpuclk, clk_nb); if (event == PRE_RATE_CHANGE) - err = cpuclk->pre_rate_cb(ndata, cpuclk); + err = cpuclk->chip->pre_rate_cb(ndata, cpuclk); else if (event == POST_RATE_CHANGE) - err = cpuclk->post_rate_cb(ndata, cpuclk); + err = cpuclk->chip->post_rate_cb(ndata, cpuclk); return notifier_from_errno(err); } +static const struct exynos_cpuclk_chip exynos_clkcpu_chips[] = { + [CPUCLK_LAYOUT_E4210] = { + .pre_rate_cb = exynos_cpuclk_pre_rate_change, + .post_rate_cb = exynos_cpuclk_post_rate_change, + }, + [CPUCLK_LAYOUT_E5433] = { + .pre_rate_cb = exynos5433_cpuclk_pre_rate_change, + .post_rate_cb = exynos5433_cpuclk_post_rate_change, + }, +}; + /* helper function to register a CPU clock */ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, const struct samsung_cpu_clock *clk_data) @@ -465,13 +483,7 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, cpuclk->lock = &ctx->lock; cpuclk->flags = clk_data->flags; cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb; - if (clk_data->reg_layout == CPUCLK_LAYOUT_E5433) { - cpuclk->pre_rate_cb = exynos5433_cpuclk_pre_rate_change; - cpuclk->post_rate_cb = exynos5433_cpuclk_post_rate_change; - } else { - cpuclk->pre_rate_cb = exynos_cpuclk_pre_rate_change; - cpuclk->post_rate_cb = exynos_cpuclk_post_rate_change; - } + cpuclk->chip = &exynos_clkcpu_chips[clk_data->reg_layout]; ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb); if (ret) { |