diff options
Diffstat (limited to 'include/linux/soundwire')
| -rw-r--r-- | include/linux/soundwire/sdw.h | 33 | ||||
| -rw-r--r-- | include/linux/soundwire/sdw_intel.h | 2 | ||||
| -rw-r--r-- | include/linux/soundwire/sdw_registers.h | 117 |
3 files changed, 137 insertions, 15 deletions
diff --git a/include/linux/soundwire/sdw.h b/include/linux/soundwire/sdw.h index 9c27a32df9bb..76052f12c9f7 100644 --- a/include/linux/soundwire/sdw.h +++ b/include/linux/soundwire/sdw.h @@ -88,10 +88,10 @@ enum sdw_slave_status { * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare */ enum sdw_clk_stop_type { - SDW_CLK_PRE_PREPARE = 0, - SDW_CLK_POST_PREPARE, - SDW_CLK_PRE_DEPREPARE, - SDW_CLK_POST_DEPREPARE, + SDW_CLK_PRE_PREPARE = 0, + SDW_CLK_POST_PREPARE, + SDW_CLK_PRE_DEPREPARE, + SDW_CLK_POST_DEPREPARE, }; /** @@ -152,19 +152,19 @@ enum sdw_data_direction { * * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received * and transmitted. + * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce + * a pseudo random data pattern that is transferred + * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of + * logic 0. The encoding will result in no signal transitions * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of * logic 1. The encoding will result in signal transitions at every bitslot * owned by this Port - * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of - * logic 0. The encoding will result in no signal transitions - * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce - * a pseudo random data pattern that is transferred */ enum sdw_port_data_mode { SDW_PORT_DATA_MODE_NORMAL = 0, - SDW_PORT_DATA_MODE_STATIC_1 = 1, + SDW_PORT_DATA_MODE_PRBS = 1, SDW_PORT_DATA_MODE_STATIC_0 = 2, - SDW_PORT_DATA_MODE_PRBS = 3, + SDW_PORT_DATA_MODE_STATIC_1 = 3, }; /* @@ -426,8 +426,7 @@ int sdw_slave_read_prop(struct sdw_slave *slave); * struct sdw_slave_id - Slave ID * @mfg_id: MIPI Manufacturer ID * @part_id: Device Part ID - * @class_id: MIPI Class ID, unused now. - * Currently a placeholder in MIPI SoundWire Spec + * @class_id: MIPI Class ID (defined starting with SoundWire 1.2 spec) * @unique_id: Device unique ID * @sdw_version: SDW version implemented * @@ -659,10 +658,14 @@ struct sdw_driver { struct device_driver driver; }; -#define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \ - { .mfg_id = (_mfg_id), .part_id = (_part_id), \ +#define SDW_SLAVE_ENTRY_EXT(_mfg_id, _part_id, _version, _c_id, _drv_data) \ + { .mfg_id = (_mfg_id), .part_id = (_part_id), \ + .sdw_version = (_version), .class_id = (_c_id), \ .driver_data = (unsigned long)(_drv_data) } +#define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \ + SDW_SLAVE_ENTRY_EXT((_mfg_id), (_part_id), 0, 0, (_drv_data)) + int sdw_handle_slave_status(struct sdw_bus *bus, enum sdw_slave_status status[]); @@ -952,10 +955,12 @@ int sdw_stream_remove_master(struct sdw_bus *bus, struct sdw_stream_runtime *stream); int sdw_stream_remove_slave(struct sdw_slave *slave, struct sdw_stream_runtime *stream); +int sdw_startup_stream(void *sdw_substream); int sdw_prepare_stream(struct sdw_stream_runtime *stream); int sdw_enable_stream(struct sdw_stream_runtime *stream); int sdw_disable_stream(struct sdw_stream_runtime *stream); int sdw_deprepare_stream(struct sdw_stream_runtime *stream); +void sdw_shutdown_stream(void *sdw_substream); int sdw_bus_prep_clk_stop(struct sdw_bus *bus); int sdw_bus_clk_stop(struct sdw_bus *bus); int sdw_bus_exit_clk_stop(struct sdw_bus *bus); diff --git a/include/linux/soundwire/sdw_intel.h b/include/linux/soundwire/sdw_intel.h index 979b41b5dcb4..120ffddc03d2 100644 --- a/include/linux/soundwire/sdw_intel.h +++ b/include/linux/soundwire/sdw_intel.h @@ -115,6 +115,7 @@ struct sdw_intel_slave_id { * links * @link_list: list to handle interrupts across all links * @shim_lock: mutex to handle concurrent rmw access to shared SHIM registers. + * @shim_mask: flags to track initialization of SHIM shared registers */ struct sdw_intel_ctx { int count; @@ -126,6 +127,7 @@ struct sdw_intel_ctx { struct sdw_intel_slave_id *ids; struct list_head link_list; struct mutex shim_lock; /* lock for access to shared SHIM registers */ + u32 shim_mask; }; /** diff --git a/include/linux/soundwire/sdw_registers.h b/include/linux/soundwire/sdw_registers.h index a686f7988156..5d3c271af7d1 100644 --- a/include/linux/soundwire/sdw_registers.h +++ b/include/linux/soundwire/sdw_registers.h @@ -12,7 +12,7 @@ #define SDW_REG_SHIFT(n) (ffs(n) - 1) /* - * SDW registers as defined by MIPI 1.1 Spec + * SDW registers as defined by MIPI 1.2 Spec */ #define SDW_REGADDR GENMASK(14, 0) #define SDW_SCP_ADDRPAGE2_MASK GENMASK(22, 15) @@ -43,6 +43,8 @@ #define SDW_DP0_INT_TEST_FAIL BIT(0) #define SDW_DP0_INT_PORT_READY BIT(1) #define SDW_DP0_INT_BRA_FAILURE BIT(2) +#define SDW_DP0_SDCA_CASCADE BIT(3) +/* BIT(4) not allocated in SoundWire specification 1.2 */ #define SDW_DP0_INT_IMPDEF1 BIT(5) #define SDW_DP0_INT_IMPDEF2 BIT(6) #define SDW_DP0_INT_IMPDEF3 BIT(7) @@ -106,6 +108,20 @@ #define SDW_SCP_ADDRPAGE2 0x49 #define SDW_SCP_KEEPEREN 0x4A #define SDW_SCP_BANKDELAY 0x4B +#define SDW_SCP_COMMIT 0x4C + +#define SDW_SCP_BUS_CLOCK_BASE 0x4D +#define SDW_SCP_BASE_CLOCK_FREQ GENMASK(2, 0) +#define SDW_SCP_BASE_CLOCK_UNKNOWN 0x0 +#define SDW_SCP_BASE_CLOCK_19200000_HZ 0x1 +#define SDW_SCP_BASE_CLOCK_24000000_HZ 0x2 +#define SDW_SCP_BASE_CLOCK_24576000_HZ 0x3 +#define SDW_SCP_BASE_CLOCK_22579200_HZ 0x4 +#define SDW_SCP_BASE_CLOCK_32000000_HZ 0x5 +#define SDW_SCP_BASE_CLOCK_RESERVED 0x6 +#define SDW_SCP_BASE_CLOCK_IMP_DEF 0x7 + +/* 0x4E is not allocated in SoundWire specification 1.2 */ #define SDW_SCP_TESTMODE 0x4F #define SDW_SCP_DEVID_0 0x50 #define SDW_SCP_DEVID_1 0x51 @@ -114,12 +130,111 @@ #define SDW_SCP_DEVID_4 0x54 #define SDW_SCP_DEVID_5 0x55 +/* Both INT and STATUS register are same */ +#define SDW_SCP_SDCA_INT1 0x58 +#define SDW_SCP_SDCA_INT_SDCA_0 BIT(0) +#define SDW_SCP_SDCA_INT_SDCA_1 BIT(1) +#define SDW_SCP_SDCA_INT_SDCA_2 BIT(2) +#define SDW_SCP_SDCA_INT_SDCA_3 BIT(3) +#define SDW_SCP_SDCA_INT_SDCA_4 BIT(4) +#define SDW_SCP_SDCA_INT_SDCA_5 BIT(5) +#define SDW_SCP_SDCA_INT_SDCA_6 BIT(6) +#define SDW_SCP_SDCA_INT_SDCA_7 BIT(7) + +#define SDW_SCP_SDCA_INT2 0x59 +#define SDW_SCP_SDCA_INT_SDCA_8 BIT(0) +#define SDW_SCP_SDCA_INT_SDCA_9 BIT(1) +#define SDW_SCP_SDCA_INT_SDCA_10 BIT(2) +#define SDW_SCP_SDCA_INT_SDCA_11 BIT(3) +#define SDW_SCP_SDCA_INT_SDCA_12 BIT(4) +#define SDW_SCP_SDCA_INT_SDCA_13 BIT(5) +#define SDW_SCP_SDCA_INT_SDCA_14 BIT(6) +#define SDW_SCP_SDCA_INT_SDCA_15 BIT(7) + +#define SDW_SCP_SDCA_INT3 0x5A +#define SDW_SCP_SDCA_INT_SDCA_16 BIT(0) +#define SDW_SCP_SDCA_INT_SDCA_17 BIT(1) +#define SDW_SCP_SDCA_INT_SDCA_18 BIT(2) +#define SDW_SCP_SDCA_INT_SDCA_19 BIT(3) +#define SDW_SCP_SDCA_INT_SDCA_20 BIT(4) +#define SDW_SCP_SDCA_INT_SDCA_21 BIT(5) +#define SDW_SCP_SDCA_INT_SDCA_22 BIT(6) +#define SDW_SCP_SDCA_INT_SDCA_23 BIT(7) + +#define SDW_SCP_SDCA_INT4 0x5B +#define SDW_SCP_SDCA_INT_SDCA_24 BIT(0) +#define SDW_SCP_SDCA_INT_SDCA_25 BIT(1) +#define SDW_SCP_SDCA_INT_SDCA_26 BIT(2) +#define SDW_SCP_SDCA_INT_SDCA_27 BIT(3) +#define SDW_SCP_SDCA_INT_SDCA_28 BIT(4) +#define SDW_SCP_SDCA_INT_SDCA_29 BIT(5) +#define SDW_SCP_SDCA_INT_SDCA_30 BIT(6) +/* BIT(7) not allocated in SoundWire 1.2 specification */ + +#define SDW_SCP_SDCA_INTMASK1 0x5C +#define SDW_SCP_SDCA_INTMASK_SDCA_0 BIT(0) +#define SDW_SCP_SDCA_INTMASK_SDCA_1 BIT(1) +#define SDW_SCP_SDCA_INTMASK_SDCA_2 BIT(2) +#define SDW_SCP_SDCA_INTMASK_SDCA_3 BIT(3) +#define SDW_SCP_SDCA_INTMASK_SDCA_4 BIT(4) +#define SDW_SCP_SDCA_INTMASK_SDCA_5 BIT(5) +#define SDW_SCP_SDCA_INTMASK_SDCA_6 BIT(6) +#define SDW_SCP_SDCA_INTMASK_SDCA_7 BIT(7) + +#define SDW_SCP_SDCA_INTMASK2 0x5D +#define SDW_SCP_SDCA_INTMASK_SDCA_8 BIT(0) +#define SDW_SCP_SDCA_INTMASK_SDCA_9 BIT(1) +#define SDW_SCP_SDCA_INTMASK_SDCA_10 BIT(2) +#define SDW_SCP_SDCA_INTMASK_SDCA_11 BIT(3) +#define SDW_SCP_SDCA_INTMASK_SDCA_12 BIT(4) +#define SDW_SCP_SDCA_INTMASK_SDCA_13 BIT(5) +#define SDW_SCP_SDCA_INTMASK_SDCA_14 BIT(6) +#define SDW_SCP_SDCA_INTMASK_SDCA_15 BIT(7) + +#define SDW_SCP_SDCA_INTMASK3 0x5E +#define SDW_SCP_SDCA_INTMASK_SDCA_16 BIT(0) +#define SDW_SCP_SDCA_INTMASK_SDCA_17 BIT(1) +#define SDW_SCP_SDCA_INTMASK_SDCA_18 BIT(2) +#define SDW_SCP_SDCA_INTMASK_SDCA_19 BIT(3) +#define SDW_SCP_SDCA_INTMASK_SDCA_20 BIT(4) +#define SDW_SCP_SDCA_INTMASK_SDCA_21 BIT(5) +#define SDW_SCP_SDCA_INTMASK_SDCA_22 BIT(6) +#define SDW_SCP_SDCA_INTMASK_SDCA_23 BIT(7) + +#define SDW_SCP_SDCA_INTMASK4 0x5F +#define SDW_SCP_SDCA_INTMASK_SDCA_24 BIT(0) +#define SDW_SCP_SDCA_INTMASK_SDCA_25 BIT(1) +#define SDW_SCP_SDCA_INTMASK_SDCA_26 BIT(2) +#define SDW_SCP_SDCA_INTMASK_SDCA_27 BIT(3) +#define SDW_SCP_SDCA_INTMASK_SDCA_28 BIT(4) +#define SDW_SCP_SDCA_INTMASK_SDCA_29 BIT(5) +#define SDW_SCP_SDCA_INTMASK_SDCA_30 BIT(6) +/* BIT(7) not allocated in SoundWire 1.2 specification */ + /* Banked Registers */ #define SDW_SCP_FRAMECTRL_B0 0x60 #define SDW_SCP_FRAMECTRL_B1 (0x60 + SDW_BANK1_OFFSET) #define SDW_SCP_NEXTFRAME_B0 0x61 #define SDW_SCP_NEXTFRAME_B1 (0x61 + SDW_BANK1_OFFSET) +#define SDW_SCP_BUSCLOCK_SCALE_B0 0x62 +#define SDW_SCP_BUSCLOCK_SCALE_B1 (0x62 + SDW_BANK1_OFFSET) +#define SDW_SCP_CLOCK_SCALE GENMASK(3, 0) + +/* PHY registers - CTRL and STAT are the same address */ +#define SDW_SCP_PHY_OUT_CTRL_0 0x80 +#define SDW_SCP_PHY_OUT_CTRL_1 0x81 +#define SDW_SCP_PHY_OUT_CTRL_2 0x82 +#define SDW_SCP_PHY_OUT_CTRL_3 0x83 +#define SDW_SCP_PHY_OUT_CTRL_4 0x84 +#define SDW_SCP_PHY_OUT_CTRL_5 0x85 +#define SDW_SCP_PHY_OUT_CTRL_6 0x86 +#define SDW_SCP_PHY_OUT_CTRL_7 0x87 + +#define SDW_SCP_CAP_LOAD_CTRL GENMASK(2, 0) +#define SDW_SCP_DRIVE_STRENGTH_CTRL GENMASK(5, 3) +#define SDW_SCP_SLEW_TIME_CTRL GENMASK(7, 6) + /* Both INT and STATUS register is same */ #define SDW_DPN_INT(n) (0x0 + SDW_DPN_SIZE * (n)) #define SDW_DPN_INTMASK(n) (0x1 + SDW_DPN_SIZE * (n)) |