diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/dt-bindings/clock/qcom,sdx75-gcc.h | 193 | ||||
-rw-r--r-- | include/dt-bindings/clock/qcom,sm8450-gpucc.h | 48 | ||||
-rw-r--r-- | include/dt-bindings/clock/qcom,sm8450-videocc.h | 38 | ||||
-rw-r--r-- | include/dt-bindings/clock/qcom,sm8550-gpucc.h | 48 | ||||
-rw-r--r-- | include/dt-bindings/power/qcom-rpmpd.h | 38 | ||||
-rw-r--r-- | include/dt-bindings/reset/qcom,sm8450-gpucc.h | 20 |
6 files changed, 371 insertions, 14 deletions
diff --git a/include/dt-bindings/clock/qcom,sdx75-gcc.h b/include/dt-bindings/clock/qcom,sdx75-gcc.h new file mode 100644 index 000000000000..a470e8c4fd41 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sdx75-gcc.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H + +/* GCC clocks */ +#define GPLL0 0 +#define GPLL0_OUT_EVEN 1 +#define GPLL4 2 +#define GPLL5 3 +#define GPLL6 4 +#define GPLL8 5 +#define GCC_AHB_PCIE_LINK_CLK 6 +#define GCC_BOOT_ROM_AHB_CLK 7 +#define GCC_EEE_EMAC0_CLK 8 +#define GCC_EEE_EMAC0_CLK_SRC 9 +#define GCC_EEE_EMAC1_CLK 10 +#define GCC_EEE_EMAC1_CLK_SRC 11 +#define GCC_EMAC0_AXI_CLK 12 +#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK 13 +#define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC 14 +#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK 15 +#define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC 16 +#define GCC_EMAC0_PHY_AUX_CLK 17 +#define GCC_EMAC0_PHY_AUX_CLK_SRC 18 +#define GCC_EMAC0_PTP_CLK 19 +#define GCC_EMAC0_PTP_CLK_SRC 20 +#define GCC_EMAC0_RGMII_CLK 21 +#define GCC_EMAC0_RGMII_CLK_SRC 22 +#define GCC_EMAC0_RPCS_RX_CLK 23 +#define GCC_EMAC0_RPCS_TX_CLK 24 +#define GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC 25 +#define GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC 26 +#define GCC_EMAC0_SLV_AHB_CLK 27 +#define GCC_EMAC0_XGXS_RX_CLK 28 +#define GCC_EMAC0_XGXS_TX_CLK 29 +#define GCC_EMAC1_AXI_CLK 30 +#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK 31 +#define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC 32 +#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK 33 +#define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC 34 +#define GCC_EMAC1_PHY_AUX_CLK 35 +#define GCC_EMAC1_PHY_AUX_CLK_SRC 36 +#define GCC_EMAC1_PTP_CLK 37 +#define GCC_EMAC1_PTP_CLK_SRC 38 +#define GCC_EMAC1_RGMII_CLK 39 +#define GCC_EMAC1_RGMII_CLK_SRC 40 +#define GCC_EMAC1_RPCS_RX_CLK 41 +#define GCC_EMAC1_RPCS_TX_CLK 42 +#define GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC 43 +#define GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC 44 +#define GCC_EMAC1_SLV_AHB_CLK 45 +#define GCC_EMAC1_XGXS_RX_CLK 46 +#define GCC_EMAC1_XGXS_TX_CLK 47 +#define GCC_EMAC_0_CLKREF_EN 48 +#define GCC_EMAC_1_CLKREF_EN 49 +#define GCC_GP1_CLK 50 +#define GCC_GP1_CLK_SRC 51 +#define GCC_GP2_CLK 52 +#define GCC_GP2_CLK_SRC 53 +#define GCC_GP3_CLK 54 +#define GCC_GP3_CLK_SRC 55 +#define GCC_PCIE_0_CLKREF_EN 56 +#define GCC_PCIE_1_AUX_CLK 57 +#define GCC_PCIE_1_AUX_PHY_CLK_SRC 58 +#define GCC_PCIE_1_CFG_AHB_CLK 59 +#define GCC_PCIE_1_CLKREF_EN 60 +#define GCC_PCIE_1_MSTR_AXI_CLK 61 +#define GCC_PCIE_1_PHY_RCHNG_CLK 62 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 63 +#define GCC_PCIE_1_PIPE_CLK 64 +#define GCC_PCIE_1_PIPE_CLK_SRC 65 +#define GCC_PCIE_1_PIPE_DIV2_CLK 66 +#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC 67 +#define GCC_PCIE_1_SLV_AXI_CLK 68 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 69 +#define GCC_PCIE_2_AUX_CLK 70 +#define GCC_PCIE_2_AUX_PHY_CLK_SRC 71 +#define GCC_PCIE_2_CFG_AHB_CLK 72 +#define GCC_PCIE_2_CLKREF_EN 73 +#define GCC_PCIE_2_MSTR_AXI_CLK 74 +#define GCC_PCIE_2_PHY_RCHNG_CLK 75 +#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 76 +#define GCC_PCIE_2_PIPE_CLK 77 +#define GCC_PCIE_2_PIPE_CLK_SRC 78 +#define GCC_PCIE_2_PIPE_DIV2_CLK 79 +#define GCC_PCIE_2_PIPE_DIV2_CLK_SRC 80 +#define GCC_PCIE_2_SLV_AXI_CLK 81 +#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 82 +#define GCC_PCIE_AUX_CLK 83 +#define GCC_PCIE_AUX_CLK_SRC 84 +#define GCC_PCIE_AUX_PHY_CLK_SRC 85 +#define GCC_PCIE_CFG_AHB_CLK 86 +#define GCC_PCIE_MSTR_AXI_CLK 87 +#define GCC_PCIE_PIPE_CLK 88 +#define GCC_PCIE_PIPE_CLK_SRC 89 +#define GCC_PCIE_RCHNG_PHY_CLK 90 +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 91 +#define GCC_PCIE_SLEEP_CLK 92 +#define GCC_PCIE_SLV_AXI_CLK 93 +#define GCC_PCIE_SLV_Q2A_AXI_CLK 94 +#define GCC_PDM2_CLK 95 +#define GCC_PDM2_CLK_SRC 96 +#define GCC_PDM_AHB_CLK 97 +#define GCC_PDM_XO4_CLK 98 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 99 +#define GCC_QUPV3_WRAP0_CORE_CLK 100 +#define GCC_QUPV3_WRAP0_S0_CLK 101 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 102 +#define GCC_QUPV3_WRAP0_S1_CLK 103 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 104 +#define GCC_QUPV3_WRAP0_S2_CLK 105 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 106 +#define GCC_QUPV3_WRAP0_S3_CLK 107 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 108 +#define GCC_QUPV3_WRAP0_S4_CLK 109 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 110 +#define GCC_QUPV3_WRAP0_S5_CLK 111 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 112 +#define GCC_QUPV3_WRAP0_S6_CLK 113 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 114 +#define GCC_QUPV3_WRAP0_S7_CLK 115 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 116 +#define GCC_QUPV3_WRAP0_S8_CLK 117 +#define GCC_QUPV3_WRAP0_S8_CLK_SRC 118 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 119 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 120 +#define GCC_SDCC1_AHB_CLK 121 +#define GCC_SDCC1_APPS_CLK 122 +#define GCC_SDCC1_APPS_CLK_SRC 123 +#define GCC_SDCC2_AHB_CLK 124 +#define GCC_SDCC2_APPS_CLK 125 +#define GCC_SDCC2_APPS_CLK_SRC 126 +#define GCC_USB2_CLKREF_EN 127 +#define GCC_USB30_MASTER_CLK 128 +#define GCC_USB30_MASTER_CLK_SRC 129 +#define GCC_USB30_MOCK_UTMI_CLK 130 +#define GCC_USB30_MOCK_UTMI_CLK_SRC 131 +#define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC 132 +#define GCC_USB30_MSTR_AXI_CLK 133 +#define GCC_USB30_SLEEP_CLK 134 +#define GCC_USB30_SLV_AHB_CLK 135 +#define GCC_USB3_PHY_AUX_CLK 136 +#define GCC_USB3_PHY_AUX_CLK_SRC 137 +#define GCC_USB3_PHY_PIPE_CLK 138 +#define GCC_USB3_PHY_PIPE_CLK_SRC 139 +#define GCC_USB3_PRIM_CLKREF_EN 140 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 141 +#define GCC_XO_PCIE_LINK_CLK 142 + +/* GCC power domains */ +#define GCC_EMAC0_GDSC 0 +#define GCC_EMAC1_GDSC 1 +#define GCC_PCIE_1_GDSC 2 +#define GCC_PCIE_1_PHY_GDSC 3 +#define GCC_PCIE_2_GDSC 4 +#define GCC_PCIE_2_PHY_GDSC 5 +#define GCC_PCIE_GDSC 6 +#define GCC_PCIE_PHY_GDSC 7 +#define GCC_USB30_GDSC 8 +#define GCC_USB3_PHY_GDSC 9 + +/* GCC resets */ +#define GCC_EMAC0_BCR 0 +#define GCC_EMAC1_BCR 1 +#define GCC_EMMC_BCR 2 +#define GCC_PCIE_1_BCR 3 +#define GCC_PCIE_1_LINK_DOWN_BCR 4 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_1_PHY_BCR 6 +#define GCC_PCIE_2_BCR 7 +#define GCC_PCIE_2_LINK_DOWN_BCR 8 +#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 9 +#define GCC_PCIE_2_PHY_BCR 10 +#define GCC_PCIE_BCR 11 +#define GCC_PCIE_LINK_DOWN_BCR 12 +#define GCC_PCIE_NOCSR_COM_PHY_BCR 13 +#define GCC_PCIE_PHY_BCR 14 +#define GCC_PCIE_PHY_CFG_AHB_BCR 15 +#define GCC_PCIE_PHY_COM_BCR 16 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 17 +#define GCC_QUSB2PHY_BCR 18 +#define GCC_TCSR_PCIE_BCR 19 +#define GCC_USB30_BCR 20 +#define GCC_USB3_PHY_BCR 21 +#define GCC_USB3PHY_PHY_BCR 22 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 +#define GCC_EMAC0_RGMII_CLK_ARES 24 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm8450-gpucc.h b/include/dt-bindings/clock/qcom,sm8450-gpucc.h new file mode 100644 index 000000000000..712b171503d6 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8450-gpucc.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8450_H + +/* Clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_APB_CLK 2 +#define GPU_CC_CX_FF_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_SNOC_DVM_CLK 5 +#define GPU_CC_CXO_AON_CLK 6 +#define GPU_CC_CXO_CLK 7 +#define GPU_CC_DEMET_CLK 8 +#define GPU_CC_DEMET_DIV_CLK_SRC 9 +#define GPU_CC_FF_CLK_SRC 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_FF_CLK 13 +#define GPU_CC_GX_GFX3D_CLK 14 +#define GPU_CC_GX_GFX3D_RDVM_CLK 15 +#define GPU_CC_GX_GMU_CLK 16 +#define GPU_CC_GX_VSENSE_CLK 17 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 18 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 19 +#define GPU_CC_HUB_AON_CLK 20 +#define GPU_CC_HUB_CLK_SRC 21 +#define GPU_CC_HUB_CX_INT_CLK 22 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 23 +#define GPU_CC_MEMNOC_GFX_CLK 24 +#define GPU_CC_MND1X_0_GFX3D_CLK 25 +#define GPU_CC_MND1X_1_GFX3D_CLK 26 +#define GPU_CC_PLL0 27 +#define GPU_CC_PLL1 28 +#define GPU_CC_SLEEP_CLK 29 +#define GPU_CC_XO_CLK_SRC 30 +#define GPU_CC_XO_DIV_CLK_SRC 31 + +/* GDSCs */ +#define GPU_GX_GDSC 0 +#define GPU_CX_GDSC 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm8450-videocc.h b/include/dt-bindings/clock/qcom,sm8450-videocc.h new file mode 100644 index 000000000000..9d795adfe4eb --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8450-videocc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_MVS0_CLK 0 +#define VIDEO_CC_MVS0_CLK_SRC 1 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 2 +#define VIDEO_CC_MVS0C_CLK 3 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 4 +#define VIDEO_CC_MVS1_CLK 5 +#define VIDEO_CC_MVS1_CLK_SRC 6 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 7 +#define VIDEO_CC_MVS1C_CLK 8 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9 +#define VIDEO_CC_PLL0 10 +#define VIDEO_CC_PLL1 11 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0C_GDSC 0 +#define VIDEO_CC_MVS0_GDSC 1 +#define VIDEO_CC_MVS1C_GDSC 2 +#define VIDEO_CC_MVS1_GDSC 3 + +/* VIDEO_CC resets */ +#define CVP_VIDEO_CC_INTERFACE_BCR 0 +#define CVP_VIDEO_CC_MVS0_BCR 1 +#define CVP_VIDEO_CC_MVS0C_BCR 2 +#define CVP_VIDEO_CC_MVS1_BCR 3 +#define CVP_VIDEO_CC_MVS1C_BCR 4 +#define VIDEO_CC_MVS0C_CLK_ARES 5 +#define VIDEO_CC_MVS1C_CLK_ARES 6 + +#endif diff --git a/include/dt-bindings/clock/qcom,sm8550-gpucc.h b/include/dt-bindings/clock/qcom,sm8550-gpucc.h new file mode 100644 index 000000000000..a6760547a3ab --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8550-gpucc.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CRC_AHB_CLK 1 +#define GPU_CC_CX_FF_CLK 2 +#define GPU_CC_CX_GMU_CLK 3 +#define GPU_CC_CXO_AON_CLK 4 +#define GPU_CC_CXO_CLK 5 +#define GPU_CC_DEMET_CLK 6 +#define GPU_CC_DEMET_DIV_CLK_SRC 7 +#define GPU_CC_FF_CLK_SRC 8 +#define GPU_CC_FREQ_MEASURE_CLK 9 +#define GPU_CC_GMU_CLK_SRC 10 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 11 +#define GPU_CC_HUB_AON_CLK 12 +#define GPU_CC_HUB_CLK_SRC 13 +#define GPU_CC_HUB_CX_INT_CLK 14 +#define GPU_CC_MEMNOC_GFX_CLK 15 +#define GPU_CC_MND1X_0_GFX3D_CLK 16 +#define GPU_CC_MND1X_1_GFX3D_CLK 17 +#define GPU_CC_PLL0 18 +#define GPU_CC_PLL1 19 +#define GPU_CC_SLEEP_CLK 20 +#define GPU_CC_XO_CLK_SRC 21 +#define GPU_CC_XO_DIV_CLK_SRC 22 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CX_BCR 1 +#define GPUCC_GPU_CC_FAST_HUB_BCR 2 +#define GPUCC_GPU_CC_FF_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +#endif diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 1bf8e87ecd7e..4ede277d20e1 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -207,20 +207,30 @@ #define SC8280XP_XO 15 /* SDM845 Power Domain performance levels */ -#define RPMH_REGULATOR_LEVEL_RETENTION 16 -#define RPMH_REGULATOR_LEVEL_MIN_SVS 48 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 -#define RPMH_REGULATOR_LEVEL_LOW_SVS 64 -#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 -#define RPMH_REGULATOR_LEVEL_SVS 128 -#define RPMH_REGULATOR_LEVEL_SVS_L0 144 -#define RPMH_REGULATOR_LEVEL_SVS_L1 192 -#define RPMH_REGULATOR_LEVEL_SVS_L2 224 -#define RPMH_REGULATOR_LEVEL_NOM 256 -#define RPMH_REGULATOR_LEVEL_NOM_L1 320 -#define RPMH_REGULATOR_LEVEL_NOM_L2 336 -#define RPMH_REGULATOR_LEVEL_TURBO 384 -#define RPMH_REGULATOR_LEVEL_TURBO_L1 416 +#define RPMH_REGULATOR_LEVEL_RETENTION 16 +#define RPMH_REGULATOR_LEVEL_MIN_SVS 48 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D2 52 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D0 60 +#define RPMH_REGULATOR_LEVEL_LOW_SVS 64 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_P1 72 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L1 80 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_L2 96 +#define RPMH_REGULATOR_LEVEL_SVS 128 +#define RPMH_REGULATOR_LEVEL_SVS_L0 144 +#define RPMH_REGULATOR_LEVEL_SVS_L1 192 +#define RPMH_REGULATOR_LEVEL_SVS_L2 224 +#define RPMH_REGULATOR_LEVEL_NOM 256 +#define RPMH_REGULATOR_LEVEL_NOM_L0 288 +#define RPMH_REGULATOR_LEVEL_NOM_L1 320 +#define RPMH_REGULATOR_LEVEL_NOM_L2 336 +#define RPMH_REGULATOR_LEVEL_TURBO 384 +#define RPMH_REGULATOR_LEVEL_TURBO_L0 400 +#define RPMH_REGULATOR_LEVEL_TURBO_L1 416 +#define RPMH_REGULATOR_LEVEL_TURBO_L2 432 +#define RPMH_REGULATOR_LEVEL_TURBO_L3 448 +#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464 +#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR 480 /* MDM9607 Power Domains */ #define MDM9607_VDDCX 0 diff --git a/include/dt-bindings/reset/qcom,sm8450-gpucc.h b/include/dt-bindings/reset/qcom,sm8450-gpucc.h new file mode 100644 index 000000000000..58ba8f987107 --- /dev/null +++ b/include/dt-bindings/reset/qcom,sm8450-gpucc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H +#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H + +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CX_BCR 1 +#define GPUCC_GPU_CC_FAST_HUB_BCR 2 +#define GPUCC_GPU_CC_FF_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 +#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 8 + +#endif |