diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/alderlake/pipeline.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/alderlake/pipeline.json | 507 |
1 files changed, 471 insertions, 36 deletions
diff --git a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json index de2c6e0ef654..d02e078a90c9 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json @@ -23,7 +23,31 @@ "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and Interrupt call and return.", + "BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x7e", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfe", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", @@ -35,6 +59,54 @@ "Unit": "cpu_atom" }, { + "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.INDIRECT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xeb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.INDIRECT_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.IND_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.COND", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x7e", + "Unit": "cpu_atom" + }, + { "BriefDescription": "Counts the number of near CALL branch instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5", @@ -47,6 +119,66 @@ "Unit": "cpu_atom" }, { + "BriefDescription": "Counts the number of near RET branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xf7", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xeb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of near relative CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.REL_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfd", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_RETURN", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.RETURN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xf7", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.COND_TAKEN", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfe", + "Unit": "cpu_atom" + }, + { "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5", @@ -58,12 +190,121 @@ "Unit": "cpu_atom" }, { + "BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x7e", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfe", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xeb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.IND_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.COND", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x7e", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xeb", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.RETURN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xf7", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.COND_TAKEN", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfe", + "Unit": "cpu_atom" + }, + { "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", "CollectPEBSRecord": "2", - "Counter": "33", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "PEBScounters": "33", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_atom" }, @@ -75,25 +316,28 @@ "EventName": "CPU_CLK_UNHALTED.CORE_P", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "2000003", + "Speculative": "1", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)", "CollectPEBSRecord": "2", - "Counter": "34", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PEBScounters": "34", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x3", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", "CollectPEBSRecord": "2", - "Counter": "33", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PEBScounters": "33", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_atom" }, @@ -105,12 +349,13 @@ "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "2000003", + "Speculative": "1", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of instructions retired. (Fixed event)", + "BriefDescription": "Counts the total number of instructions retired. (Fixed event)", "CollectPEBSRecord": "2", - "Counter": "32", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PEBScounters": "32", @@ -119,6 +364,17 @@ "Unit": "cpu_atom" }, { + "BriefDescription": "Counts the total number of instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003", + "Unit": "cpu_atom" + }, + { "BriefDescription": "This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5", @@ -162,6 +418,7 @@ "EventName": "MACHINE_CLEARS.DISAMBIGUATION", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "20003", + "Speculative": "1", "UMask": "0x8", "Unit": "cpu_atom" }, @@ -173,6 +430,7 @@ "EventName": "MACHINE_CLEARS.MRN_NUKE", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x80", "Unit": "cpu_atom" }, @@ -182,9 +440,9 @@ "Counter": "0,1,2,3,4,5", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.PAGE_FAULT", - "PEBS": "1", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "20003", + "Speculative": "1", "UMask": "0x20", "Unit": "cpu_atom" }, @@ -196,6 +454,7 @@ "EventName": "MACHINE_CLEARS.SLOW", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "20003", + "Speculative": "1", "UMask": "0x6f", "Unit": "cpu_atom" }, @@ -207,17 +466,19 @@ "EventName": "MACHINE_CLEARS.SMC", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "20003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots not consumed due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing uops from the UROM until a specified older uop retires.", + "BriefDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5", "EventCode": "0x75", "EventName": "SERIALIZATION.NON_C01_MS_SCB", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "200003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_atom" }, @@ -229,6 +490,7 @@ "EventName": "TOPDOWN_BAD_SPECULATION.ALL", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "Unit": "cpu_atom" }, { @@ -239,6 +501,7 @@ "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_atom" }, @@ -250,6 +513,7 @@ "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x3", "Unit": "cpu_atom" }, @@ -261,6 +525,7 @@ "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x4", "Unit": "cpu_atom" }, @@ -272,6 +537,7 @@ "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_atom" }, @@ -283,6 +549,7 @@ "EventName": "TOPDOWN_BE_BOUND.ALL", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "Unit": "cpu_atom" }, { @@ -293,6 +560,7 @@ "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_atom" }, @@ -304,6 +572,7 @@ "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_atom" }, @@ -315,6 +584,7 @@ "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x8", "Unit": "cpu_atom" }, @@ -326,6 +596,7 @@ "EventName": "TOPDOWN_BE_BOUND.REGISTER", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x20", "Unit": "cpu_atom" }, @@ -337,6 +608,7 @@ "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x40", "Unit": "cpu_atom" }, @@ -348,6 +620,7 @@ "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x10", "Unit": "cpu_atom" }, @@ -359,6 +632,7 @@ "EventName": "TOPDOWN_FE_BOUND.ALL", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "Unit": "cpu_atom" }, { @@ -369,6 +643,7 @@ "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_atom" }, @@ -380,6 +655,7 @@ "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x40", "Unit": "cpu_atom" }, @@ -391,6 +667,7 @@ "EventName": "TOPDOWN_FE_BOUND.CISC", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_atom" }, @@ -402,6 +679,7 @@ "EventName": "TOPDOWN_FE_BOUND.DECODE", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x8", "Unit": "cpu_atom" }, @@ -413,17 +691,19 @@ "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x8d", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x72", "Unit": "cpu_atom" }, @@ -435,6 +715,7 @@ "EventName": "TOPDOWN_FE_BOUND.ITLB", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x10", "Unit": "cpu_atom" }, @@ -446,6 +727,7 @@ "EventName": "TOPDOWN_FE_BOUND.OTHER", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x80", "Unit": "cpu_atom" }, @@ -457,6 +739,7 @@ "EventName": "TOPDOWN_FE_BOUND.PREDECODE", "PEBScounters": "0,1,2,3,4,5", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x4", "Unit": "cpu_atom" }, @@ -527,6 +810,7 @@ "EventName": "ARITH.DIVIDER_ACTIVE", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x9", "Unit": "cpu_core" }, @@ -539,6 +823,7 @@ "EventName": "ARITH.DIV_ACTIVE", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x9", "Unit": "cpu_core" }, @@ -551,11 +836,24 @@ "EventName": "ARITH.FP_DIVIDER_ACTIVE", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "This event counts the cycles the integer divider is busy.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb0", + "EventName": "ARITH.IDIV_ACTIVE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", @@ -563,10 +861,23 @@ "EventName": "ARITH.INT_DIVIDER_ACTIVE", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x8", "Unit": "cpu_core" }, { + "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc1", + "EventName": "ASSISTS.ANY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1f", + "Unit": "cpu_core" + }, + { "BriefDescription": "All branch instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", @@ -709,7 +1020,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS", + "BriefDescription": "number of branch instructions retired that were mispredicted and taken.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", @@ -757,6 +1068,42 @@ "Unit": "cpu_core" }, { + "BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.C01", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.C02", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Core clocks when the thread is in the C0.1 or C0.2 or running a PAUSE in C0 ACPI state.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.C0_WAIT", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x70", + "Unit": "cpu_core" + }, + { "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", @@ -764,6 +1111,7 @@ "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_core" }, @@ -775,22 +1123,24 @@ "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "25003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "CPU_CLK_UNHALTED.PAUSE", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.PAUSE", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x40", "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST", "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", @@ -798,6 +1148,7 @@ "EventName": "CPU_CLK_UNHALTED.PAUSE_INST", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x40", "Unit": "cpu_core" }, @@ -808,26 +1159,41 @@ "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x8", "Unit": "cpu_core" }, { "BriefDescription": "Reference cycles when the core is not in halt state.", "CollectPEBSRecord": "2", - "Counter": "34", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PEBScounters": "34", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x3", "Unit": "cpu_core" }, { + "BriefDescription": "Reference cycles when the core is not in halt state.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { "BriefDescription": "Core cycles when the thread is not in halt state", "CollectPEBSRecord": "2", - "Counter": "33", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PEBScounters": "33", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_core" }, @@ -839,6 +1205,7 @@ "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "Unit": "cpu_core" }, { @@ -850,6 +1217,7 @@ "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x8", "Unit": "cpu_core" }, @@ -862,6 +1230,7 @@ "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -874,6 +1243,7 @@ "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x10", "Unit": "cpu_core" }, @@ -886,6 +1256,7 @@ "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0xc", "Unit": "cpu_core" }, @@ -898,6 +1269,7 @@ "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x5", "Unit": "cpu_core" }, @@ -910,6 +1282,7 @@ "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x4", "Unit": "cpu_core" }, @@ -921,6 +1294,7 @@ "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_core" }, @@ -932,6 +1306,7 @@ "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x4", "Unit": "cpu_core" }, @@ -943,6 +1318,7 @@ "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x8", "Unit": "cpu_core" }, @@ -954,6 +1330,7 @@ "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x10", "Unit": "cpu_core" }, @@ -966,6 +1343,7 @@ "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x21", "Unit": "cpu_core" }, @@ -978,10 +1356,23 @@ "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x40", "Unit": "cpu_core" }, { + "BriefDescription": "Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x80", + "Unit": "cpu_core" + }, + { "BriefDescription": "Instruction decoders utilized in a cycle", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", @@ -989,13 +1380,14 @@ "EventName": "INST_DECODED.DECODERS", "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, { "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", "CollectPEBSRecord": "2", - "Counter": "32", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PEBScounters": "32", @@ -1015,7 +1407,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "INST_RETIRED.MACRO_FUSED", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", @@ -1026,7 +1418,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "Number of all retired NOP instructions.", + "BriefDescription": "Retired NOP instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", @@ -1039,7 +1431,7 @@ { "BriefDescription": "Precise instruction retired with PEBS precise-distribution", "CollectPEBSRecord": "2", - "Counter": "32", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "1", "PEBScounters": "32", @@ -1048,7 +1440,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "INST_RETIRED.REP_ITERATION", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", @@ -1066,6 +1458,7 @@ "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "500009", + "Speculative": "1", "UMask": "0x80", "Unit": "cpu_core" }, @@ -1077,11 +1470,12 @@ "EventName": "INT_MISC.RECOVERY_CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "500009", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "INT_MISC.UNKNOWN_BRANCH_CYCLES", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", @@ -1090,6 +1484,7 @@ "MSRValue": "0x7", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", + "Speculative": "1", "TakenAlone": "1", "UMask": "0x40", "Unit": "cpu_core" @@ -1102,11 +1497,12 @@ "EventName": "INT_MISC.UOP_DROPPING", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x10", "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "INT_VEC_RETIRED.128BIT", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", @@ -1117,7 +1513,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "INT_VEC_RETIRED.256BIT", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", @@ -1150,7 +1546,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "INT_VEC_RETIRED.MUL_256", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", @@ -1161,7 +1557,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "INT_VEC_RETIRED.SHUFFLES", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", @@ -1172,7 +1568,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "INT_VEC_RETIRED.VNNI_128", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", @@ -1183,7 +1579,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "INT_VEC_RETIRED.VNNI_256", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", @@ -1201,6 +1597,7 @@ "EventName": "LD_BLOCKS.ADDRESS_ALIAS", "PEBScounters": "0,1,2,3", "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x4", "Unit": "cpu_core" }, @@ -1212,6 +1609,7 @@ "EventName": "LD_BLOCKS.NO_SR", "PEBScounters": "0,1,2,3", "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x88", "Unit": "cpu_core" }, @@ -1223,6 +1621,7 @@ "EventName": "LD_BLOCKS.STORE_FORWARD", "PEBScounters": "0,1,2,3", "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x82", "Unit": "cpu_core" }, @@ -1234,6 +1633,7 @@ "EventName": "LOAD_HIT_PREFETCH.SWPF", "PEBScounters": "0,1,2,3", "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -1244,8 +1644,9 @@ "CounterMask": "1", "EventCode": "0xa8", "EventName": "LSD.CYCLES_ACTIVE", - "PEBScounters": "0,1,2,3", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -1256,8 +1657,9 @@ "CounterMask": "6", "EventCode": "0xa8", "EventName": "LSD.CYCLES_OK", - "PEBScounters": "0,1,2,3", + "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -1269,6 +1671,7 @@ "EventName": "LSD.UOPS", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -1282,6 +1685,7 @@ "EventName": "MACHINE_CLEARS.COUNT", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -1293,17 +1697,19 @@ "EventName": "MACHINE_CLEARS.SMC", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x4", "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "MISC2_RETIRED.LFENCE", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe0", "EventName": "MISC2_RETIRED.LFENCE", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "400009", + "Speculative": "1", "UMask": "0x20", "Unit": "cpu_core" }, @@ -1326,6 +1732,7 @@ "EventName": "RESOURCE_STALLS.SB", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x8", "Unit": "cpu_core" }, @@ -1337,6 +1744,7 @@ "EventName": "RESOURCE_STALLS.SCOREBOARD", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_core" }, @@ -1348,6 +1756,7 @@ "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "10000003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_core" }, @@ -1357,6 +1766,7 @@ "EventCode": "0xa4", "EventName": "TOPDOWN.BAD_SPEC_SLOTS", "SampleAfterValue": "10000003", + "Speculative": "1", "UMask": "0x4", "Unit": "cpu_core" }, @@ -1366,27 +1776,30 @@ "EventCode": "0xa4", "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", "SampleAfterValue": "10000003", + "Speculative": "1", "UMask": "0x8", "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "10000003", + "Speculative": "1", "UMask": "0x10", "Unit": "cpu_core" }, { "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", "CollectPEBSRecord": "2", - "Counter": "35", + "Counter": "Fixed counter 3", "EventName": "TOPDOWN.SLOTS", "PEBScounters": "35", "SampleAfterValue": "10000003", + "Speculative": "1", "UMask": "0x4", "Unit": "cpu_core" }, @@ -1398,17 +1811,19 @@ "EventName": "TOPDOWN.SLOTS_P", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "10000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "UOPS_DECODED.DEC0_UOPS", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UOPS_DECODED.DEC0_UOPS", "PEBScounters": "0,1,2,3", "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -1420,6 +1835,7 @@ "EventName": "UOPS_DISPATCHED.PORT_0", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -1431,6 +1847,7 @@ "EventName": "UOPS_DISPATCHED.PORT_1", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_core" }, @@ -1442,6 +1859,7 @@ "EventName": "UOPS_DISPATCHED.PORT_2_3_10", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x4", "Unit": "cpu_core" }, @@ -1453,6 +1871,7 @@ "EventName": "UOPS_DISPATCHED.PORT_4_9", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x10", "Unit": "cpu_core" }, @@ -1464,6 +1883,7 @@ "EventName": "UOPS_DISPATCHED.PORT_5_11", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x20", "Unit": "cpu_core" }, @@ -1475,6 +1895,7 @@ "EventName": "UOPS_DISPATCHED.PORT_6", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x40", "Unit": "cpu_core" }, @@ -1486,6 +1907,7 @@ "EventName": "UOPS_DISPATCHED.PORT_7_8", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x80", "Unit": "cpu_core" }, @@ -1498,6 +1920,7 @@ "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_core" }, @@ -1510,6 +1933,7 @@ "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_core" }, @@ -1522,6 +1946,7 @@ "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_core" }, @@ -1534,6 +1959,7 @@ "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x2", "Unit": "cpu_core" }, @@ -1546,6 +1972,7 @@ "EventName": "UOPS_EXECUTED.CYCLES_GE_1", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -1558,6 +1985,7 @@ "EventName": "UOPS_EXECUTED.CYCLES_GE_2", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -1570,6 +1998,7 @@ "EventName": "UOPS_EXECUTED.CYCLES_GE_3", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -1582,6 +2011,7 @@ "EventName": "UOPS_EXECUTED.CYCLES_GE_4", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -1595,6 +2025,7 @@ "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -1608,6 +2039,7 @@ "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -1619,6 +2051,7 @@ "EventName": "UOPS_EXECUTED.THREAD", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -1630,6 +2063,7 @@ "EventName": "UOPS_EXECUTED.X87", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x10", "Unit": "cpu_core" }, @@ -1641,6 +2075,7 @@ "EventName": "UOPS_ISSUED.ANY", "PEBScounters": "0,1,2,3,4,5,6,7", "SampleAfterValue": "2000003", + "Speculative": "1", "UMask": "0x1", "Unit": "cpu_core" }, @@ -1657,7 +2092,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "Retired uops except the last uop of each instruction.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", @@ -1668,7 +2103,7 @@ "Unit": "cpu_core" }, { - "BriefDescription": "TBD", + "BriefDescription": "UOPS_RETIRED.MS", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", @@ -1718,4 +2153,4 @@ "UMask": "0x2", "Unit": "cpu_core" } -]
\ No newline at end of file +] |