diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json index e8512c585572..82e07c73cff0 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json @@ -1,7 +1,6 @@ [ { "BriefDescription": "Memory accesses that missed the DTLB.", - "Counter": "0,1", "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.DTLB_MISS", "SampleAfterValue": "200000", @@ -9,7 +8,6 @@ }, { "BriefDescription": "DTLB misses due to load operations.", - "Counter": "0,1", "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD", "SampleAfterValue": "200000", @@ -17,7 +15,6 @@ }, { "BriefDescription": "DTLB misses due to store operations.", - "Counter": "0,1", "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST", "SampleAfterValue": "200000", @@ -25,7 +22,6 @@ }, { "BriefDescription": "L0 DTLB misses due to load operations.", - "Counter": "0,1", "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD", "SampleAfterValue": "200000", @@ -33,7 +29,6 @@ }, { "BriefDescription": "L0 DTLB misses due to store operations", - "Counter": "0,1", "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST", "SampleAfterValue": "200000", @@ -41,7 +36,6 @@ }, { "BriefDescription": "ITLB flushes.", - "Counter": "0,1", "EventCode": "0x82", "EventName": "ITLB.FLUSH", "SampleAfterValue": "200000", @@ -49,7 +43,6 @@ }, { "BriefDescription": "ITLB hits.", - "Counter": "0,1", "EventCode": "0x82", "EventName": "ITLB.HIT", "SampleAfterValue": "200000", @@ -57,7 +50,6 @@ }, { "BriefDescription": "ITLB misses.", - "Counter": "0,1", "EventCode": "0x82", "EventName": "ITLB.MISSES", "PEBS": "2", @@ -66,7 +58,6 @@ }, { "BriefDescription": "Retired loads that miss the DTLB (precise event).", - "Counter": "0,1", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", "PEBS": "1", @@ -75,7 +66,6 @@ }, { "BriefDescription": "Duration of page-walks in core cycles", - "Counter": "0,1", "EventCode": "0xC", "EventName": "PAGE_WALKS.CYCLES", "SampleAfterValue": "2000000", @@ -83,7 +73,6 @@ }, { "BriefDescription": "Duration of D-side only page walks", - "Counter": "0,1", "EventCode": "0xC", "EventName": "PAGE_WALKS.D_SIDE_CYCLES", "SampleAfterValue": "2000000", @@ -91,7 +80,6 @@ }, { "BriefDescription": "Number of D-side only page walks", - "Counter": "0,1", "EventCode": "0xC", "EventName": "PAGE_WALKS.D_SIDE_WALKS", "SampleAfterValue": "200000", @@ -99,7 +87,6 @@ }, { "BriefDescription": "Duration of I-Side page walks", - "Counter": "0,1", "EventCode": "0xC", "EventName": "PAGE_WALKS.I_SIDE_CYCLES", "SampleAfterValue": "2000000", @@ -107,7 +94,6 @@ }, { "BriefDescription": "Number of I-Side page walks", - "Counter": "0,1", "EventCode": "0xC", "EventName": "PAGE_WALKS.I_SIDE_WALKS", "SampleAfterValue": "200000", @@ -115,7 +101,6 @@ }, { "BriefDescription": "Number of page-walks executed.", - "Counter": "0,1", "EventCode": "0xC", "EventName": "PAGE_WALKS.WALKS", "SampleAfterValue": "200000", |