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-rw-r--r--tools/perf/pmu-events/arch/x86/broadwellx/memory.json143
1 files changed, 0 insertions, 143 deletions
diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/memory.json b/tools/perf/pmu-events/arch/x86/broadwellx/memory.json
index 545f61f691b9..a7449e5b68dc 100644
--- a/tools/perf/pmu-events/arch/x86/broadwellx/memory.json
+++ b/tools/perf/pmu-events/arch/x86/broadwellx/memory.json
@@ -1,8 +1,6 @@
[
{
"BriefDescription": "Number of times HLE abort was triggered",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED",
"PEBS": "1",
@@ -12,8 +10,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@@ -22,8 +18,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC2",
"PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
@@ -32,8 +26,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC3",
"PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
@@ -42,8 +34,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC4",
"PublicDescription": "Number of times HLE caused a fault.",
@@ -52,8 +42,6 @@
},
{
"BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
@@ -62,8 +50,6 @@
},
{
"BriefDescription": "Number of times HLE commit succeeded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.COMMIT",
"PublicDescription": "Number of times HLE commit succeeded.",
@@ -72,8 +58,6 @@
},
{
"BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xc8",
"EventName": "HLE_RETIRED.START",
"PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
@@ -82,8 +66,6 @@
},
{
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
@@ -92,8 +74,6 @@
},
{
"BriefDescription": "Randomly selected loads with latency value being above 128",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -103,13 +83,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 128.",
"SampleAfterValue": "1009",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 16",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -119,13 +96,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 16.",
"SampleAfterValue": "20011",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 256",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -135,13 +109,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 256.",
"SampleAfterValue": "503",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 32",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -151,13 +122,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 32.",
"SampleAfterValue": "100007",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 4",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -167,13 +135,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above four.",
"SampleAfterValue": "100003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 512",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -183,13 +148,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 512.",
"SampleAfterValue": "101",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 64",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -199,13 +161,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above 64.",
"SampleAfterValue": "2003",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Randomly selected loads with latency value being above 8",
- "Counter": "3",
- "CounterHTOff": "3",
"Data_LA": "1",
"Errata": "BDM100, BDM35",
"EventCode": "0xcd",
@@ -215,13 +174,10 @@
"PEBS": "2",
"PublicDescription": "Counts randomly selected loads with latency value being above eight.",
"SampleAfterValue": "50021",
- "TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
@@ -230,8 +186,6 @@
},
{
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
@@ -240,236 +194,177 @@
},
{
"BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000244",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63BC00091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87FC00091",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x6040007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x63BC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x87FC007F7",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all requests miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC08FFF",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x604000122",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00002",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00200",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00100",
- "Offcore": "1",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "Number of times RTM abort was triggered",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
@@ -479,8 +374,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
@@ -489,8 +382,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC2",
"PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
@@ -499,8 +390,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC3",
"PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
@@ -509,8 +398,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC4",
"PublicDescription": "Number of times a RTM caused a fault.",
@@ -519,8 +406,6 @@
},
{
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
@@ -529,8 +414,6 @@
},
{
"BriefDescription": "Number of times RTM commit succeeded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT",
"PublicDescription": "Number of times RTM commit succeeded.",
@@ -539,8 +422,6 @@
},
{
"BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.START",
"PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
@@ -549,8 +430,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC1",
"SampleAfterValue": "2000003",
@@ -558,8 +437,6 @@
},
{
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
@@ -568,8 +445,6 @@
},
{
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
@@ -578,8 +453,6 @@
},
{
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC4",
"PublicDescription": "RTM region detected inside HLE.",
@@ -588,8 +461,6 @@
},
{
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5d",
"EventName": "TX_EXEC.MISC5",
"SampleAfterValue": "2000003",
@@ -597,8 +468,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
"PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
@@ -607,8 +476,6 @@
},
{
"BriefDescription": "Number of times a TSX line had a cache conflict",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_CONFLICT",
"PublicDescription": "Number of times a TSX line had a cache conflict.",
@@ -617,8 +484,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
@@ -627,8 +492,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
@@ -637,8 +500,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
@@ -647,8 +508,6 @@
},
{
"BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
@@ -657,8 +516,6 @@
},
{
"BriefDescription": "Number of times we could not allocate Lock Buffer",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x54",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"PublicDescription": "Number of times we could not allocate Lock Buffer.",
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-09 07:58:55 +0300