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2022-07-07phy: qcom-qmp: move QSERDES V5 registers to separate headersDmitry Baryshkov3-130/+152
Move QSERDES V5 registers to the separate headers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-12-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-07phy: qcom-qmp: move QSERDES V4 registers to separate headersDmitry Baryshkov3-151/+173
Move QSERDES V4 registers to the separate headers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-11-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-07phy: qcom-qmp: move QSERDES V3 registers to separate headersDmitry Baryshkov3-133/+156
Move QSERDES V3 registers to the separate headers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-10-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-07phy: qcom-qmp: move QSERDES registers to separate headerDmitry Baryshkov3-109/+130
Move QSERDES V2 registers to the separate header. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-9-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-07phy: qcom-qmp: use QPHY_V4_PCS for ipq6018/ipq8074 PCIe gen3Dmitry Baryshkov2-74/+41
PCS_COM_* symbols duplicate the QPHY_V4_PCS_*. PCS_PCIE_* symbols duplicate the QPHY_V4_PCS_PCIE_*. Use generic register names for the IPQ6018 and IPQ8074 tables and drop the custom PCS_COM_*/PCS_PCIE* names. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-8-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-07phy: qcom-qmp: rename QMP V2 PCS registersDmitry Baryshkov6-69/+69
Rename QMP V2 PCS registers to follow the usual pattern of QPHY_V2_PCS_*. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-7-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-07phy: qcom-qmp: drop special QMP V2 PCIE gen3 definesDmitry Baryshkov2-107/+67
Replace separate defines for QMP V2 PHY for PCIe gen3 ports. They are equivalent to the QSERDES_V4_ symbols. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-6-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-07phy: qcom-qmp-pcie: split pcs_misc region for ipq6018 pcie gen3Dmitry Baryshkov2-16/+25
Follow the example of other PCIe PHYs and use separate pcs_misc region to access PCS_PCIE_* resources. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-5-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-07phy: qcom-qmp-combo,usb: add support for separate PCS_USB regionDmitry Baryshkov3-108/+163
Different QMP USB PHYs might have different offset from PCS to PCS_USB register space, but the same PCS_USB register layout. Add separate PCS_USB region space and merge related PCS_USB definitions. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-07phy: qcom-qmp-ufs: remove spurious register write in the msm8996 tableDmitry Baryshkov1-1/+0
The msm8996_ufs_serdes_tbl table contains write to QPHY_POWER_DOWN_CONTROL, however this register doesn't belong to the QSERDES register space. Also the PHY power down is already handled in the qcom_qmp_phy_ufs_com_init(). Drop this entry completely. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-07phy: qcom-qmp: fix the QSERDES_V5_COM_CMN_MODE registerDmitry Baryshkov1-1/+2
Change QSERDES_V5_COM_CMN_MODE to be defined to 0x1a0 rather than 0x1a4. The only user of this register name (sm8450_qmp_gen4x2_pcie_serdes_tbl) should use the 0x1a0 register, as stated in the downstream dtsi tree. Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220705094320.1313312-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-07drm/msm/dp: delete vdda regulator related functions from eDP/DP controllerKuogee Hsieh3-115/+2
Vdda regulators are related to both eDP and DP phy so that it should be managed at eDP and DP phy driver instead of controller. This patch removes vdda regulators related functions out of eDP/DP controller. Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/1657038556-2231-4-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-07phy: qcom-qmp: add regulator_set_load to dp phyKuogee Hsieh1-9/+32
This patch add regulator_set_load() before enable regulator at DP phy driver. Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/1657038556-2231-3-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-06phy: qcom-edp: add regulator_set_load to edp phyKuogee Hsieh1-0/+12
This patch add regulator_set_load() before enable regulator at eDP phy driver. Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1657038556-2231-2-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: amlogic: Add G12A Analog MIPI D-PHY driverNeil Armstrong3-0/+184
The Amlogic G12A SoCs embeds an Analog MIPI D-PHY used to communicate with DSI panels. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220705075650.3165348-3-narmstrong@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05dt-bindings: phy: add Amlogic G12A Analog MIPI D-PHY bindingsNeil Armstrong1-0/+35
The Amlogic G12A SoCs embeds an Analog MIPI D-PHY to communicate with DSI panels, this adds the bindings. This Analog D-PHY works with a separate Digital MIPI D-PHY. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220705075650.3165348-2-narmstrong@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: phy-brcm-usb: drop unexpected word "the" in the commentsJiang Jian1-1/+1
there is an unexpected word "the" in the comments that need to be dropped file: ./drivers/phy/broadcom/phy-brcm-usb-init.c line: 864 * Make sure the the second and third memory controller changed to * Make sure the second and third memory controller Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20220621122401.115500-1-jiangjian@cdjrlc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: rockchip-inno-usb2: Sync initial otg statePeter Geis1-0/+6
The initial otg state for the phy defaults to device mode. The actual state isn't detected until an ID IRQ fires. Fix this by syncing the ID state during initialization. Fixes: 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") Signed-off-by: Peter Geis <pgwipeout@gmail.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220622003140.30365-1-pgwipeout@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: qcom-qmp-pcie: add IPQ8074 PCIe Gen3 QMP PHY supportRobert Marko1-0/+160
IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3. Gen2 one is already supported, so add the support for the Gen3 one. It uses the same register layout as IPQ6018. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220621195512.1760362-3-robimarko@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05dt-bindings: phy: qcom,qmp: add IPQ8074 PCIe Gen3 PHY bindingRobert Marko1-0/+2
IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3. Gen2 one is already supported, document the bindings for the Gen3 one. Signed-off-by: Robert Marko <robimarko@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220621195512.1760362-2-robimarko@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: qcom-qmp-pcie: make pipe clock rate configurableRobert Marko1-2/+12
IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz like every other PCIe QMP PHY does, so make it configurable as part of the qmp_phy_cfg. Signed-off-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220621195512.1760362-1-robimarko@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: qcom-qmp: clean up hex definesJohan Hovold1-8/+8
Use lower case hex consistently for define values. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220609120338.4080-4-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: qcom-qmp: clean up define alignmentJohan Hovold1-24/+24
Clean up the QMP defines by removing some stray white space and making sure values are aligned. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20220609120338.4080-3-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: qcom-qmp: clean up v4 and v5 define orderJohan Hovold1-3/+3
Clean up the QMP v4 and v5 defines by moving a few entries that were out of order. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220609120338.4080-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: qcom-qmp-usb: clean up pipe clock handlingJohan Hovold1-13/+2
Clean up the pipe clock handling by using dev_err_probe() to handle probe deferral and dropping the obsolete comment that claimed that the pipe clock was optional for some other PHY types. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220623113314.29761-4-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: qcom-qmp-pcie-msm8996: drop obsolete pipe clock type checkJohan Hovold1-17/+2
Drop the obsolete pipe clock handling which was used to treat the pipe clock as optional for types other than PCIe and USB and which is no longer needed since splitting the PHY driver. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220623113314.29761-3-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: qcom-qmp-pcie: drop obsolete pipe clock type checkJohan Hovold1-17/+2
Drop the obsolete pipe clock handling which was used to treat the pipe clock as optional for types other than PCIe and USB and which is no longer needed since splitting the PHY driver. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220623113314.29761-2-johan+linaro@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: phy-mtk-dp: Add driver for DP phyMarkus Schneider-Pargmann4-0/+212
This is a new driver that supports the integrated DisplayPort phy for mediatek SoCs, especially the mt8195. The phy is integrated into the DisplayPort controller and will be created by the mtk-dp driver. This driver expects a struct regmap to be able to work on the same registers as the DisplayPort controller. It sets the device data to be the struct phy so that the DisplayPort controller can easily work with it. The driver does not have any devicetree bindings because the datasheet does not list the controller and the phy as distinct units. The interaction with the controller can be covered by the configure callback of the phy framework and its displayport parameters. Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> [Bo-Chen: Modify reviewers' comments.] Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220624062725.4095-1-rex-bc.chen@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: cdns-dphy: Add support for DPHY TX on J721eRahul T R1-0/+61
Add support new compatible for dphy-tx on j721e and implement dphy ops required. Signed-off-by: Rahul T R <r-ravikumar@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220623125433.18467-4-r-ravikumar@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: cdns-dphy: Add band config for dphy txRahul T R1-1/+39
Add support for band ctrl config for dphy tx. Signed-off-by: Rahul T R <r-ravikumar@ti.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220623125433.18467-3-r-ravikumar@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: dt-bindings: cdns,dphy: Add compatible for dphy on j721eRahul T R1-2/+3
Add compatible to support dphy tx on j721e Signed-off-by: Rahul T R <r-ravikumar@ti.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220623125433.18467-2-r-ravikumar@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: rockchip-inno-usb2: Prevent incorrect error on probePeter Geis1-1/+1
If a phy supply is designated but isn't available at probe time, an EPROBE_DEFER is returned. Use dev_err_probe to prevent this from incorrectly printing during boot. Signed-off-by: Peter Geis <pgwipeout@gmail.com> Link: https://lore.kernel.org/r/20220625212711.558495-1-pgwipeout@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: dphy: drop unexpected word "the" in the commentsJiang Jian1-1/+1
there is an unexpected word "the" in the comments that need to be dropped file: ./drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c line: 139 * when in RxULPS check state, after the the logic enable the analog, changed to * when in RxULPS check state, after the logic enable the analog, Signed-off-by: Jiang Jian <jiangjian@cdjrlc.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220621120015.113682-1-jiangjian@cdjrlc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: tegra: Add PCIe PIPE2UPHY support for Tegra234Vidya Sagar1-1/+47
Synopsys DesignWare core based PCIe controllers in Tegra234 SoC interface with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module. For each PCIe lane of a controller, there is a P2U unit instantiated at hardware level. This driver provides support for the programming required for each P2U that is going to be used for a PCIe controller. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Link: https://lore.kernel.org/r/20220629060435.25297-9-vidyas@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05dt-bindings: PHY: P2U: Add support for Tegra234 P2U blockVidya Sagar1-4/+13
Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue module instantiated once for each PCIe lane between Synopsys DesignWare core based PCIe IP and Universal PHY block. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220629060435.25297-2-vidyas@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: mediatek: Add PCIe PHY driverJianjun Wang3-0/+279
Add PCIe GEN3 PHY driver support on MediaTek chipsets. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: AngeloGioachino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220617070246.20142-3-jianjun.wang@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05dt-bindings: phy: mediatek: Add YAML schema for PCIe PHYJianjun Wang1-0/+75
Add YAML schema documentation for PCIe PHY on MediaTek chipsets. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220617070246.20142-2-jianjun.wang@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-05phy: ti: tusb1210: Don't check for write errors when powering onAndy Shevchenko1-2/+3
On some platforms, like Intel Merrifield, the writing values during power on may timeout: tusb1210 dwc3.0.auto.ulpi: error -110 writing val 0x41 to reg 0x80 phy phy-dwc3.0.auto.ulpi.0: phy poweron failed --> -110 dwc3 dwc3.0.auto: error -ETIMEDOUT: failed to initialize core dwc3: probe of dwc3.0.auto failed with error -110 which effectively fails the probe of the USB controller. Drop the check as it was before the culprit commit (see Fixes tag). Fixes: 09a3512681b3 ("phy: ti: tusb1210: Improve ulpi_read()/_write() error checking") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Ferry Toth <fntoth@gmail.com> Link: https://lore.kernel.org/r/20220613160848.82746-1-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-17MAINTAINERS: add include/dt-bindings/phy to GENERIC PHY FRAMEWORKLukas Bulwahn1-0/+1
Maintainers of the directory Documentation/devicetree/bindings/phy are also the maintainers of the corresponding directory include/dt-bindings/phy. Add the file entry for include/dt-bindings/phy to the appropriate section in MAINTAINERS. Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20220613122621.18397-1-lukas.bulwahn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-17phy: qcom-qmp: fix PCIe PHY supportDmitry Baryshkov1-2/+2
Replace init/exit ops with power_on/power_off which should be used for the PCIe PHYs to fix PHY initialization. Fixes: da07a06b905f ("phy: qcom-qmp-pcie: drop support for non-PCIe PHY types") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220610185542.3662484-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-17phy: qcom-qmp: fix msm8996 PCIe PHY supportDmitry Baryshkov1-2/+2
Replace init/exit ops with power_on/power_off which should be used for the PCIe PHYs to fix PHY initialization. Fixes: f575ac2d64e7 ("phy: qcom-qmp-pcie-msm8996: drop support for non-PCIe PHY types") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220610185542.3662484-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-17phy: ti: phy-j721e-wiz: use OF data for device specific dataRoger Quadros1-25/+50
Move device specific data into OF data structure so it is easier to maintain and we can get rid of if statements. Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Matt Ranostay <mranostay@ti.com> Link: https://lore.kernel.org/r/20220526064121.27625-1-rogerq@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-17dt-bindings: phy: renesas: usb3-phy: Spelling s/funcional/functional/Geert Uytterhoeven1-1/+1
Fix a misspelling of the word "functional". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/3da9bd360e1c83007af0e0e90fa4e6c2b50fdab3.1652100633.git.geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-17phy: samsung-ufs: add support for FSD ufs phy driverAlim Akhtar4-0/+63
Adds support for Tesla Full Self-Driving (FSD) ufs phy driver. This SoC has different cdr lock status offset. Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220610104119.66401-4-alim.akhtar@samsung.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-17phy: samsung-ufs: move cdr offset to drvdataAlim Akhtar4-2/+9
Move CDR lock offset to drv data so that it can be extended for other SoCs which are having CDR lock at different register offset. Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220610104119.66401-3-alim.akhtar@samsung.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-17dt-bindings: phy: Add FSD UFS PHY bindingsAlim Akhtar1-0/+1
Add tesla,fsd-ufs-phy compatible for Tesla Full Self-Driving (FSD) SoC. Signed-off-by: Bharat Uppal <bharat.uppal@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220610104119.66401-2-alim.akhtar@samsung.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-17dt-bindings: phy: List supplies for qcom,edp-phyDouglas Anderson1-0/+6
We're supposed to list the supplies in the dt bindings but there are none in the eDP PHY bindings. Looking at the driver in Linux, I can see that there seem to be two relevant supplies: "vdda-phy" and "vdda-pll". Let's add those to the bindings. NOTE: from looking at the Qualcomm datasheet for sc7280, it's not immediately clear how to figure out how to fill in these supplies. The only two eDP related supplies are simply described as "power for eDP 0.9V circuits" and "power for eDP 1.2V circuits". From guessing and from comparing how a similar PHY is hooked up on other similar Qualcomm boards, I'll make the educated guess that the 1.2V supply goes to "vdda-phy" and the 0.9V supply goes to "vdda-pll" and I'll use that in the example here. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com> Link: https://lore.kernel.org/r/20220425140619.2.Iae013f0ff4599294189f3a6e91376fad137bbabf@changeid Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-09phy: qcom-qmp-usb: use bulk reset_control APIDmitry Baryshkov1-31/+18
Switch qcom-qmp-usb driver to use reset_control_bulk_assert / _deassert functions rather than hardcoding the loops in the driver itself. Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220607213203.2819885-31-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-09phy: qcom-qmp-pcie-msm8996: use bulk reset_control APIDmitry Baryshkov1-31/+18
Switch qcom-qmp-pcie-msm8996 driver to use reset_control_bulk_assert / _deassert functions rather than hardcoding the loops in the driver itself. Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220607213203.2819885-30-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-06-09phy: qcom-qmp-pcie: use bulk reset_control APIDmitry Baryshkov1-31/+18
Switch qcom-qmp-pcie driver to use reset_control_bulk_assert / _deassert functions rather than hardcoding the loops in the driver itself. Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20220607213203.2819885-29-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
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