kernel/linux.git - Linux kernel stable tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2015-06-21	MIPS: ingenic: Initial JZ4780 support	Paul Burton	8	-6/+134
2015-06-21	MIPS: JZ4740: use Ingenic SoC UART driver	Paul Burton	11	-120/+28
2015-06-21	serial: 8250_ingenic: support for Ingenic SoC UARTs	Paul Burton	3	-0/+278
2015-06-21	devicetree: document Ingenic SoC UART binding	Paul Burton	1	-0/+22
2015-06-21	MIPS: JZ4740: only detect RAM size if not specified in DT	Paul Burton	3	-1/+10
2015-06-21	MIPS: JZ4740: remove clock.h	Paul Burton	3	-27/+3
2015-06-21	clk: ingenic: add JZ4780 CGU support	Paul Burton	2	-0/+734
2015-06-21	MIPS, clk: move jz4740 clock suspend, resume functions to jz4740-cgu	Paul Burton	5	-99/+38
2015-06-21	MIPS, clk: move jz4740 UDC auto suspend functions to jz4740-cgu	Paul Burton	2	-13/+22
2015-06-21	MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu	Paul Burton	2	-16/+22
2015-06-21	MIPS,clk: migrate JZ4740 to common clock framework	Paul Burton	11	-968/+255
2015-06-21	clk: ingenic: add driver for Ingenic SoC CGU clocks	Paul Burton	4	-0/+936
2015-06-21	DEVICETREE: Add Ingenic CGU binding documentation	Paul Burton	3	-0/+178
2015-06-21	MIPS: JZ4740: replace use of jz4740_clock_bdata	Paul Burton	3	-4/+29
2015-06-21	MIPS: JZ4740: Call jz4740_clock_init earlier	Paul Burton	3	-2/+5
2015-06-21	MIPS/IRQCHIP: Move Ingenic SoC intc driver to drivers/irqchip	Paul Burton	6	-8/+12
2015-06-21	MIPS: JZ4740: support newer SoC interrupt controllers	Paul Burton	1	-0/+9
2015-06-21	MIPS: JZ4740: Avoid JZ4740-specific naming	Paul Burton	3	-16/+16
2015-06-21	MIPS: JZ4740: read intc base address from DT	Paul Burton	1	-3/+6
2015-06-21	MIPS: JZ4740: define IRQ numbers based on number of intc IRQs	Paul Burton	1	-3/+7
2015-06-21	MIPS: JZ4740: support >32 interrupts	Paul Burton	1	-25/+46
2015-06-21	MIPS: JZ4740: Remove jz_intc_base global	Paul Burton	1	-8/+31
2015-06-21	MIPS: JZ4740: drop intc debugfs code	Paul Burton	1	-42/+0
2015-06-21	MIPS: JZ4740: register an irq_domain for the interrupt controller	Paul Burton	1	-0/+6
2015-06-21	MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT	Paul Burton	1	-1/+6
2015-06-21	MIPS: JZ4740: probe interrupt controller via DT	Paul Burton	4	-5/+18
2015-06-21	devicetree: document Ingenic SoC interrupt controller binding	Paul Burton	1	-0/+28
2015-06-21	MIPS: JZ4740: Move arch_init_irq out of arch/mips/jz4740/irq.c	Paul Burton	3	-4/+11
2015-06-21	MIPS: JZ4740: use generic plat_irq_dispatch	Paul Burton	1	-12/+0
2015-06-21	MIPS: JZ4740: probe CPU interrupt controller via DT	Paul Burton	2	-2/+9
2015-06-21	IRQCHIP: irq_cpu: declare irqchip table entry	Paul Burton	1	-0/+3
2015-06-21	MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip.	Ralf Baechle	13	-56/+57
2015-06-21	MIPS: JZ4740: require & include DT	Paul Burton	6	-0/+43
2015-06-21	MIPS: ingenic: Add newer vendor IDs	Paul Burton	2	-3/+7
2015-06-21	MIPS: JZ4740: introduce CONFIG_MACH_INGENIC	Paul Burton	4	-9/+13
2015-06-21	devicetree/bindings: add Qi Hardware vendor prefix	Paul Burton	1	-0/+1
2015-06-21	devicetree/bindings: add Ingenic Semiconductor vendor prefix	Paul Burton	1	-0/+1
2015-06-21	MIPS: DEC: Update CPU overrides	Maciej W. Rozycki	1	-0/+16
2015-06-21	MIPS: netlogic: remove unnecessary MTD partition probe specification	Brian Norris	1	-3/+0
2015-06-21	MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidation	Maciej W. Rozycki	1	-2/+2
2015-06-21	MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init'	Maciej W. Rozycki	3	-7/+8
2015-06-21	MIPS: tlb-r3k: Also invalidate wired TLB entries on boot	Maciej W. Rozycki	1	-11/+13
2015-06-21	MIPS: dump_tlb: Take XPA into account	James Hogan	1	-5/+13
2015-06-21	MIPS: dump_tlb: Take RI/XI bits into account	James Hogan	1	-7/+20
2015-06-21	MIPS: dump_tlb: Take EHINV bit into account	James Hogan	1	-0/+3
2015-06-21	MIPS: dump_tlb: Take global bit into account	James Hogan	2	-3/+12
2015-06-21	MIPS: dump_tlb: Make use of EntryLo bit definitions	James Hogan	2	-12/+12
2015-06-21	MIPS: dump_tlb: Refactor TLB matching	James Hogan	1	-30/+35
2015-06-21	MIPS: dump_tlb: Use tlbr hazard macros	James Hogan	1	-8/+3
2015-06-21	MIPS: mipsregs.h: Add EntryLo bit definitions	James Hogan	1	-0/+22