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2017-04-19clk: imx7d: fix USDHC NAND clockStefan Agner1-2/+1
2017-04-19clk: spear: fix ADC clock definition on SPEAr600Thomas Petazzoni1-1/+1
2017-04-19clk: mediatek: add clk support for MT6797Kevin-CW Chen7-0/+1134
2017-04-19dt-bindings: arm: mediatek: document clk bindings for MT6797Kevin-CW Chen7-1/+8
2017-04-19Merge branch 'clk-mt6797' into clk-nextStephen Boyd1-0/+281
2017-04-19clk: mediatek: add mt6797 clock IDsMars Cheng1-0/+281
2017-04-19clk: imx7d: add the missing ipg_root_clkDong Aisheng1-1/+2
2017-04-19clk: clk-imx7d: fix ahb clk definitionDong Aisheng1-3/+2
2017-04-19clk: vc5: Add support for IDT VersaClock 5P49V5935Alexey Firago1-2/+13
2017-04-19clk: vc5: Add bindings for IDT VersaClock 5P49V5935Alexey Firago1-3/+13
2017-04-19clk: vc5: Add structure to describe particular chip featuresAlexey Firago1-18/+47
2017-04-19Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel...Stephen Boyd18-40/+832
2017-04-17Merge branch 'clk-fixes' into clk-nextStephen Boyd4-0/+74
2017-04-17Merge tag 'sunxi-clk-fixes-for-4.11-2-bis' of https://git.kernel.org/pub/scm/...Stephen Boyd4-0/+74
2017-04-13clk: sunxi-ng: a33: gate then ungate PLL CPU clk after rate changeChen-Yu Tsai1-0/+11
2017-04-13clk: sunxi-ng: Add clk notifier to gate then ungate PLL clocksChen-Yu Tsai2-0/+61
2017-04-13clk: sunxi-ng: fix build failure in ccu-sun9i-a80 driverTobias Regnery1-0/+1
2017-04-13clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLERTobias Regnery1-0/+1
2017-04-12clk: cs2000: use existing priv_to_dev() to getting struct deviceKuninori Morimoto1-5/+3
2017-04-12Merge tag 'meson-clk-for-4.12' of git://github.com/BayLibre/clk-meson into cl...Michael Turquette7-13/+332
2017-04-12Merge tag 'amlogic-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/khil...Michael Turquette9-56/+867
2017-04-12clk: aggregate return codes of notify chainsPeter De Schrijver1-0/+2
2017-04-12clk: add clk_possible_parents debugfs filePeter De Schrijver1-0/+32
2017-04-12clk: imx: correct uart4_serial clock name in driver for i.MX6ULRobin van der Gracht1-1/+1
2017-04-12clk: zte: Mark pll config tables as constStephen Boyd1-2/+2
2017-04-12clk: zte: add pll_vga clock for zx296718Shawn Guo1-0/+24
2017-04-12clk: zte: pd_bit is not 0 on zx296718Shawn Guo2-2/+16
2017-04-12clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocksShawn Guo1-3/+3
2017-04-12clk: imx: clk-imx6ul: The i.mx6ul has no aips_tz3 clockRobin van der Gracht1-4/+5
2017-04-12Merge tag 'tegra-for-4.12-clk' of git://git.kernel.org/pub/scm/linux/kernel/g...Michael Turquette20-268/+739
2017-04-12cs-2000-cp: keep Reserved bit on each registerKuninori Morimoto1-3/+22
2017-04-12clk: qcom: msm8996: Fix the vfe1 powerdomain nameRajendra Nayak1-1/+1
2017-04-12clk: stm32f4: fix timeout management for pll and ready gateGabriel Fernandez1-14/+29
2017-04-12clk: iproc: Remove redundant checkRay Jui1-1/+1
2017-04-12Merge tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/...Michael Turquette12-255/+276
2017-04-12Merge tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/...Michael Turquette7-78/+306
2017-04-12Merge branch 'clk-fixes' into clk-nextStephen Boyd1-3/+10
2017-04-12clk: stm32f4: fix: exclude values 0 and 1 for PLLQGabriel Fernandez1-3/+10
2017-04-12Merge branch 'for-4.12-ti-clk-cleanups' of https://github.com/t-kristo/linux-...Stephen Boyd28-601/+543
2017-04-12clk: hi6220: add debug APB clockLeo Yan2-1/+5
2017-04-07clk: meson: mpll: use 64bit math in rate_from_paramsMartin Blumenstingl1-1/+1
2017-04-07clk: meson: mpll: fix division by zero in rate_from_paramsMartin Blumenstingl1-11/+15
2017-04-07clk: meson: gxbb: add cts_i958 clockJerome Brunet2-1/+23
2017-04-07clk: meson: gxbb: add cts_mclk_i958Jerome Brunet2-1/+56
2017-04-07clk: meson: gxbb: add cts_amclkJerome Brunet2-1/+71
2017-04-07clk: meson: add audio clock divider supportJerome Brunet3-1/+155
2017-04-07clk: meson: gxbb: protect against holes in the onecell_data arrayJerome Brunet1-0/+4
2017-04-07MAINTAINERS: Add maintainers for the meson clock driverJerome Brunet1-0/+10
2017-04-06clk: sunxi-ng: Display index when clock registration failsPriit Laes1-2/+2
2017-04-05clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factorChen-Yu Tsai1-7/+11