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path: root/Documentation/devicetree/bindings/riscv
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2020-10-27dt-bindings: Explicitly allow additional properties in board/SoC schemasRob Herring1-0/+3
2020-10-27dt-bindings: More whitespace clean-ups in schema filesRob Herring1-2/+2
2020-10-07dt-bindings: Explicitly allow additional properties in common schemasRob Herring1-0/+2
2020-10-01dt-bindings: riscv: sifive-l2-cache: convert bindings to json-schemaSagar Kadam2-51/+98
2020-05-03dt-bindings: Remove cases of 'allOf' containing a '$ref'Rob Herring1-11/+9
2019-10-23dt-bindings: riscv: Fix CPU schema errorsRob Herring1-16/+13
2019-08-09dt-bindings: riscv: fix the schema compatible string for the HiFive Unleashed...Paul Walmsley1-1/+1
2019-08-09dt-bindings: riscv: remove obsolete cpus.txtPaul Walmsley2-162/+12
2019-08-09dt-bindings: Update the riscv,isa string descriptionAtish Patra1-0/+4
2019-07-21dt-bindings: riscv: Limit cpus schema to only check RiscV 'cpu' nodesRob Herring1-82/+61
2019-06-26dt-bindings: riscv: resolve 'make dt_binding_check' warningsPaul Walmsley1-12/+14
2019-06-17dt-bindings: riscv: convert cpu binding to json-schemaPaul Walmsley1-0/+168
2019-06-17dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540Paul Walmsley1-0/+25
2019-05-17RISC-V: Add DT documentation for SiFive L2 Cache ControllerYash Shah1-0/+51
2017-09-26dt-bindings: RISC-V CPU BindingsPalmer Dabbelt1-0/+162