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2022-09-14ARM: dts: qcom: align SDHCI reg-names with DT schemaKrzysztof Kozlowski1-1/+1
DT schema requires SDHCI reg names to be hc/core without "_mem" suffix, just like TXT bindings were expecting before the conversion. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220712144245.17417-5-krzysztof.kozlowski@linaro.org
2022-07-17ARM: dts: qcom: sdx65: reorder USB interruptsJohan Hovold1-4/+6
Three SoCs did not follow the interrupt order specified by the USB controller binding. While keeping the non-SuperSpeed interrupts together seems natural, reorder the interrupts to match the binding. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Johan Hovold <johan+linaro@kernel.org> [bjorn: Split out from arm64 patch] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220715070248.19078-5-johan+linaro@kernel.org
2022-07-03ARM: dts: qcom: Fix sdhci node names - use 'mmc@'Bhupesh Sharma1-1/+1
Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports issues with inconsistent 'sdhci@' convention used for specifying the sdhci nodes. The generic mmc bindings expect 'mmc@' format instead. Fix the same. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> [bjorn: Extracted from combined arm64 patch] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220514215424.1007718-2-bhupesh.sharma@linaro.org
2022-06-28ARM: dts: qcom: sdx65: Add Watchdog supportRohit Agarwal1-0/+6
Enable Watchdog support for Application Processor Subsystem (APSS) block on SDX65 platform. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1654080312-5408-11-git-send-email-quic_rohiagar@quicinc.com
2022-06-28ARM: dts: qcom: sdx65: Add pshold supportRohit Agarwal1-0/+5
Add support for pshold block to drive pshold towards the PMIC, which is used to trigger a configurable event such as reboot or poweroff of the SDX65 platform. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1654080312-5408-12-git-send-email-quic_rohiagar@quicinc.com
2022-06-28ARM: dts: qcom: sdx65: Add Modem remoteproc nodeRohit Agarwal1-0/+33
Add modem support to SDX65 using the PAS remoteproc driver. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1654080312-5408-7-git-send-email-quic_rohiagar@quicinc.com
2022-06-28ARM: dts: qcom: sdx65: Add SCM nodeRohit Agarwal1-0/+6
Add SCM node to enable SCM functionality on SDX65 platform. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1654080312-5408-6-git-send-email-quic_rohiagar@quicinc.com
2022-06-28ARM: dts: qcom: sdx65: Add IMEM and PIL info regionRohit Agarwal1-0/+13
Add a simple-mfd representing IMEM on SDX65 and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteproc. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1654080312-5408-4-git-send-email-quic_rohiagar@quicinc.com
2022-06-28ARM: dts: qcom: sdx65: Add modem SMP2P nodeRohit Agarwal1-0/+31
Add SMP2P nodes for the SDX65 platform to communicate with the modem. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1654080312-5408-3-git-send-email-quic_rohiagar@quicinc.com
2022-06-28ARM: dts: qcom: sdx65: Add CPUFreq supportRohit Agarwal1-0/+29
Add CPUFreq support to SDX65 platform using the cpufreq-dt driver. There is no dedicated hardware block available on this platform to carry on the CPUFreq duties. Hence, it is accomplished using the CPU clock and regulators tied together by the operating points table. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1654080312-5408-2-git-send-email-quic_rohiagar@quicinc.com
2022-06-28ARM: dts: qcom: sdx65: Add QPIC NAND supportKaushal Kumar1-0/+22
Add devicetree node to enable support for QPIC NAND controller on Qualcomm SDX65 platform. Since there is no "aon" clock in SDX65, a dummy clock is provided. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Kaushal Kumar <quic_kaushalk@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1651511286-18690-3-git-send-email-quic_kaushalk@quicinc.com
2022-06-28ARM: dts: qcom: sdx65: Add QPIC BAM supportKaushal Kumar1-0/+12
Add devicetree node to enable support for QPIC BAM DMA controller on Qualcomm SDX65 platform. Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Kaushal Kumar <quic_kaushalk@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1651511286-18690-2-git-send-email-quic_kaushalk@quicinc.com
2022-06-28ARM: dts: qcom: sdx65: Add USB3 and PHY supportRohit Agarwal1-0/+83
Add devicetree nodes for enabling USB3 controller, Qcom QMP PHY and SNPS HS PHY on SDX65. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1651482395-29443-4-git-send-email-quic_rohiagar@quicinc.com
2022-06-28ARM: dts: qcom: sdx65: Add interconnect nodesRohit Agarwal1-0/+25
Add interconnect devicetree nodes in SDX65 platform. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> [bjorn: Sorted nodes] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1651482395-29443-2-git-send-email-quic_rohiagar@quicinc.com
2022-06-28ARM: dts: qcom: sdx65: Add Shared memory manager supportRohit Agarwal1-1/+3
Add smem node to support shared memory manager on SDX65 platform. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1651480665-14978-5-git-send-email-quic_rohiagar@quicinc.com
2022-04-19ARM: dts: qcom: sdx55: remove wrong unit address from RPMH RSC clocksKrzysztof Kozlowski1-1/+1
The clock controller of RPMH RSC does not have 'reg' property, so should not have unit address. Fixes: bae2f5979c6e ("ARM: dts: qcom: Add SDX65 platform and MTP board support") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220411085935.130072-2-krzysztof.kozlowski@linaro.org
2022-04-13ARM: dts: qcom: sdx65: Add support for TCSR MutexRohit Agarwal1-0/+6
Add TCSR Mutex node to support Qualcomm Hardware Mutex block on SDX65 platform. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1649670615-21268-7-git-send-email-quic_rohiagar@quicinc.com
2022-04-13ARM: dts: qcom: sdx65: Enable ARM SMMURohit Agarwal1-0/+40
Add a node for the ARM SMMU found in the SDX65. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1649670615-21268-6-git-send-email-quic_rohiagar@quicinc.com
2022-04-13ARM: dts: qcom: sdx65: Add support for SDHCI controllerRohit Agarwal1-0/+13
Add devicetree support for SDHCI controller found in Qualcomm SDX65 platform. The SDHCI controller is based on the MSM SDHCI v5 IP. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1649670615-21268-4-git-send-email-quic_rohiagar@quicinc.com
2022-04-13ARM: dts: qcom: sdx65: Add reserved memory nodesRohit Agarwal1-0/+45
Add reserved memory nodes to the SDX65 dtsi as defined by the memory map. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1649670615-21268-2-git-send-email-quic_rohiagar@quicinc.com
2022-04-13ARM: dts: qcom: sdx65: Add rpmpd nodeRohit Agarwal1-0/+51
Add rpmpd node and opps for this node to the SDX65 dts. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1647411447-25249-5-git-send-email-quic_rohiagar@quicinc.com
2022-04-13ARM: dts: qcom: sdx65: Add spmi nodeRohit Agarwal1-0/+19
Add SPMI node to SDX65 dtsi. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1647411447-25249-2-git-send-email-quic_rohiagar@quicinc.com
2022-04-13ARM: dts: qcom: sdx65: Add support for APCS blockRohit Agarwal1-0/+9
The APCS block on SDX65 acts as a mailbox controller and also provides clock output for the Cortex A7 CPU. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1645505785-2271-5-git-send-email-quic_rohiagar@quicinc.com
2022-04-13ARM: dts: qcom: sdx65: Add support for A7 PLL clockRohit Agarwal1-0/+8
On SDX65 there is a separate A7 PLL which is used to provide high frequency clock to the Cortex A7 CPU via a MUX. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1645505785-2271-4-git-send-email-quic_rohiagar@quicinc.com
2021-12-15ARM: dts: qcom: sdx65: Add pincontrol nodeVamsi krishna Lanka1-0/+12
This commit adds pincontrol node to SDX65 dts. Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1635552125-16407-4-git-send-email-quic_vamslank@quicinc.com
2021-12-15ARM: dts: qcom: Add SDX65 platform and MTP board supportVamsi krishna Lanka1-0/+210
Add basic devicetree support for SDX65 platform and MTP board from Qualcomm. The SDX65 platform features an ARM Cortex A7 CPU which forms the Application Processor Sub System (APSS) along with standard Qualcomm peripherals like GCC, TLMM, BLSP, QPIC, and BAM etc... Also, there exists the networking parts such as IPA, MHI, PCIE-EP, EMAC, and Modem etc.. This commit adds basic devicetree support that includes GCC, RPMh clock, INTC and Debug UART. Signed-off-by: Vamsi Krishna Lanka <quic_vamslank@quicinc.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1635552125-16407-3-git-send-email-quic_vamslank@quicinc.com
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