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2022-09-09ARM: dts: r9a06g032: Add CAN{0,1} nodesBiju Das1-0/+20
Add CAN{0,1} nodes to R9A06G032 (RZ/N1) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220830164518.1381632-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-29ARM: dts: r9a06g032: Describe switchClément Léger1-0/+51
Add the description of the switch that is present on the RZ/N1 SoC. This description includes ethernet-port descriptions for all the ports that are present on the switch along with their connection to the MII converter ports and to the GMAC for the CPU port. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20220624144001.95518-15-clement.leger@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-29ARM: dts: r9a06g032: Describe GMAC2Clément Léger1-0/+18
The RZ/N1 SoC includes two MACs named GMACx that are compatible with the "snps,dwmac" driver. GMAC1 is connected directly to the MII converter port 1. GMAC2 however can be used as the MAC for the switch CPU management port or can be muxed to be connected directly to the MII converter port 2. This commit adds the description for the GMAC2 which will be used by the switch description. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Link: https://lore.kernel.org/r/20220624144001.95518-14-clement.leger@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-06-29ARM: dts: r9a06g032: Describe MII converterClément Léger1-0/+39
Add the MII converter node which describes the MII converter that is present on the RZ/N1 SoC. Signed-off-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Link: https://lore.kernel.org/r/20220624144001.95518-13-clement.leger@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHYHerve Codina1-0/+12
Describe the PCI USB devices that are behind the PCI bridge, adding necessary links to the USB PHY device. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Link: https://lore.kernel.org/r/20220429134143.628428-8-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06ARM: dts: r9a06g032: Add USB PHY DT supportHerve Codina1-0/+6
Define the r9a06g032 generic part of the USB PHY device node. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Link: https://lore.kernel.org/r/20220429134143.628428-7-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06ARM: dts: r9a06g032: Add internal PCI bridge nodeHerve Codina1-0/+29
Add the device node for the r9a06g032 internal PCI bridge device. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Link: https://lore.kernel.org/r/20220429134143.628428-6-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06ARM: dts: r9a06g032: Describe the RTCMiquel Raynal1-0/+13
Describe the SoC RTC which counts time and provides alarm support. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20220429104602.368055-7-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06ARM: dts: r9a06g032: Fix the NAND controller nodeMiquel Raynal1-0/+1
Add the missing power-domains property which is mandatory. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20220429105229.368728-3-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06ARM: dts: r9a06g032: Fill the UART DMA propertiesMiquel Raynal1-0/+10
UART 0 to 2 do not have DMA support, while UART 3 to 7 do. Fill the "dmas" and "dma-names" properties for each of these nodes. Please mind that these nodes go through the dmamux node which will redirect the requests to the right DMA controller. The first 4 cells of the "dmas" properties will be transferred as-is to the DMA controllers. The last 2 cells are consumed by the dmamux. Which means cell 0 and 4 are almost redundant, one giving the controller request ID and the other the dmamux channel which is a 1:1 translation of the request IDs, shifted by 16 when pointing to the second DMA controller. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20220421095323.101811-11-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06ARM: dts: r9a06g032: Describe the DMA routerMiquel Raynal1-0/+10
There is a dmamux on this SoC which allows picking two different sources for a single DMA request. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20220427095653.91804-10-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06ARM: dts: r9a06g032: Add the two DMA nodesMiquel Raynal1-0/+28
Describe the two DMA controllers available on this SoC. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20220427095653.91804-9-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-28ARM: dts: r9a06g032: Add missing '#power-domain-cells'Herve Codina1-0/+1
Without '#power-domain-cells' property, power-domains cannot be used. This property is noted required in the device-tree binding. Add '#power-domain-cells' as needed. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Link: https://lore.kernel.org/r/20220422120850.769480-6-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-04-19ARM: dts: r9a06g032: Drop "arm,cortex-a7-timer" from timer nodeGeert Uytterhoeven1-2/+1
"make dtbs_check": arch/arm/boot/dts/r9a06g032-rzn1d400-db.dt.yaml: timer: compatible: 'oneOf' conditional failed, one must be fixed: ['arm,cortex-a7-timer', 'arm,armv7-timer'] is too long 'arm,cortex-a7-timer' is not one of ['arm,cortex-a15-timer'] 'arm,cortex-a7-timer' is not one of ['arm,armv7-timer'] 'arm,cortex-a7-timer' is not one of ['arm,armv8-timer'] From schema: Documentation/devicetree/bindings/timer/arm,arch_timer.yaml The Cortex-A7 timer should just declare compatibility with "arm,armv7-timer". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/a8e0cf00a983b4c539cdb1cfad5cc6b10b423c5b.1649680220.git.geert+renesas@glider.be
2022-02-24ARM: dts: r9a06g032: Add the watchdog nodesJean-Jacques Hiblot1-0/+16
This SoC includes 2 watchdog controllers (one per A7 core). Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Link: https://lore.kernel.org/r/20220221095032.95054-4-jjhiblot@traphandler.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-01-24ARM: dts: r9a06g032: Describe the NAND controllerMiquel Raynal1-0/+11
Describe the NAND controller embedded in r9a06g032 SoCs. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20211217142033.353599-5-miquel.raynal@bootlin.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-11ARM: dts: renesas: Fix pin controller node namesGeert Uytterhoeven1-1/+1
According to Devicetree Specification v0.2 and later, Section "Generic Names Recommendation", the node name for a pin controller device node should be "pinctrl". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200821112351.5518-1-geert+renesas@glider.be
2020-06-15ARM: dts: r9a06g032: Correct GIC compatible value orderGeert Uytterhoeven1-1/+1
According to commit 61efb56e30f1c54e ("dt-bindings: arm: gic: Allow combining arm,gic-400 compatible strings"), "arm,gic-400" should be listed first. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20200519095431.5650-1-geert+renesas@glider.be
2018-11-28ARM: dts: r9a06g032: Correct the GIC DT node namePhil Edworthy1-1/+1
Harmless mistake, but it's incorrect. The DT spec provides recommendations for the node names: "The name of a node should be somewhat generic, reflecting the function of the device and not its precise programming model. If appropriate, the name should be one of the following choices: ... interrupt-controller" Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-28ARM: dts: r9a06g032: Add pinctrl nodePhil Edworthy1-0/+8
This provides a pinctrl driver for the Renesas R9A06G032 SoC Based on a patch originally written by Michel Pollet at Renesas. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-14ARM: dts: r9a06g032: Correct UART and add all other UARTsPhil Edworthy1-3/+80
- UART0 was missing the bus clock ("apb_pclk"). - Use recently accepted r9a06g032 and rzn1 compat strings. - Add all the other UARTs. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> [simon: updated changelog] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-06ARM: dts: r9a06g032: Use r9a06g032-sysctrl binding definitionsGeert Uytterhoeven1-3/+4
Replace the hardcoded clock indices by R9A06G032_CLK_* symbols. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-07-23ARM: dts: Renesas R9A06G032 SMP enable methodMichel Pollet1-0/+2
Add a special enable method for the second CA7 of the R9A06G032 as well as the default value for the "cpu-release-addr" property. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-07-23ARM: dts: Renesas R9A06G032 base device tree fileMichel Pollet1-0/+113
This adds the Renesas R9A06G032 bare bone support. This currently only handles the SYSCTRL block note, generic parts (gic, architected timer) and a UART. Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> [simon: updated MAINTAINERS file [simon: do not use r9a06g032-sysctrl.h as it is not in the renesas tree yet] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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