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2022-07-25ARM: dts: add EMAC AXI settings for Cyclone5Dinh Nguyen1-0/+8
Add the dts entries needed to support the EMAC AXI bus settings on the Cyclone5. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2022-05-04ARM: dts: socfpga: drop useless 'dma-channels/requests' propertiesKrzysztof Kozlowski1-2/+0
The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Reported-by: Rob Herring <robh@kernel.org> Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220430121902.59895-3-krzysztof.kozlowski@linaro.org
2022-04-07ARM: dts: socfpga: align interrupt controller node name with dtschemaKrzysztof Kozlowski1-1/+1
Fixes dtbs_check warnings like: $nodename:0: 'intc@fffed000' does not match '^interrupt-controller(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lore.kernel.org/r/20220317115705.450427-2-krzysztof.kozlowski@canonical.com
2021-12-27ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"Dinh Nguyen1-1/+1
Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"), which does a write to the CQSPI_REG_WR_COMPLETION_CTRL register regardless of any condition. Well, the Cadence QuadSPI controller on Intel's SoCFPGA platforms does not implement the CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register results in a crash! So starting with v5.16, I introduced the patch 98d948eb833 ("spi: cadence-quadspi: fix write completion support"), which adds the dts compatible "intel,socfpga-qspi" that is specific for versions that doesn't have the CQSPI_REG_WR_COMPLETION_CTRL register implemented. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v3: revert back to "intel,socfpga-qspi" v2: use both "cdns,qspi-nor" and "cdns,qspi-nor-0010"
2020-08-04Merge tag 'arm-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-0/+2
Pull ARM SoC DT updates from Arnd Bergmann: "As usual, there are many patches addressing minor issues in existing DTS files, such as DTC warnings, or adding support for additional peripherals. There are three added SoCs in existing product families: - Amazon: Alpine v3 is a 16-core Cortex-A72 SoC from Amazon's Annapurna Labs, otherwise known as AL73400 or first-generation Graviton, and following the already supported Cortex-A1`5 and Cortex-A57 based Alpine chips. This one is added together with the official Evaluation platform. - Qualcomm: The Snapdragon SDM630 platform is a family of mid-range mobile phone chips from 2017 based on Cortex-A53 or Kryo 260 CPUs. A total of five end-user products are added based on these, all Android phones from Sony: Xperia 10, 10 Plus, XA2, XA2 Plus and XA2 Ultra. - Renesas: RZ/G2H (r8a774e1) is currently the top model in the Renesas RZ/G family, and apparently closely related to the RZ/G2N and RZ/G2M models we already support but has a faster GPU and additional on-chip peripherals. It is added along with the HopeRun HiHope RZ/G2H development board A small number of new boards for already supported SoCs also debut: - Allwinner sunxi: Only one new machine, revision v1.2 of the Pine64 PinePhone (non-Android) smartphone, containing minor changes compared to earlier versions. - Amlogic Meson: WeTek Core2 is an Amlogic S912 (GXM) based Set-top-box - Aspeed: EthanolX is AMD's EPYC data center rerence platform, using an ASpeed AST2600 baseboard management controller. - Mediatek: Lenovo IdeaPad Duet 10.1" (kukui/krane) is a new Chromebook based on the MT8183 (Helio P60t) SoC. - Nvidia Tegra: ASUS Google Nexus 7 and Acer Iconia Tab A500 are two Android tablets from around 2012 using Tegra 3 and Tegra 2, respectively. Thanks to PostmarketOS, these can now run mainline kernels and become useful again. The Jetson Xavier NX Developer Kit uses a SoM and carrier board for the Tegra194, their latest 64-bit chip based on Carmel CPU cores and Volta graphics. - NXP i.MX: Five new boards based on the 32-bit i.MX6 series are added: The MYiR MYS-6ULX single-board computer, and four different models of industrial computers from Protonic. - Qualcomm: MikroTik RouterBoard 3011 is a rackmounted router based on the 32-bit IPQ8064 networking SoC Three older phones get added, the Snapdragon 808 (msm8992) based Xiaomi Libra (Mi 4C) and Microsoft Lumia 950, originally running Windows Phone, and the Snapdragon 810 (msm8994) based Sony Xperia Z5. - Renesas: In addition to the HiHope RZ/G2H board mentioned above, we gain support for board versions 3.0 and 4.0 of the earlier RZ/G2M and RZ/G2N reference boards. Beacon EmbeddedWorks adds another SoM+Carrier development board for RZ/G2M. - Rockchips: Radxa Rock Pi N8 development board and the VMARC RK3288 SoM it is based on, using the high-end 32-bit rk3288 SoC. Notable updates to existing platforms are usually for added on-chip peripherals, including: - ASpeed AST2xxx (various) - Allwinner (cpufreq, thermal, Pinephone touchscreen) - Amlogic Meson (audio, gpu dvdfs, board updates) - Arm Versatile - Broadcom (board updates for switch ports, Raspberry pi clock updates) - Hisilicon (various) - Intel/Altera SoCFPGA (various) - Marvell Armada 7xxx/8xxx (smmu) - Marvell MMP (GPU on mmp2/mmp3) - Mediatek mt8183 (USB, pericfg) - NXP Layerscape (VPU, thermal, DSPI) - NXP i.MX (VPU, bindings, board updates) - Nvidia Tegra194 (GPU) - Qualcomm (GPU, Interconnect, ...) - Renesas R-Car (SPI, IPMMU, board updates) - STMicroelectronics STM32 (various) - Samsung Exynos (various) - Socionext Uniphier (updates to serial, and pcie) - TI K3 (serdes, usb3, audio, sd, chipid) - TI OMAP (IPU/DSP remoteproc changes, dropping platform data)" * tag 'arm-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (605 commits) arm64: dts: meson: odroid-n2: add jack audio output support arm64: dts: meson: odroid-n2: enable audio loopback ARM: dts: berlin: Align L2 cache-controller nodename with dtschema arm64: dts: qcom: Add Microsoft Lumia 950 (Talkman) device tree arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device tree arm64: dts: qcom: msm8992: Add RPMCC node arm64: dts: qcom: msm8992: Add PSCI support. arm64: dts: qcom: msm8992: Add PMU node arm64: dts: qcom: msm8992: Add BLSP2_UART2 and I2C nodes arm64: dts: qcom: msm8992: Add SPMI PMIC arbiter device arm64: dts: qcom: msm8992: Add a SCM node arm64: dts: qcom: msm8992: Add a proper CPU map arm64: dts: qcom: bullhead: Move UART pinctrl to SoC arm64: dts: qcom: bullhead: Add qcom,msm-id arm64: dts: qcom: msm8992: Fix SDHCI1 arm64: dts: qcom: msm8992: Modernize the DTS style arm64: dts: qcom: Add support for Sony Xperia Z5 (SoMC Sumire-RoW) arm64: dts: qcom: Move msm8994-smd-rpm contents to lg-bullhead. arm64: dts: qcom: msm8994: Add support for SMD RPM arm64: dts: qcom: msm8992: Add a label to rpm-requests ...
2020-07-19arm: dts: socfpga: add reset-names to spi nodeDinh Nguyen1-0/+2
Add reset-names = "spi" to spi dts nodes. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2020-07-15ARM: dts: socfpga: Align L2 cache-controller nodename with dtschemaKrzysztof Kozlowski1-1/+1
Fix dtschema validator warnings like: l2-cache@fffff000: $nodename:0: 'l2-cache@fffff000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Fixes: 475dc86d08de ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2020-05-04ARM: dts: socfpga: Add fpga2hps and fpga2sdram bridgesSteffen Trumtrar1-0/+14
Add the remaining two bridges on the Cyclone-V SoCFPGA SoCs. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2020-05-04ARM: dts: socfgpa: set bridges status to disabledSteffen Trumtrar1-0/+2
The hps-to-fpga bridges can't be used, when the FPGA is not programmed. Set the default state to disabled and leave enabling them to the board-specific dts files. Although this changes behavior, there are no in-tree users of the bridges, so this won't break anything. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: socfpga: add missing reset-names for dmaDinh Nguyen1-0/+1
The dma dts node was missing the reset-names = "dma". The reset driver needs this line to get the reset property. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-07-30ARM: dts: socfpga: update to new Denali NAND bindingMasahiro Yamada1-1/+1
With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller and NAND chips"), the Denali NAND controller driver migrated to the new controller/chip representation. Update DT for it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-01-30ARM: dts: socfpga: update more missing reset propertiesSimon Goldschmidt1-0/+4
Add reset property for dma, can and sdram on socfpga gen5. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2019-01-15ARM: dts: socfpga: update missing reset property peripheralsDinh Nguyen1-0/+12
Add reset property for gpio, i2c, sdmmc, nand, qspi, spi, uart, and watchdog on base socfpga and socfpga_arria10. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-11-28ARM: dts: socfpga: use tabs for indentationSimon Goldschmidt1-1/+1
In two of the gen5 socfpga devicetree files, there are some lines indented using spaces instead of tabs. Fix this by correctly indenting them with tabs. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-11-28arm: dts: socfpga: remove dma-mask propertyDinh Nguyen1-1/+0
The dma-mask property has been removed from the NAND driver. Remove the property from the DTS files. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-11-28arm: dts: socfpga*.dts*: use SPDX-License-IdentifierSimon Goldschmidt1-14/+2
Follow the recent trend for the license description. This is also in an effort to fully sync the devicetrees with U-Boot. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-10-09ARM: dts: socfgpa: remove ethernet aliases from dtsiDinh Nguyen1-2/+0
Not all boards use two ethernet devices and/or use them in different order. As almost all in-tree boards already define their own ethernet aliases, remove them from the dtsi and add the aliases to the two boards, that are missing their own definition. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> [dinguyen@kernel.org: rebased to latest dts changes] Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-09-17ARM: dts: socfpga: add timer resets for SoCFPGA platformDinh Nguyen1-0/+8
Add the resets property for all the timers on the Cyclone5/Arria5/Arria10 platforms. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-08-30ARM: dts: socfpga: update NAND clocking for c5/a5Dinh Nguyen1-2/+10
The NAND IP needs 3 clocks(nand_x_clk, nand_clk, and nand_ecc_clk). The nand_x_clk and nand_ecc_clk are derived from the nand_clk. The nand_x_clk has a fixed divider of 4. Also, update the NAND dts property with the correct clocks property. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v2: add nand_ecc_clk and update commit message
2018-05-14ARM: dts: socfpga: Fix NAND controller node compatibleMarek Vasut1-1/+1
The compatible string for the Denali NAND controller is incorrect, fix it by replacing it with one matching the DT bindings and the driver. Cc: stable@vger.kernel.org Signed-off-by: Marek Vasut <marex@denx.de> Fixes: d837a80d19 ("ARM: dts: socfpga: add nand controller nodes") Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-05-14ARM: dts: socfpga: Fix NAND controller clock supplyMarek Vasut1-1/+1
The Denali NAND x-clock should be supplied by nand_x_clk, not by nand_clk. Fix this, otherwise the Denali driver gets incorrect clock frequency information and incorrectly configures the NAND timing. Cc: stable@vger.kernel.org Signed-off-by: Marek Vasut <marex@denx.de> Fixes: d837a80d19 ("ARM: dts: socfpga: add nand controller nodes") Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-03-23arm: dts: socfpga: fix GIC PPI warningPhilipp Puschmann1-1/+1
Fixes the warning "GIC: PPI13 is secure or misconfigured" by changing the interrupt type from level_low to edge_raising Signed-off-by: Philipp Puschmann <pp@emlix.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-01-23ARM: dts: socfpga: add i2c reset signalsTim Sander1-0/+4
Add the reset signals for the i2c controllers on Cyclone5-based SoCFPGA boards to the dtsi. Signed-off-by: Tim Sander <tim.sander@hbm.com> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-06-23ARM: dts: socfpga: Fix the ethernet clock phandleMarek Vasut1-2/+2
The ethernet block clock phandle must point to the clock node which represents the clock which directly supply the ethernet block. This is emac_x_clk , not emacx_clk , so fix this. From: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-07ARM: dts: socfpga: Add support for PMUFlorian Vaussard1-0/+9
The dual Cortex-A9 MPCore inside socfpga has a standard PMU unit for each core mapped in the DAP memory space. Add support for it! Tested with perf on a Cyclone 5 SoC DK. Reported-by: Alberto Dassatti <alberto.dassatti@heig-vd.ch> Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Tested-by: Alberto Dassatti <alberto.dassatti@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-07ARM: dts: socfpga: Add labels for CPU nodesFlorian Vaussard1-2/+2
This makes it easier to reference the CPU nodes afterwards. Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-07ARM: dts: socfpga: Do not include skeleton.dtsiFlorian Vaussard1-1/+0
The skeleton.dtsi file is now deprecated as noted in commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). The SoCFPGA device trees already contain the nodes that are defined in skeleton.dtsi (#address-cells, #size-cells, chosen, aliases, memory). Including skeleton.dtsi is useless and will produce the following warning when compiled with W=1: Node /memory has a reg or ranges property, but no unit name Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-07ARM: dts: socfpga: Remove unneeded unit namesFlorian Vaussard1-2/+2
Node eccmgr has a unit name, but do not have a reg property as only the child nodes do have this property. Likewise the usbphy node do not have a reg property. This will trigger the following warnings when compiled with W=1: Node /soc/eccmgr@ffd08140 has a unit name, but no reg property Node /soc/usbphy@0 has a unit name, but no reg property Remove the superfluous unit names. Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-07ARM: dts: socfpga: Add unit name to clock nodesFlorian Vaussard1-19/+19
Most clock nodes in Arria5, Cyclone5 and Arria10 have a reg property but does not have a unit name. This will trigger several warnings like this one (when compiled with W=1): Node /soc/clkmgr@ffd04000/clocks/periph_pll has a reg or ranges property, but no unit name Add the corresponding unit name to each node. Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-06ARM: dts: socfpga: add missing compatible string for SDRAM controllerDinh Nguyen1-1/+1
Add "altr,sdr-ctl" to the SDRAM controller node. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-06ARM: dts: socfpga: add base fpga region and fpga bridgesAlan Tull1-0/+27
Add h2f and lwh2f bridges. Add base FPGA Region to support DT overlays for FPGA programming. Add l3regs. Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v2: removed fpga-bridges, ranges, and reset-names
2017-01-05ARM: dts: socfpga: fpga manager data is 32 bitsDinh Nguyen1-1/+1
Adjust regs property for the FPGA manager data register to properly reflect that it is a single 32 bit register. Signed-off-by: Dalon Westergreen <dwesterg@altera.com> Signed-off-by: Alan Tull <atull@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2016-11-21ARM: dts: socfpga: fine-tune L2 cache configurationMarek Vasut1-0/+5
Enable double-linefill and increase prefetch offset, which gives considerable read performance boost. The following numbers were obtained using lmbench 3.0 bw_mem tool, for easier comparison, the numbers are pasted in two columns. The test machine has Cyclone V SoC running at 800MHz MPU clock and 512MiB 333MHz 16bit DDR3 DRAM. Without patch | With patch $ for i in rd wr rdwr cp fwr frd fcp bzero bcopy ; do echo $i ; bw_mem 64M $i ; done rd | rd 64.00 526.46 | 64.00 1151.06 wr | wr 64.00 329.95 | 64.00 346.14 rdwr | rdwr 64.00 342.07 | 64.00 367.24 cp | cp 64.00 239.79 | 64.00 322.47 fwr | fwr 64.00 1027.90 | 64.00 1025.38 frd | frd 64.00 322.36 | 64.00 641.89 fcp | fcp 64.00 256.99 | 64.00 408.41 bzero | bzero 64.00 1028.43 | 64.00 1025.07 bcopy | bcopy 64.00 294.73 | 64.00 357.19 Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-11-09ARM: dts: socfpga: add nand controller nodesSteffen Trumtrar1-0/+13
Add the denali nand controller to the socfpga dtsi. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2016-10-19ARM: dts: socfpga: add qspi nodeSteffen Trumtrar1-0/+14
Add the qspi node to the socfpga dtsi file. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-18ARM: dts: socfpga: enable arm,shared-override in the pl310Dinh Nguyen1-0/+1
Enable the bit(22) shared-override bit for the SoCFPGA family. While at it, enable the prefetch-data and prefetch-instr settings for the Arria10. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-04-11ARM: dts: socfpga: add reset control for USBDinh Nguyen1-0/+4
Add the resets property for the 2 USB controllers. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-03-21Merge tag 'armsoc-dt' of ↵Linus Torvalds1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Arnd Bergmann: "These are all the updates to device tree files for 32-bit platforms, plus a couple of related 64-bit updates: New SoC support: - Allwinner A83T - Axis Artpec-6 SoC - Mediatek MT7623 SoC - TI Keystone K2G SoC - ST Microelectronics stm32f469 New board or machine support: - ARM Juno R2 - Buffalo Linkstation LS-QVL and LS-GL - Cubietruck plus - D-Link DIR-885L - DT support for ARM RealView PB1176 and PB11MPCore - Google Nexus 7 - Homlet v2 - Itead Ibox - Lamobo R1 - LG Optimus Black - Logicpd dm3730 - Raspberry Pi Model A Other changes include - Lots of updates for Qualcomm APQ8064, MSM8974 and others - Improved support for Nokia N900 and other OMAP machines - Common clk support for lpc32xx - HDLCD display on ARM - Improved stm32f429 support - Improved Renesas device support, r8a779x and others - Lots of Rockchip updates - Samsung cleanups - ADC support for Atmel SAMA5D2 - BCM2835 (Raspberry Pi) improvements - Broadcom Northstar Plus enhancements - OMAP GPMC rework - Several improvements for Atmel SAMA5D2 / Xplained - Global change to remove inofficial "arm,amba-bus" compatible string" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (350 commits) ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus" ARM: dts: artpec: dual-license on artpec6.dtsi ARM: dts: ux500: add synaptics RMI4 for Ux500 TVK DT arm64: dts: juno/vexpress: fix node name unit-address presence warnings arm64: dts: foundation-v8: add SBSA Generic Watchdog device node ARM: dts: at91: sama5d2 Xplained: add leds node ARM: dts: at91: sama5d2 Xplained: add user push button ARM: dts: at91: sama5d2 Xplained: set pin muxing for usb gadget and usb host ARM: dts: stm32f429: Enable Ethernet on Eval board ARM: dts: omap3-sniper: TWL4030 keypad support Revert "ARM: dts: DRA7: Add dt nodes for PWMSS" ARM: dts: dm814x: dra62x: Disable wait pin monitoring for NAND ARM: dts: dm814x: dra62x: Fix NAND device nodes ARM: dts: stm32f429: Add Ethernet support ARM: dts: stm32f429: Add system config bank node ARM: dts: at91: sama5d2: add nand0 and nfc0 nodes ARM: dts: at91: sama5d2: add dma properties to UART nodes ARM: dts: at91: sama5d2 Xplained: Correct the macb irq pinctrl node ARM: dts: exynos: Don't overheat the Odroid XU3-Lite on high load ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs ...
2016-03-13ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"Masahiro Yamada1-1/+1
The compatible string "simple-bus" is well defined in ePAPR, while I see no documentation for the "arm,amba-bus" arnywhere in ePAPR or Documentation/devicetree/. DT is also used by other projects than Linux kernel. It is not a good idea to rely on such an unofficial binding. This commit - replaces "arm,amba-bus" with "simple-bus" - drops "arm,amba-bus" where it is used along with "simple-bus" Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-11ARM: dts: Add Altera L2 Cache and OCRAM EDAC entriesThor Thayer1-0/+20
Add the device tree entries and bindings needed to support the Altera L2 cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to declare and setup On-chip RAM properly: 8b907c8b62ac ("arm: dts: socfpga: Add OCRAM node") Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Acked-by: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: galak@codeaurora.org Cc: grant.likely@linaro.org Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: ijc+devicetree@hellion.org.uk Cc: Kumar Gala <galak@codeaurora.org> Cc: linux-arm-kernel@lists.infradead.org Cc: linux@arm.linux.org.uk Cc: linux-doc@vger.kernel.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: m.chehab@samsung.com Cc: Pawel Moll <pawel.moll@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Russell King <linux@arm.linux.org.uk> Link: http://lkml.kernel.org/r/1455132384-17108-2-git-send-email-tthayer@opensource.altera.com Signed-off-by: Borislav Petkov <bp@suse.de>
2015-12-21ARM: socfpga: dts: Enable MMC support at correct place in the DTMarek Vasut1-0/+1
The socfpga.dtsi explicitly enabled MMC support, but not all boards are equiped with an MMC card. There are setups which only have QSPI NOR. Therefore, disable the MMC support on socfpga.dtsi level and enable it on per-board basis. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alan Tull <atull@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Olof Johansson <olof@lixom.net> Cc: Thor Thayer <tthayer@altera.com> Cc: Vince Bridgers <vbridgers2013@gmail.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-10-22Merge tag 'socfpga_for_v4.4_cleanup' of ↵Olof Johansson1-64/+64
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt SoCFPGA dts cleanup for v4.4 - Re-order DTS nodes into correct alphabetical order * tag 'socfpga_for_v4.4_cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: dts: sort nodes alphabetically Signed-off-by: Olof Johansson <olof@lixom.net>
2015-10-16ARM: socfpga: dts: sort nodes alphabeticallySteffen Trumtrar1-64/+64
The sorting policy for this file is alphabetically. Reorder all nodes, that are out of place. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-10-16ARM: socfpga: dts: add fpga managerAlan Tull1-0/+7
Add FPGA manager to device tree for SoCFPGA. Signed-off-by: Alan Tull <atull@opensource.altera.com> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-13Merge tag 'socfpga_dts_for_v4.3_part_2' of ↵Olof Johansson1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt SoCFPGA DTS updates for v4.3, take 2 - Add DTS property "altr,modrst-offset" for reset driver to use - Add updated reset defines for the reset driver - Add reset property for EMACs on Arria10 * tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: socfpga: dts: Add resets for EMACs on Arria10 ARM: socfpga: dts: add "altr,modrst-offset" property dt-bindings: Add reset manager offsets for Arria10 Signed-off-by: Olof Johansson <olof@lixom.net>
2015-08-10ARM: socfpga: dts: add "altr,modrst-offset" propertyDinh Nguyen1-0/+1
The "altr,modrst-offset" property represents the offset into the reset manager that is the first register to be used by the driver to bring peripherals out of reset. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-25ARM: socfpga: dts: add osc1 as a possible parent for dbg_base_clkDinh Nguyen1-1/+1
The dbg_base_clk can also have osc1 has a parent. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-22ARM: socfpga: dts: add missing clock gates to socfpga.dtsiMatthew Gerlach1-1/+30
The gates for the clocks coming out of the sdram pll were missing. The change adds the missing nodes to the device tree. Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-22ARM: socfpga: dts: Fix gpio dts entry for the correct clockDinh Nguyen1-3/+3
The correct clock for the HPS gpio(s) should be the l4_mp_clk. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-22ARM: socfpga: dts: Correct the parent clock for l3_sp_clk and dbg_clkDinh Nguyen1-2/+2
The l3_sp_clk's parent should be the l3_mp_clk. This will account for the extra divider that is present for the l3_mp_clk. The dbg_clk's parent should be the dbg_at_clk. This will account for the extra divider that is present for the dbg_at_clk. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-19 06:09:34 +0300