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2023-06-21ARM: dts: Move .dts files to vendor sub-directoriesRob Herring1-2068/+0
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
2023-01-23ARM: tegra: Sort nodes by unit-address, then alphabeticallyThierry Reding1-30/+30
Nodes in device tree should be sorted by unit-address, followed by nodes without a unit-address, sorted alphabetically. Some exceptions are the top-level aliases, chosen, firmware, memory and reserved-memory nodes, which are expected to come first. These rules apply recursively with some exceptions, such as pinmux nodes or regulator nodes, which often follow more complicated ordering (often by "importance"). While at it, change the name of some of the nodes to follow standard naming conventions, which helps with the sorting order and reduces the amount of warnings from the DT validation tools. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-15ARM: tegra: Add usb-role-switch property to USB OTG portsStefan Eichenberger1-0/+1
If an USB port is an OTG port, then we should add the usb-role-switch property. Otherwise XUSB setup fails and therefore padctl is unable to set up the ports. This leads to broken USB and PCIe ports. Add the usb-role-switch properties to Tegra124 device-trees to fix the problem. The error message shown without this patch is e.g: usb2-0: usb-role-switch not found for otg mode [digetx@gmail.com: improved commit message] Tested-by: Thomas Graichen <thomas.graichen@gmail.com> # T124 Nyan Big Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-14ARM: tegra: Rename thermal zone nodesThierry Reding1-3/+3
The DT schema requires that nodes representing thermal zones include a "-thermal" suffix in their name. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-14ARM: tegra: Drop reg-shift for Tegra HS UARTThierry Reding1-0/+3
When the Tegra High-Speed UART is used instead of the regular UART, the reg-shift property is implied from the compatible string and should not be explicitly listed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-14ARM: tegra: Rename GPU node on Tegra124Thierry Reding1-1/+1
In order to be able to pass DT schema validation, change the GPU nodes' unit-address to the standard notation. Previously this was using a "0," prefix that originated from a time when the top-level device tree node contained #address-cells = <2>. Note that this technically breaks backwards-compatibility with certain older versions of the U-Boot bootloader because early versions used a hard-coded DT path lookup to find the GPU node and perform some fixups on it. However, this was changed to a compatible string based lookup in April 2016, so it's reasonable to expect people to update U-Boot on the systems that they want to use this updated kernel DTB with. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-14ARM: tegra: Rename GPIO hog nodes to match schemaThierry Reding1-2/+2
GPIO hog nodes must have a "hog-" prefix or "-hog" suffix according to the DT schema. Rename all such nodes to allow validation to pass. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-13ARM: tegra: apalis: Correct interrupt trigger type of temperature sensorDmitry Osipenko1-1/+1
The LM90 temperature sensor should use edge-triggered interrupt because LM90 hardware doesn't deassert interrupt line until temperature is back to normal state, which results in interrupt storm. Correct the interrupt trigger type. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Use standard name for Ethernet devicesThierry Reding1-1/+1
Ethernet device should be named "ethernet@<unit-address>". Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Add missing #sound-dai-cells property to codecsThierry Reding1-0/+1
Audio codecs need a #sound-dai-cells property, so add one to the audio codecs on various Tegra-based boards that don't have one. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-06-25ARM: tegra: Rename sdhci nodes to mmcThierry Reding1-1/+1
The new json-schema based validation tools require SD/MMC controller nodes to be named mmc. Rename all references to them. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-03-13ARM: tegra: Update sound node clocks in device treeSowjanya Komatineni1-1/+7
clk_out_1, clk_out_2, and clk_out_3 are part of Tegra PMC block but were previously erroneously provided by the clock and reset controller. clk_out_1 is dedicated for audio mclk on Tegra30 through Tegra210. This patch updates device tree sound node to use clk_out_1 from the PMC provider as mclk and uses assigned-clock properties to specify clock parents for clk_out_1 and extern1. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17ARM: tegra: apalis: Move PLL power supplies to XUSB pad controllerThierry Reding1-0/+5
The XUSB pad controller is responsible for supplying power to the PLLs used to drive the various USB, PCI and SATA pads. Move the PLL power supplies from the PCIe and XUSB controllers to the XUSB pad controller to make sure they are available when needed. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-04-17ARM: tegra: Convert to SPDX license tags for Tegra124 ApalisIgor Opaniuk1-38/+2
Replace boiler plate licenses texts with the SPDX license identifiers in Colibri/Apalis DTS files. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> [treding@nvidia.com: drop unneeded parentheses, keep license at X11] Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26ARM: tegra: apalis-tk1: shorten temperature-sensor nodeMarcel Ziswiler1-1/+1
Shorten temperature-sensor node to just temp-sensor as suggested in the binding documentation. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26ARM: tegra: apalis-tk1: get rid of fake clocks simple busMarcel Ziswiler1-11/+4
Get rid of the fake clocks simple bus and use node names as per the actual schematics. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26ARM: tegra: apalis-tk1: replace underscores in node names with dashesMarcel Ziswiler1-145/+145
As underscores in node names are not recommended replace them all where possible with dashes. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26ARM: tegra: apalis-tk1: drop module level model and compatibleMarcel Ziswiler1-3/+0
Drop model and compatible nodes from the module level device tree as they get overridden by the carrier board device tree anyway. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26ARM: tegra: apalis-tk1: reorder cpu dfll clock propertiesMarcel Ziswiler1-1/+1
Reorder CPU DFLL clock properties. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26ARM: tegra: apalis-tk1: enable emmc ddr52 modeMarcel Ziswiler1-0/+1
Add mmc-ddr-1_8v property enabling eMMC DDR52 mode. root@apalis-tk1-mainline:~# cat /sys/kernel/debug/mmc2/ios clock: 52000000 Hz actual clock: 52000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 8 (mmc DDR52) signal voltage: 1 (1.80 V) driver type: 0 (driver type B) root@apalis-tk1-mainline:~# hdparm -t /dev/mmcblk2 /dev/mmcblk2: Timing buffered disk reads: 256 MB in 3.02 seconds = 84.83 MB/sec Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26ARM: tegra: apalis-tk1: add proper emmc vmmc and vqmmc suppliesMarcel Ziswiler1-0/+2
Add proper eMMC vmmc and vqmmc supplies e.g. fixing signalling voltage. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26ARM: tegra: apalis-tk1: white-space clean-upMarcel Ziswiler1-3/+0
White-space clean-up. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26ARM: tegra: apalis-tk1: drop unused pinmux labelMarcel Ziswiler1-1/+1
Drop unused pinmux label. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26ARM: tegra: apalis-tk1: add missing regulatorsMarcel Ziswiler1-1/+13
Add missing regulators: - reg_module_3v3_audio being VDDA supply of SGTL5000 - VDDD supply of SGTL5000 actually being reg_1v8_vio - TMP451 temperature sensor vcc supply being reg_module_3v3 - usb3-0 vbus supply being reg_usbh_vbus - usb3-1 vbus supply being reg_usbo1_vbus - carrier board HDMI supply being reg_5v0 - carrier board sata target 5v supply being reg_5v0 - carrier board sata target 12v supply being reg_12v0 - carrier board reg_3v3 actually being backlight power supply Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26ARM: tegra: apalis-tk1: regulator clean-upMarcel Ziswiler1-50/+50
Just cosmetic regulator clean-up. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26ARM: tegra: apalis-tk1: reorder padctl propertiesMarcel Ziswiler1-11/+11
Reorder padctl properties. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26ARM: tegra: apalis-tk1: reorder host1x/hdmi propertiesMarcel Ziswiler1-2/+2
Reorder Host1x/HDMI properties. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-09-26ARM: tegra: apalis-tk1: add local-mac-address propertyMarcel Ziswiler1-0/+5
Add empty local-mac-address property to be filled in by boot loader (e.g. U-Boot). Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-07-09ARM: tegra: Fix unit_address_vs_reg DTC warnings for /memoryKrzysztof Kozlowski1-1/+1
Add a generic /memory node in each Tegra DTSI (with empty reg property, to be overidden by each DTS) and set proper unit address for /memory nodes to fix the DTC warnings: arch/arm/boot/dts/tegra20-harmony.dtb: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name The DTB after the change is the same as before except adding unit-address to /memory node. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-03ARM: tegra: apalis-tk1: Fix high speed UART compatibleMarcel Ziswiler1-3/+3
Turns out the compatible "nvidia,tegra124-hsuart" does not (yet) exist and everybody else also uses it only in conjunction with "nvidia,tegra30-hsuart". Reported-by: Martin Šafařík <msafarik@retia.cz> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis-tk1: Copyright period, spurious newlinesMarcel Ziswiler1-10/+1
Update the copyright period and get rid of some spurious newlines. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis-tk1: Hog group for ethernet, PCIe, reset GPIOsMarcel Ziswiler1-0/+18
The Apalis TK1 module uses some dedicated GPIOs as I210 gigabit Ethernet controller reset and to control RESET_MOCI aka reset module output carrier input on MXM3 pin 26. The Apalis Evaluation Board furthermore uses Apalis GPIO7 on MXM3 pin 15 as reset signal for its PLX PEX 8605 PCIe Switch. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis-tk1: Add missing as3722 gpio0 configurationMarcel Ziswiler1-3/+3
As the AS3722 GPIO0 is also a not connected on our Apalis TK1 module explicitly configure it to high-impedance as well. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis-tk1: Activate PWM pin muxing for pwm3Marcel Ziswiler1-4/+4
Activate PWM pin muxing for Apalis PWM3. Note that the same PWM3 is already active on pu6 being Apalis BKL1_PWM as well. Therefore exporting that one for raw sysfs access will fail and one has to revert to using the PWM backlight. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: apalis-tk1: Set critical tripsMarcel Ziswiler1-24/+3
Set "critical" trip temperatures for cpu, gpu, mem and pllx thermal zones. These trips can trigger shut down or reset. Similar to commit 40823f8e267f ("arm: tegra: set critical trips for Tegra124"). Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-03-08ARM: tegra: Fix I2C bus frequencies on Apalis/ColibriMarcel Ziswiler1-1/+1
Use a faster speed of 400 kbit/s for regular I2C busses. Use a slower speed of 10 kbit/s for DDC/EDID to improve reliability. Use a slower speed of 100 kbit/s for power I2C to be within specs of the LM95245 temperature sensor. While at it further annotate I2C pin usage. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-13ARM: dts: tegra: fix PCI bus dtc warningsRob Herring1-1/+1
dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: linux-tegra@vger.kernel.org Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: tegra: apalis-tk1: Update compatibility commentMarcel Ziswiler1-1/+1
Now with the new V1.1A HW card detect being implemented update resp. compatibility information. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: tegra: apalis-tk1: Adjust pin muxing for v1.1 HWMarcel Ziswiler1-30/+23
Configure Apalis MMC1 D6 GPIO on SDMMC3_CLK_LB_IN as reserved function without any pull-up/down. Configure GPIO_PV2 as SD1_CD# according to latest V1.1 HW. Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output driver enabled aka not tristated and input driver enabled as well as it features some magic properties even though the external loopback is disabled and the internal loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being set to 0xfffd according to the TRM! This pin is now a not-connect on V1.1 HW in order to avoid any interference. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: tegra: apalis-tk1: Optional DisplayPort hot-plug detectMarcel Ziswiler1-1/+1
Configure DP_HPD_PFF0 pin as optional DisplayPort hot-plug detect. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-25ARM: tegra: apalis-tk1: Pull-up temperature alertMarcel Ziswiler1-2/+2
Pull-up GPIO_PI6 connected to TMP451's ALERT#/THERM2#. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-08ARM: tegra: apalis-tk1: Drop leading 0 from unit-addressThierry Reding1-1/+1
According to the latest best practices, unit-addresses should be represented without any leading zeroes. Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-07-11ARM: tegra: Initial support for Apalis TK1Marcel Ziswiler1-0/+2100
This patch adds the device tree to support Toradex Apalis TK1 a computer on module which can be used on different carrier boards. The module consists of a Tegra TK1 SoC, a PMIC solution, 2 GB of DDR3L RAM, a bunch of level shifters, an eMMC, a TMP451 temperature sensor chip, an I210 gigabit Ethernet controller and a SGTL5000 audio codec. Furthermore, there is a Kinetis MK20DN512 companion micro controller for analogue, CAN and resistive touch functionality which is not yet supported. Anything that is not self contained on the module is disabled by default. The device tree for the Evaluation Board includes the module's device tree and enables the supported peripherals of the carrier board (the Evaluation Board supports almost all of them). Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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