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2020-03-16ARM: dts: uniphier: Set SCSSI clock and reset IDs for each channelKunihiko Hayashi1-2/+2
Currently common clock and reset IDs were used, however, each clock and reset ID should be used for each channel. Pro5 and PXs2 are affected by this fix, but the SCSSI clock gate of Pro5 is common to all channels. Fixes: 92fa4f4cc2cd ("ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-03-16ARM: dts: uniphier: Add USB3 controller nodes for Pro5Kunihiko Hayashi1-0/+148
Add USB3 controller nodes for Pro5 SoC and the boards. Pro5 SoC has 2 controllers. USB0 includes 1 SS-PHY and 1 HS-PHY, and USB1 includes 1 SS-PHY and 2 HS-PHY. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-29ARM: dts: uniphier: rename cache controller nodes to follow json-schemaMasahiro Yamada1-2/+2
Follow the standard nodename pattern "^(cache-controller|cpu)(@[0-9a-f,]+)*$" defined in schemas/cache-controller.yaml of dt-schema. Otherwise, after the dt-binding is converted to json-schema, 'make ARCH=arm dtbs_check' will show warnings like this: l2-cache@500c0000: $nodename:0: 'l2-cache@500c0000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-29ARM: dts: uniphier: rename NAND node names to follow json-schemaMasahiro Yamada1-1/+1
Follow the standard nodename pattern "^nand-controller(@.*)?" defined in Documentation/devicetree/bindings/mtd/nand-controller.yaml Otherwise, after the dt-binding is converted to json-schema, 'make ARCH=arm dtbs_check' will show warnings like this: nand@68000000: $nodename:0: 'nand@68000000' does not match '^nand-controller(@.*)?' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-29ARM: dts: uniphier: rename aidet node names to follow json-schemaMasahiro Yamada1-1/+1
Follow the standard nodename pattern "^interrupt-controller(@[0-9a-f,]+)*$" defined in schemas/interrupt-controller.yaml of dt-schema. Otherwise, after the dt-binding is converted to json-schema, make ARCH=arm dtbs_check' will show warnings like this: aidet@5fc20000: $nodename:0: 'aidet@5fc20000' does not match '^interrupt-controller(@[0-9a-f,]+)*$' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-29ARM: dts: uniphier: change SD/eMMC node names to follow json-schemaMasahiro Yamada1-2/+2
Follow the standard nodename pattern "^mmc(@.*)?$" defined in Documentation/devicetree/bindings/mmc/mmc-controller.yaml Otherwise, after the dt-binding is converted to json-schema, 'make ARCH=arm dtbs_check' will show warnings like this: sdhc@5a000000: $nodename:0: 'sdhc@5a000000' does not match '^mmc(@.*)?$' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-17ARM: dts: uniphier: add reset-names to NAND controller nodeMasahiro Yamada1-1/+2
The Denali NAND controller IP has separate reset control for the controller core and registers. Add the reset-names, and one more phandle accordingly. This is the approved DT-binding. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-25ARM: dts: uniphier: update to new Denali NAND bindingMasahiro Yamada1-1/+3
With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller and NAND chips"), the Denali NAND controller driver migrated to the new controller/chip representation. Update DT for it. In the new binding, the number of connected chips are described in DT instead of run-time probed. I added just one chip to the reference boards, where we do not know if the on-board NAND device is a single chip or multiple chips. If we added too many chips into DT, it would end up with the timeout error in nand_scan_ident(). I changed all the pinctrl properties to use the single CS. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-03ARM: dts: uniphier: add SD/eMMC controller nodesMasahiro Yamada1-0/+34
Add SD controller nodes for LD4, Pro4, sLD8, Pro5, and PXs2. This is also used as an eMMC controller for LD4, Pro4, and sLD8. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-28ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCsKunihiko Hayashi1-0/+22
Add nodes of SPI controller for LD4, Pro4, sLD8, Pro5 and PXs2. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-28ARM: uniphier: dts: add more clocks to Denali NAND controller nodeMasahiro Yamada1-1/+2
Catch up with the new binding of the Denali IP where three clocks, "nand", "nand_x", "ecc" are required. For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they are both 200MHz. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-15ARM: dts: uniphier: use proper SPDX-License-Identifier styleMasahiro Yamada1-8/+6
According to Documentation/process/license-rules.rst, move the SPDX License Identifier to the very top of the file. I used C++ comment style not only for the SPDX line but for the entire block because this seems Linus' preference [1]. I also dropped the parentheses to follow the examples in that document. [1] https://lkml.org/lkml/2017/11/25/133 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-11ARM: dts: uniphier: add efuse node for UniPhier 32bit SoCKeiji Hayashibara1-0/+33
Add efuse node for UniPhier LD4, Pro4, sLD8, Pro5 and PXs2. This efuse node is included in soc-glue. Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23ARM: dts: uniphier: add resets propertiesMasahiro Yamada1-0/+11
Add resets properties to all nodes that have reset lines. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-23ARM: dts: uniphier: add GPIO controller nodesMasahiro Yamada1-0/+14
The GPIO controller also acts as an interrupt controller and the interrupt lines are connected to the AIDET block. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-10-15ARM: dts: uniphier: fix W=2 build warningsMasahiro Yamada1-2/+2
Fix warnings like follows: Warning (node_name_chars_strict): Character '_' not recommended in ... Commit 8654cb8d0371 ("dtc: update warning settings for new bus and node/property name checks") says these checks are a bit subjective, but Rob also says to not add new W=2 warnings. The exising warnings should be fixed in order to catch new ones easily. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-28ARM: dts: uniphier: fix size of sdctrl nodesMasahiro Yamada1-1/+1
All registers are located within 0x400 size from the base address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-28ARM: dts: uniphier: add AIDET nodesMasahiro Yamada1-0/+7
Add UniPhier AIDET (ARM Interrupt Detector) nodes to support active low interrupts. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-15ARM: dts: uniphier: add Denali NAND controller nodeMasahiro Yamada1-0/+11
Add NAND controller node to LD4, Pro4, sLD8, Pro5, and PXs2. Set up pinctrl to enable 2 chip select lines except Pro4. The CS1 for Pro4 is multiplexed with other peripherals such as UART2, so I did not enable it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-15ARM: dts: uniphier use #include instead of /include/Masahiro Yamada1-1/+1
To include dt-bindings headers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-07-16ARM: dts: uniphier: use SPDX-License-Identifier (2nd)Masahiro Yamada1-37/+1
Commit fa53757bca33 ("ARM: dts: uniphier: use SPDX-License-Identifier") missed to touch these two. Now updating. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-06ARM: dts: uniphier: fix simple-bus unit address format errorMasahiro Yamada1-1/+1
Compiling the UniPhier DT files with W=1, DTC warns like follows: Warning (simple_bus_reg): Node /soc/system-bus@58c00000/support_card@1,1f00000/ethernet@00000000 simple-bus unit address format error, expected "0" Warning (simple_bus_reg): Node /soc/system-bus@58c00000/support_card@1,1f00000/uart@000b0000 simple-bus unit address format error, expected "b0000" Warning (simple_bus_reg): Node /soc/smpctrl@59800000 simple-bus unit address format error, expected "59801000" Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-06ARM: dts: uniphier: Use - instead of @ for DT OPP entriesViresh Kumar1-16/+16
Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-03-06ARM: dts: uniphier: remove skeleton.dtsi inclusionMasahiro Yamada1-2/+2
Commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated") declared that skeleton.dtsi was deprecated. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-11-05ARM: dts: uniphier: make 32bit SoC DTSI linearMasahiro Yamada1-117/+241
I notice some mistakes in the SoC DTSI; wrong interrupts properties of timer nodes, mismatch between the node name and the compatible for sdctrl block. Given those problems fixed, the common parts among SoCs are less than I had first expected. The more and more property overrides are making the SoC DTSI unreadable. Stretch out the SoC DTSI files and fix the following: - Fix the 3rd cell of the interrupts property of the timer nodes for Pro4, Pro5, PXs2 - Fix the node name mioctrl to sdctrl for Pro5, PXs2 - Fix the second region of l2 node for PXs2 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-11-05ARM: dts: uniphier: add CPU clocks and OPP table for Pro5 SoCMasahiro Yamada1-0/+74
Add a CPU clock to every CPU node and a CPU OPP table to use the generic cpufreq driver. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2016-10-22ARM: dts: uniphier: change MIO node to SD control nodeMasahiro Yamada1-2/+2
I made a mistake bacuse the Media I/O block is not implemented in these SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-30ARM: dts: uniphier: use clock/reset controllersMasahiro Yamada1-18/+30
The UniPhier reset controller driver has been merged. Enable it. Also, replace the fixed-rate clocks with the dedicated clock drivers. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-30ARM: dts: uniphier: switch over to PSCIMasahiro Yamada1-1/+2
Use PSCI for enable-method instead of SoC specific implementation. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-30ARM: dts: uniphier: match DT names to other projects and documentsMasahiro Yamada1-0/+199
All UniPhier device trees have the common prefix "uniphier-", so "ph1-" is just making names longer. Recent documents and other projects are not using PH1- prefixes any more. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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