summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/freescale
AgeCommit message (Collapse)AuthorFilesLines
2022-06-27arm64: dts: imx8mp-evk: correct eqos pad settingsPeng Fan1-15/+15
According to RM bit layout, BIT3 and BIT0 are reserved. 8 7 6 5 4 3 2 1 0 PE HYS PUE ODE FSEL X DSE X Although function is not broken, we should not set reserved bit. Fixes: dc6d5dc89bad ("arm64: dts: imx8mp-evk: enable EQOS ethernet") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-27arm64: dts: imx8mp-evk: correct vbus pad settingsPeng Fan1-1/+1
0x19 is not a valid setting. According to RM bit layout, BIT3 and BIT0 are reserved. 8 7 6 5 4 3 2 1 0 PE HYS PUE ODE FSEL X DSE X Not set reserved bit. Fixes: 43da4f92a611 ("arm64: dts: imx8mp-evk: enable usb1 as host mode") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-27arm64: dts: imx8mp-evk: correct gpio-led pad settingsPeng Fan1-1/+1
0x19 is not a valid setting. According to RM bit layout, BIT3 and BIT0 are reserved. 8 7 6 5 4 3 2 1 0 PE HYS PUE ODE FSEL X DSE X Correct setting with PE PUE set, DSE set to 0. Fixes: 50d336b12f34 ("arm64: dts: imx8mp-evk: Add GPIO LED support") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-27arm64: dts: imx8mp-evk: correct the uart2 pinctl valueSherry Sun1-2/+2
According to the IOMUXC_SW_PAD_CTL_PAD_UART2_RXD/TXD register define in imx8mp RM, bit0 and bit3 are reserved, and the uart2 rx/tx pin should enable the pull up, so need to set bit8 to 1. The original pinctl value 0x49 is incorrect and needs to be changed to 0x140, same as uart1 and uart3. Fixes: 9e847693c6f3 ("arm64: dts: freescale: Add i.MX8MP EVK board support") Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Sherry Sun <sherry.sun@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-27arm64: dts: imx8mp-evk: correct mmc pad settingsPeng Fan1-4/+4
According to RM bit layout, BIT3 and BIT0 are reserved. 8 7 6 5 4 3 2 1 0 PE HYS PUE ODE FSEL X DSE X Not set reserved bit. Fixes: 9e847693c6f3 ("arm64: dts: freescale: Add i.MX8MP EVK board support") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-27arm64: dts: imx8mn-evk: add bt-sco sound card supportShengjiu Wang1-0/+43
Add bt-sco sound card, which supports wb profile as default Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-27arm64: dts: imx8mq-evk: add bt-sco sound card supportShengjiu Wang1-0/+43
Add bt-sco sound card, which supports wb profile as default Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-27arm64: dts: imx8mm-evk: add bt-sco sound card supportShengjiu Wang1-0/+43
Add bt-sco sound card, which supports wb profile as default Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-27arm64: dts: imx8mp: correct clock of pgc_ispdwpPeng Fan1-1/+1
The deprecated DIV clk is previously part of the ISP composite clk, but there is still one child clk(IMX8MP_CLK_MEDIA_ISP_ROOT) sourcing from IMX8MP_CLK_MEDIA_ISP( previously IMX8MP_CLK_MEDIA_ISP_DIV) So IMX8MP_CLK_MEDIA_ISP_ROOT should be used, not IMX8MP_CLK_MEDIA_ISP_DIV. Fixes: 9d89189d5227 ("arm64: dts: imx8mp: Add MEDIAMIX power domains") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-20arm64: freescale/imx8mp-evk.dts: reorder nodes alphabeticallyUwe Kleine-König1-14/+14
The nodes after the root nodes are supposed to be ordered alphabetically. There is however an expection for &pinctrl that some consider to be good placed at the end of the file. So only move flexcan1 and flexcan2 to their proper place. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-20arm64: dts: imx8mq: Pass a label to the AIPS nodesFabio Estevam1-4/+4
Pass a label to the AIPS nodes to make it easier to reference it from other devicetree files. The other i.MX8M dtsi files already describe labels for the AIPS nodes. Make it available for imx8mq for consistency. U-Boot, for example usually needs to access the AIPS node to pass U-Boot-specific properties. Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-20arm64: dts: imx8m: Pass a label to the soc nodeFabio Estevam5-5/+5
Pass a label to the 'soc' node to make it easier to reference it from other devicetree files. U-Boot, for example usually needs to access the AIPS node to pass U-Boot-specific properties. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-20arm64: dts: imx8mm-venice-gw7902: fix UART1 CTSTim Harvey1-1/+1
Configure the correct GPIO for UART1 CTS. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-19arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM and PDK2Marek Vasut3-0/+1194
Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK2 carrier board. Currently supported are serial console, EQoS and FEC ethernets, eMMC, SD, SPI NOR, CAN. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: NXP Linux Team <linux-imx@nxp.com> To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-19arm64: dts: freescale: align led node names with dtschemaKrzysztof Kozlowski2-5/+5
The node names should be generic and DT schema expects certain pattern with 'led'. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-19arm64: dts: freescale: align gpio-key node names with dtschemaKrzysztof Kozlowski15-39/+39
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-19arm64: dts: imx8m: Disable job ring 0 nodesFabio Estevam4-0/+4
Now that the JR0 reservation is done in both upstream (v2.7) and downstream (NXP lf_v2.4) TF-A versions, the kernel fails to initialize the job ring 0: # dmesg | grep jr caam_jr 30901000.jr: failed to flush job ring 0 caam_jr: probe of 30901000.jr failed with error -5 Disable the sec_jr0 nodes by default to avoid the caam_jr probe error. Suggested-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-19arm64: dts: freescale: imx8qxp: Fix thermal zone name for cpu0Abel Vesa1-1/+1
The proper name is cpu0-thermal, not cpu-thermal0, so change it to that. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-19arm64: dts: mba8mx: Remove unneeded commentsFabio Estevam1-2/+0
The bootargs line is already commented out and the comment of UART4 does not apply, as uart4 node is not described. Remove both comments to make the dtsi cleaner. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-14arm64: dts: fsl: adjust whitespace around '='Krzysztof Kozlowski24-88/+88
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-14arm64: dts: fsl-ls10xx: use generic dma node namePeng Fan3-3/+3
dma-controller is preferred for dma node. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-14arm64: dts: imx8mp-evk: add regulator supply to CPU nodesLucas Stach1-1/+17
This supply is used by cpufreq to scale the voltage applied to the ARM voltage domain of the SoC when switching between the different operating points. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-14arm64: dts: imx8mm: Add SNVS LPGPRMarek Vasut1-0/+5
Add SNVS LPGPR bindings to MX8M Mini, the LPGPR is used to store boot counter. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: devicetree@vger.kernel.org To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-14arm64: dts: fsl: ls1012a: fix Micron SPI NOR compatibleKrzysztof Kozlowski1-1/+1
The proper compatible for Micron n25q128a11 SPI NOR flash should include vendor-prefix. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-10arm64: dts: imx8ulp: address build warningPeng Fan1-3/+3
Fix warnings such as: Warning (simple_bus_reg): /soc@0/gpio@2e200000: simple-bus unit address format error, expected "2e200080" Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-10arm64: dts: freescale: add i.MX93 11x11 EVK basic supportPeng Fan2-0/+115
Enable lpuart & SDHC for console and rootfs Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-10arm64: dts: freescale: Add i.MX93 dtsi supportPeng Fan2-0/+957
The i.MX 93 applications processors are the first in the i.MX portfolio to integrate the scalable Arm Cortex-A55 core, bringing performance and energy efficiency to Linux-based edge applications and the Arm Ethos-U65 microNPU, enabling developers to create more capable, cost-effective and energy-efficient ML applications. Add the basic dtsi support for i.MX93. Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-06-07arm64: s32g2: Pass unit name to soc nodeFabio Estevam1-1/+1
Pass unit name to soc node to fix the following W=1 build warning: arch/arm64/boot/dts/freescale/s32g2.dtsi:82.6-123.4: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Chester Lin <clin@suse.com> Signed-off-by: Chester Lin <clin@suse.com> Link: https://lore.kernel.org/r/20220514143505.1554813-1-festevam@gmail.com
2022-05-26Merge tag 'arm-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds58-314/+5355
Pull ARM DT updates from Arnd Bergmann: "There are 40 branches this time, adding a lot of new hardware support, and cleanups. Krzysztof Kozlowski continues his treewide cleanups. There are a number of new SoCs, all of them as part of existing families, and typically added along with a reference board: - Renesas RZ/G2UL (R9A07G043) is the single-core version of the RZ/G2L general-purpose MPU. - Renesas RZ/V2M (R9A09G011) is a smart camera SoC - Renesas R-Car V4H (R8A779G0) is an automotive chip with Cortex-A76 cores and deep learning accerlation. - Broadcom BCM47622 is a new broadband SoC based on a quad Cortex-A7 and dual Wifi-6. - Corstone1000 is a generic platform from Arm that is used for designing custom SoCs, the support for now is for the Fixed Virtual Platform emulation for it. - Mediatek MT8195 (Kompanio 1200) is a high-end consumer chip used in upcoming Chromebooks. - NXP i.MXRT1050 is a Cortex-M7 based microcontroller, the first MMU-less SoC to be added in a while New machines based on already supported SoCs this time are mainly for 32-bit platforms and include: - Two wireless routers based on Broadcom bcm4708 - 30 new boards based on NXP i.MX6, i.MX7 and i.MX8 families, mostly for the industrial embedded market, and on NXP LS1021A based IOT board. - Two ethernet switches based on Microchip LAN966 - Eight Qualcomm Snapdragon based machines, including a smartwatch, a Chromebook board and some phones - Another phone based on the old ST-Ericsson Ux500 platform - Seven STM32MP1 based boards - Four single-board computers based on Rockchip RK3566/RK3568" * tag 'arm-dt-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (791 commits) ARM: dts: kswitch-d10: enable networking ARM: dts: lan966x: add switch node ARM: dts: lan966x: add serdes node ARM: dts: lan966x: add reset switch reset node ARM: dts: lan966x: add MIIM nodes ARM: dts: lan966x: add hwmon node ARM: dts: lan966x: add basic Kontron KSwitch D10 support ARM: dts: lan966x: add flexcom I2C nodes ARM: dts: lan966x: add flexcom SPI nodes ARM: dts: lan966x: add all flexcom usart nodes ARM: dts: lan966x: add missing uart DMA channel ARM: dts: lan966x: add sgpio node ARM: dts: lan966x: swap dma channels for crypto node ARM: dts: lan966x: rename pinctrl nodes ARM: dts: at91: sama7g5: remove interrupt-parent from gic node ARM: dts: at91: use generic node name for dataflash ARM: dts: turris-omnia: Add atsha204a node arm64: dts: mt8192: Follow binding order for SCP registers arm64: dts: mediatek: add mtk-snfi for mt7622 arm64: dts: mediatek: mt8195-demo: enable uart1 ...
2022-05-05arm64: dt: imx8mp: support pwm polarity inversionMarkus Niebel1-4/+4
The i.MX8M Plus has the same PWM IP as i.MX6 / i.MX7. This IP and the driver supporting pwm polarity inversion. Switch CPU device tree fragment to use 3 pwm-cells. Tested on MBa8MPxL mainboard. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dt: imx8mn: support pwm polarity inversionMarkus Niebel1-4/+4
The i.MX8M Nano has the same PWM IP as i.MX6 / i.MX7. This IP and the driver supporting pwm polarity inversion. Switch CPU device tree fragment to use 3 pwm-cells. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dt: imx8mm: support pwm polarity inversionMarkus Niebel3-6/+6
The i.MX8M Mini has the same PWM IP as i.MX6 / i.MX7. This IP and the driver supporting pwm polarity inversion. Switch CPU device tree fragment to use 3 pwm-cells and correct board device trees. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dt: imx8mq: support pwm polarity inversionMarkus Niebel3-6/+6
The i.MX8MQ has the same PWM IP as i.MX6 / i.MX7. This IP and the driver supporting pwm polarity inversion. Switch CPU device tree fragment to use 3 pwm-cells and correct board device trees. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8mm-venice-gw7901: remove unnecessary cpu temp overrideTim Harvey1-12/+0
Remove the unnecessary cpu_alert0 and cpu_crit0 TMU node overrides as these are added dynamically by boot firmware based on CPU temperature grade. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8mm-venice-gw7902: add vdd_5p0 ADC channelTim Harvey2-0/+14
Add missing vdd_5p0 ADC channel for the GW7902 boards. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8m*venice: add missing clock-names to pcie_phyTim Harvey5-0/+5
Define the missing clock-names property for the pcie_phy required by the fsl,imx8-pcie-phy dt bindings. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8mm-venice-gw7902: fix pcie bindingsTim Harvey1-3/+4
Update the pcie bindings to the correct dt bindings: pcie_phy: - use pcie0_refclk - add required clock-names pcie: - remove pcie_phy clock as it comes from phy driver Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: freescale: reduce the interrup-map-maskMichael Walle5-5/+5
Reduce the interrupt-map-mask of the external interrupt controller to 0xf to align with the devicetree schema. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8mn-beacon: Enable RTS-CTS on UART3Adam Ford1-0/+3
There is a header for a DB9 serial port, but any attempts to use hardware handshaking fail. Enable RTS and CTS pin muxing and enable handshaking in the uart node. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8mm-beacon: Enable RTS-CTS on UART3Adam Ford1-0/+3
There is a header for a DB9 serial port, but any attempts to use hardware handshaking fail. Enable RTS and CTS pin muxing and enable handshaking in the uart node. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8mm: Use 100 kHz I2C2 on Data Modul i.MX8M Mini eDM SBCMarek Vasut1-1/+1
The I2C2 has SMBus device SMSC USB2514Bi connected to it, the device is capable of up to 100 kHz operation. Reduce the bus frequency to 100 kHz to guarantee this I2C device can work correctly. Fixes: 583f24ae42a07 ("arm64: dts: imx8mm: Add support for Data Modul i.MX8M Mini eDM SBC") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: NXP Linux Team <linux-imx@nxp.com> To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8mm: Disable USB2 OC on Data Modul i.MX8M Mini eDM SBCMarek Vasut1-0/+1
The USB2 port has USB Hub permanently connected to it, disable OC to avoid getting false OC indication. Fixes: 583f24ae42a07 ("arm64: dts: imx8mm: Add support for Data Modul i.MX8M Mini eDM SBC") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: NXP Linux Team <linux-imx@nxp.com> To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8mm: Add CPLD on MX8Menlo boardMarek Vasut1-1/+14
The CPLD on MX8Menlo board is used to operate custom hardware, the CPLD content is compatible with previous M53Menlo CPLD, add the bindings. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: devicetree@vger.kernel.org To: linux-arm-kernel@lists.infradead.org Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8mq-kontron-pitx-imx8m: Use the standard 'uart-has-rtscts'Fabio Estevam1-1/+1
The usage of the 'fsl,uart-has-rtscts' property is deprecated. Use the standard 'uart-has-rtscts' instead. Cc: Heiko Thiery <heiko.thiery@gmail.com> Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-By: Heiko Thiery <heiko.thiery@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8mp-verdin: Use the standard 'uart-has-rtscts'Fabio Estevam2-3/+3
The usage of the 'fsl,uart-has-rtscts' property is deprecated. Use the standard 'uart-has-rtscts' instead. Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8mp: Add MEDIA_BLK_CTRLPaul Elder1-0/+38
Add a DT node for the MEDIA_BLK_CTRL, which provides power domains for the camera and display devices. Signed-off-by: Paul Elder <paul.elder@ideasonboard.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8mp: Add MEDIAMIX power domainsLaurent Pinchart1-0/+23
Add the power domains related to the MEDIAMIX to the GPC. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8mp: add HSIO power-domainsLucas Stach1-6/+51
This adds the GPC and HSIO blk-ctrl nodes providing power control for the high-speed (USB and PCIe) IOs. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter KitManoj Sai2-0/+176
Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Plus PCIe - MIPI CSI - 2x CAN - Audio Out i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam. i.Core MX8M Plus needs to mount on top of this Evaluation board for creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-05-05arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoMManoj Sai1-0/+186
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam. General features: - NXP i.MX8M Plus - Up to 4GB LDDR4 - 8 eMMC - Gigabit Ethernet - USB 3.0, 2.0 Host/OTG - PCIe 3.0 interface - I2S - LVDS - rest of i.MX8M Plus features i.Core MX8M Plus needs to mount on top of Engicam baseboards for creating complete platform solutions. Add support for it. Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-19 02:23:42 +0300