Age | Commit message (Collapse) | Author | Files | Lines |
|
Since beginning the DTS extended the SPI0 in two places adding two SPI
muxes, each with same SPI NOR flash. Both used exactly the same
chip-selects, so this was clearly buggy code. Then in commit
d0f482bb06f9 ("arm64: dts: sparx5: Add the Sparx5 switch node") one SPI
mux was removed, while keeping the SPI NOR flash node.
This still leaves duplicated SPI nodes under same chip select 0,
reported by dtc W=1 warnings:
sparx5_pcb135_board.dtsi:92.10-96.4: Warning (unique_unit_address_if_enabled): /axi@600000000/spi@600104000/flash@0: duplicate unit-address (also used in node /axi@600000000/spi@600104000/spi@0)
Steen Hegelund confirmed that in fact there is a SPI mux, thus remove
the duplicated node without the mux.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|
|
Since beginning the DTS extended the SPI0 in two places adding two SPI
muxes, each with same SPI NOR flash. Both used exactly the same
chip-selects, so this was clearly buggy code. Then in commit
d0f482bb06f9 ("arm64: dts: sparx5: Add the Sparx5 switch node") one SPI
mux was removed, while keeping the SPI NOR flash node.
This still leaves duplicated SPI nodes under same chip select 0,
reported by dtc W=1 warnings:
sparx5_pcb134_board.dtsi:277.10-281.4: Warning (unique_unit_address_if_enabled): /axi@600000000/spi@600104000/flash@0: duplicate unit-address (also used in node /axi@600000000/spi@600104000/spi@0)
Steen Hegelund confirmed that in fact there is a SPI mux, thus remove
the duplicated node without the mux.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|
|
GPIO leds should not have unit addresses (no "reg" property), as
reported by dtc W=1 warnings:
sparx5_pcb135_board.dtsi:18.9-22.5: Warning (unit_address_vs_reg): /leds/led@0: node has a unit name, but no reg or ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|
|
GPIO leds should not have unit addresses (no "reg" property), as
reported by dtc W=1 warnings:
sparx5_pcb134_board.dtsi:18.9-21.5: Warning (unit_address_vs_reg): /leds/led@0: node has a unit name, but no reg or ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|
|
DT schema expects node names to match certain. This fixes dtbs_check
warnings like:
sparx5_pcb135_emmc.dtb: i2c0-imux@0: $nodename:0: 'i2c0-imux@0' does not match '^(i2c-?)?mux'
and dtc W=1 warnings:
sparx5_pcb135_board.dtsi:132.25-137.4: Warning (simple_bus_reg): /axi@600000000/i2c0-imux@0: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|
|
DT schema expects node names to match certain. This fixes dtbs_check
warnings like:
sparx5_pcb134_emmc.dtb: i2c0-emux@0: $nodename:0: 'i2c0-emux@0' does not match '^(i2c-?)?mux'
and dtc W=1 warnings:
sparx5_pcb134_board.dtsi:398.25-403.4: Warning (unique_unit_address_if_enabled): /axi@600000000/i2c0-imux@0: duplicate unit-address (also used in node /axi@600000000/i2c0-emux@0)
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|
|
The children of I2C mux should be named "i2c", according to DT schema
and bindings, and they should have unit address.
This fixes dtbs_check warnings like:
sparx5_pcb135.dtb: i2c0-imux@0: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'i2c_sfp1', 'i2c_sfp2', 'i2c_sfp3', 'i2c_sfp4' were unexpected)
and dtc W=1 warnings:
sparx5_pcb135_board.dtsi:172.23-180.4: Warning (simple_bus_reg): /axi@600000000/sfp-eth60: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|
|
The children of I2C mux should be named "i2c", according to DT schema
and bindings, and they should have unit address.
This fixes dtbs_check warnings like:
sparx5_pcb134_emmc.dtb: i2c0-imux@0: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'i2c_sfp1', ...
and dtc W=1 warnings:
sparx5_pcb134_board.dtsi:548.23-555.4: Warning (simple_bus_reg): /axi@600000000/sfp-eth12: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|
|
Unit address should match "reg" property, as reported by dtc W=1
warnings:
sparx5.dtsi:463.27-468.5: Warning (simple_bus_reg): /axi@600000000/serdes@10808000: simple-bus unit address format error, expected "610808000"
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|
|
Correct the reg address of mdio node to match unit address. Assume the
reg is not correct and unit address was correct, because there is
already node using the existing reg 0x110102d4.
sparx5.dtsi:443.25-451.5: Warning (simple_bus_reg): /axi@600000000/mdio@6110102f8: simple-bus unit address format error, expected "6110102d4"
Fixes: d0f482bb06f9 ("arm64: dts: sparx5: Add the Sparx5 switch node")
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|
|
The DTS code coding style expects exactly one space before and after '='
sign.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230702185108.43959-1-krzysztof.kozlowski@linaro.org
[claudiu.beznea: added link]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
|
|
The pinctrl device tree binding will be converted to YAML format. Rename
the pin nodes so they end with "-pins" to match the schema.
Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20220420194600.3416282-1-michael@walle.cc
Link: https://lore.kernel.org/r/20220319204628.1759635-5-michael@walle.cc
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
There is no reason for CPU node #address-cells to be set at 2, so lets
change them to 1 and update the reg property accordingly.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Link: https://lore.kernel.org/r/20230221105039.316819-2-robert.marko@sartura.hr
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot that
is shipped does not implement it as well.
I have tried flashing the latest BSP 2022.12 U-boot which did not work.
After contacting Microchip, they confirmed that there is no ATF for the
SoC nor PSCI implementation which is unfortunate in 2023.
So, disable PSCI as otherwise kernel crashes as soon as it tries probing
PSCI with, and the crash is only visible if earlycon is used.
Since PSCI is not implemented, switch core bringup to use spin-tables
which are implemented in the vendor U-boot and actually work.
Tested on PCB134 with eMMC (VSC5640EV).
Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Acked-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Link: https://lore.kernel.org/r/20230221105039.316819-1-robert.marko@sartura.hr
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
As all level 2 and level 3 caches are unified, add required
cache-unified and cache-level properties to fix warnings like:
sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property
Link: https://lore.kernel.org/r/20230421223155.115339-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
"okay" over "ok" is preferred for status property.
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Link: https://lore.kernel.org/r/20230127101824.93684-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
By coding style, unit address should not start with 0x.
Link: https://lore.kernel.org/r/20221210113343.63864-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
|
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment. No functional
changes (same DTB).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220526204110.831805-1-krzysztof.kozlowski@linaro.org
|
|
The node names should be generic and SPI NOR dtschema expects "flash".
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20220407143223.295344-2-krzysztof.kozlowski@linaro.org
|
|
Add support for ptp interrupt. This interrupt is used when using 2-step
timestamping. For each timestamp that is added in a queue, an interrupt
is generated.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
This adds the interrupt for the Sparx5 Frame DMA.
If this configuration is present the Sparx5 SwitchDev driver will use the
Frame DMA feature, and if not it will use register based injection and
extraction for sending and receiving frames to the CPU.
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
This provides the configuration for the currently available evaluation
boards PCB134 and PCB135.
The series depends on the following series currently on its way
into the kernel:
- Sparx5 Reset Driver
Link: https://lore.kernel.org/r/20210416084054.2922327-1-steen.hegelund@microchip.com/
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
This adds SGPIO devices for the Sparx5 SoC and configures it for the
applicable reference boards.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20201113145151.68900-4-lars.povlsen@microchip.com
|
|
This adds reset support to the Sparx5 SoC DT.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20201006200316.2261245-4-lars.povlsen@microchip.com
|
|
This patch add spi-nand DT nodes to the applicable Sparx5 boards.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200824203010.2033-7-lars.povlsen@microchip.com
|
|
This add spi-nor device nodes to the Sparx5 reference boards.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200824203010.2033-6-lars.povlsen@microchip.com
|
|
This adds a SPI controller to the Microchip Sparx5 SoC, as well as the
mmio-mux that is required to select the right SPI interface for a
given SPI device.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200824203010.2033-4-lars.povlsen@microchip.com
|
|
This adds a hwmon temperature node sensor to the Sparx5 SoC.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200618135951.25441-3-lars.povlsen@microchip.com
|
|
This adds eMMC support to the applicable Sparx5 board configuration
files.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200825081357.32354-4-lars.povlsen@microchip.com
|
|
This patch adds i2c devices and muxes to the Sparx5 reference boards.
Link: https://lore.kernel.org/r/20200615133242.24911-11-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock
to misc peripherals, specifically the SDHCI/eMMC controller.
Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.com
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
This add pinctrl support to the Microchip Sparx5 SoC.
Link: https://lore.kernel.org/r/20200615133242.24911-5-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
This adds the basic DT structure for the Microchip Sparx5 SoC, and the
reference boards, pcb125, pcb134 and pcb135. The two latter have a
NAND vs a eMMC centric variant (as a mount option).
Link: https://lore.kernel.org/r/20200615133242.24911-4-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|