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2023-05-03Merge tag 'for-6.4-rc1' of ↵Linus Torvalds1-0/+17
git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux Pull hardware timestamp engine updates from Dipen Patel: "The changes for the hte subsystem include: - Add Tegra234 HTE provider and relevant DT bindings - Update MAINTAINERS file for the HTE subsystem" * tag 'for-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux: hte: tegra-194: Use proper includes hte: Use device_match_of_node() hte: tegra-194: Fix off by one in tegra_hte_map_to_line_id() hte: tegra: fix 'struct of_device_id' build error hte: Use of_property_present() for testing DT property presence gpio: tegra186: Add Tegra234 hte support hte: handle nvidia,gpio-controller property hte: Deprecate nvidia,slices property hte: Add Tegra234 provider hte: Re-phrase tegra API document arm64: tegra: Add Tegra234 GTE nodes dt-bindings: timestamp: Deprecate nvidia,slices property dt-bindings: timestamp: Add Tegra234 support MAINTAINERS: Add HTE/timestamp subsystem details
2023-04-27arm64: tegra: Add Tegra234 GTE nodesDipen Patel1-0/+17
Add GTE LIC and AON GPIO nodes for the tegra234 SoC. Signed-off-by: Dipen Patel <dipenp@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
2023-04-25Merge tag 'soc-dt-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-2/+18
Pull ARM SoC devicetree updates from Arnd Bergmann: "The devicetree changes overall are again dominated by the Qualcomm Snapdragon platform that weighs in at over 300 changesets, but there are many updates across other platforms as well, notably Mediatek, NXP, Rockchips, Renesas, TI, Samsung and ST Microelectronics. These all add new features for existing machines, as well as new machines and SoCs. The newly added SoCs are: - Allwinner T113-s, an Cortex-A7 based variant of the RISC-V based D1 chip. - StarFive JH7110, a RISC-V SoC based on the Sifive U74 core like its JH7100 predecessor, but with additional CPU cores and a GPU. - Apple M2 as used in current Macbook Air/Pro and Mac Mini gets added, with comparable support as its M1 predecessor. - Unisoc UMS512 (Tiger T610) is a midrange smartphone SoC - Qualcomm IPQ5332 and IPQ9574 are Wi-Fi 7 networking SoCs, based on the Cortex-A53 and Cortex-A73 cores, respectively. - Qualcomm sa8775p is an automotive SoC derived from the Snapdragon family. Including the initial board support for the added SoC platforms, there are 52 new machines. The largest group are 19 boards industrial embedded boards based on the NXP i.MX6 (32-bit) and i.MX8 (64-bit) families. Others include: - Two boards based on the Allwinner f1c200s ultra-low-cost chip - Three 'Banana Pi' variants based on the Amlogic g12b (A311D, S922X) SoC. - The Gl.Inet mv1000 router based on Marvell Armada 3720 - A Wifi/LTE Dongle based on Qualcomm msm8916 - Two robotics boards based on Qualcomm QRB chips - Three Snapdragon based phones made by Xiaomi - Five developments boards based on various Rockchip SoCs, including the rk3588s-khadas-edge2 and a few NanoPi models - The AM625 Beagleplay industrial SBC Another 14 machines get removed: both boards for the obsolete 'oxnas' platform, three boards for the Renesas r8a77950 SoC that were only for pre-production chips, and various chromebook models based on the Qualcomm Sc7180 'trogdor' design that were never part of products" * tag 'soc-dt-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (836 commits) arm64: dts: rockchip: Add support for volume keys to rk3399-pinephone-pro arm64: dts: rockchip: Add vdd_cpu_big regulators to rk3588-rock-5b arm64: dts: rockchip: Use generic name for es8316 on Pinebook Pro and Rock 5B arm64: dts: rockchip: Drop RTC clock-frequency on rk3588-rock-5b arm64: dts: apple: t8112: Add PWM controller arm64: dts: apple: t600x: Add PWM controller arm64: dts: apple: t8103: Add PWM controller arm64: dts: rockchip: Add pinctrl gpio-ranges for rk356x ARM: dts: nomadik: Replace deprecated spi-gpio properties ARM: dts: aspeed-g6: Add UDMA node ARM: dts: aspeed: greatlakes: add mctp device ARM: dts: aspeed: greatlakes: Add gpio names ARM: dts: aspeed: p10bmc: Change power supply info arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMM050 Magnetometer arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMA255 Accelerometer arm64: dts: mediatek: mt6795: Add tertiary PWM node arm64: dts: rockchip: add panel to Anbernic RG353 series dt-bindings: arm: Add Data Modul i.MX8M Plus eDM SBC dt-bindings: arm: fsl: Add chargebyte Tarragon dt-bindings: vendor-prefixes: add chargebyte ...
2023-04-03arm64: tegra: Add DSU PMUs for Tegra234Jon Hunter1-0/+18
Populate the DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) devices for Tegra234 which has one DSU PMU per CPU cluster. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-04-03arm64: tegra: Drop serial clock-names and reset-namesKrzysztof Kozlowski1-2/+0
The serial node does not use clock-names and reset-names: tegra234-sim-vdk.dtb: serial@3100000: Unevaluated properties are not allowed ('clock-names', 'reset-names' were unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-03-02arm64: tegra: Bump CBB ranges property on Tegra194 and Tegra234Thierry Reding1-1/+1
Both Xavier (Tegra194) and Orin (Tegra234) support a 40-bit address map, so bump the CBB ranges property to cover all of the 1 TiB address space. This fixes an issue where some of the PCIe regions could not be remapped because of they were outside the memory specified by the CBB's ranges property. Reported-by: Jonathan Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-27arm64: tegra: Drop I2C iommus and dma-coherent propertiesThierry Reding1-16/+0
Drop the iommus and dma-coherent properties for the I2C controller device tree nodes. These are only needed for the device tree nodes that represent the GPC DMA controller, since that is the device performing the direct memory accesses. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-26arm64: tegra: Mark host1x as dma-coherent on Tegra194/234Mikko Perttunen1-0/+1
Ensure appropriate configuration is done to make the host1x device and context devices DMA coherent by adding the dma-coherent flag. Fixes: b35f5b53a87b ("arm64: tegra: Add context isolation domains on Tegra234") Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-24arm64: tegra: Populate the XUDC node for Tegra234Jon Hunter1-0/+23
Populate the Tegra XUSB device controller (XUDC) node for Tegra234. This is based upon a patch from Wayne Chang <waynec@nvidia.com>. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-17arm64: tegra: Populate address/size cells for Tegra234 I2CJon Hunter1-0/+16
Populate the address and size cells properties for the I2C devices on Tegra234. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-17arm64: tegra: Enable XUSB host function on Jetson AGX OrinWayne Chang1-0/+145
This commit enables XUSB host and pad controller on Jetson AGX Orin. Signed-off-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-17arm64: tegra: Sort nodes by unit-address, then alphabeticallyThierry Reding1-195/+195
Nodes in device tree should be sorted by unit-address, followed by nodes without a unit-address, sorted alphabetically. Some exceptions are the top-level aliases, chosen, firmware, memory and reserved-memory nodes, which are expected to come first. These rules apply recursively with some exceptions, such as pinmux nodes or regulator nodes, which often follow more complicated ordering (often by "importance"). While at it, change the name of some of the nodes to follow standard naming conventions, which helps with the sorting order and reduces the amount of warnings from the DT validation tools. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-17arm64: tegra: Bump #address-cells and #size-cellsThierry Reding1-763/+767
The #address-cells and #size-cells properties for the top-level bus were set to 1 because that was enough to represent the register ranges of all the IP blocks on that bus. However, most of these devices can do DMA to a larger address space, so translation of DMA addresses needs to happen in a 64-bit address space. Partially this was already done by the memory controller increasing that address space by setting #address-cells and #size-cells to 2, but a full DMA address translation would still cause truncation when traversing to the top-level bus. Fix this by setting #address-cells = <2> and #size-cells = <2> on the top-level bus and adjusting all "reg" and "ranges" properties of its children. While at it, also move the PCI and GPU nodes back under the top-level bus where they belong. The were put outside of it to work around this same problem. Signed-off-by: Thierry Reding <treding@nvidia.com>
2023-01-17arm64: tegra: Sort includesThierry Reding1-1/+1
Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Fix up compatible string for SDMMC1 on Tegra234Thierry Reding1-1/+1
The compatible string list for SDHCI on Tegra234 should be "nvidia,tegra234-sdhci", followed by the "nvidia,tegra186-sdhci" fallback. Use that consistently for all SDHCI controllers. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Remove unused reset-names for QSPIThierry Reding1-2/+0
The Tegra QSPI controller uses a single reset line, so there's no need for a reset-names property. Remove such properties. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Use correct compatible string for Tegra234 HDAThierry Reding1-1/+1
The Tegra234 HDA controller is not backwards-compatible with Tegra30, so drop the corresponding compatible string from the list. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Update cache propertiesPierre Gondois1-0/+33
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add dma-channel-mask in GPCDMA nodeAkhil R1-1/+3
Add dma-channel-mask property in Tegra GPCDMA device tree node. The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. This is wrong and does not align with the hardware. Correct this and update the interrupts property to list all 32 interrupts. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controllerVidya Sagar1-1/+1
Fix the starting address of the non-prefetchable aperture of PCIe C3 controller. Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add ECAM aperture info for all the PCIe controllersVidya Sagar1-22/+33
Add the ECAM aperture information for all the PCIe controllers of Tegra234. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Remove clock-names from PWM nodesThierry Reding1-8/+0
The Tegra PWFM controllers use a single clock, so there's no need for a clock-names property. Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add missing whitespaceThierry Reding1-1/+1
The unit-address of a node should be separated from the opening brace by a space. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Sort nodes by unit-addressThierry Reding1-192/+192
The P2U nodes that were recently added were not added in the correct order. Sort them in the right place by unit-address. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add Tegra234 SDMMC1 device tree nodePrathamesh Shete1-0/+56
Add device tree node for Tegra234 SDMMC1 instance. Add and enable SD card instance in device tree. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add SBSA UART for Tegra234Jon Hunter1-0/+7
Populate the SBSA UART for Tegra234 and enable this UART for Jetson AGX Orin. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Populate Tegra234 PWMsJon Hunter1-2/+78
Populate all the PWM devices for Tegra234. Finally, update the compatible string for the existing 'pwm1' node to just be 'tegra194-pwm' and remove the fallback to 'tegra186-pwm', which aligns with the binding documentation. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Remove unused property for I2CJon Hunter1-1/+0
Commit 156af9de0932 ("arm64: tegra: Add Tegra234 I2C devicetree nodes") populated the I2C device nodes for Tegra234. One of these nodes contains the property 'nvidia,hw-instance-id' which is neither documented or used. Remove this unused property. Fixes: 156af9de0932 ("arm64: tegra: Add Tegra234 I2C devicetree nodes") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Fix Prefetchable aperture ranges of Tegra234 PCIe controllersVidya Sagar1-3/+3
commit edf408b946d3 ("PCI: dwc: Validate iATU outbound mappings against hardware constraints") exposes an issue with the existing partitioning of the aperture space where the Prefetchable apertures of controllers C5, C7 and C9 in Tegra234 cross the 32GB boundary hardware constraint. This patch makes sure that the Prefetchable region doesn't spill over the 32GB boundary. Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Add NVDEC on Tegra234Mikko Perttunen1-0/+36
Add a device tree node for NVDEC on Tegra234. Booting the firmware requires some information regarding offsets within the firmware binary. These are passed through the device tree, but since the values vary depending on the firmware version, and the firmware itself is not available to the OS, the flasher is expected to provide a device tree overlay with values corresponding to the firmware it is flashing. The overlay then replaces the placeholder values here. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-11-21arm64: tegra: Fix ranges for host1x nodesMikko Perttunen1-1/+1
The currently specified 'ranges' properties don't actually include all devices under the host1x bus on Tegra194 and Tegra234. Expand them appropriately. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add GPCDMA support for Tegra I2CAkhil R1-0/+32
Add dma properties to support GPCDMA for I2C in Tegra 186 and later chips Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add iommus for HDA on Tegra234Mohan Kumar1-0/+1
Add the iommus property to the HDA node on Tegra234. Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add context isolation domains on Tegra234Mikko Perttunen1-0/+18
Add Host1x context isolation domains on Tegra234. On Tegra234 we have two IOMMUs that are connected to Host1x-channel programmed engines, so we have to include domains for each of them. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add MGBE nodes on Tegra234Thierry Reding1-0/+136
Add device tree nodes for the four instances of the Multi-Gigabit Ethernet (MGBE) IP found on NVIDIA Tegra234 SoCs. Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Fix up compatible for Tegra234 GPCDMAThierry Reding1-1/+0
There is no need to list the Tegra194-specific compatible for Tegra234 because the backwards-compatibility goes back all the way to Tegra186. Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-09-15arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DTVidya Sagar1-0/+927
Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree. The Tegra234 SoC contains 10 PCIe controllers and 24 P2U instances grouped into three different PHY bricks namely High-Speed IO (HSIO-8 P2Us) NVIDIA High Speed (NVHS-8 P2Us) and Gigabit Ethernet (GBE-8 P2Us) respectively. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Update compatible for Tegra234 GPCDMAAkhil R1-2/+3
Use the compatible specific to Tegra234 for GPCDMA to support additional features. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add Host1x and VIC on Tegra234Mikko Perttunen1-0/+46
Add device tree nodes for Host1x and VIC on Tegra234. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Enable native timers on Tegra234Kartik1-0/+22
The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add and enable the device tree node on Tegra234. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add node for CBB 2.0 on Tegra234Sumit Gupta1-0/+42
Tegra234 uses the Control Backbone (CBB) version 2.0. Add the nodes that enable error handling from the various CBB 2.0 fabrics found on Tegra234. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Mark BPMP channels as no-memory-wcMikko Perttunen1-0/+1
The Tegra SYSRAM contains regions access to which is restricted to certain hardware blocks on the system, and speculative accesses to those will cause issues. Patch 'misc: sram: Only map reserved areas in Tegra SYSRAM' attempted to resolve this by only mapping the regions specified in the device tree on the assumption that there are no such restricted areas within the 64K-aligned area of memory that contains the memory we wish to map. Turns out this assumption is wrong, as there are such areas above the 4K pages described in the device trees. As such, we need to use the bigger hammer that is no-memory-wc, which causes the memory to be mapped as Device memory to which speculative accesses are disallowed. As such, the previous patch in the series, 'firmware: tegra: bpmp: do only aligned access to IPC memory area', is required with this patch to make the BPMP driver only issue aligned memory accesses as those are also required with Device memory. Fixes: fec29bf04994 ("misc: sram: Only map reserved areas in Tegra SYSRAM") Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Yousaf Kaukab <ykaukab@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add Tegra234 GPCDMA device tree nodeAkhil R1-0/+42
Add device tree nodes for Tegra234 GPCDMA Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-07-08arm64: tegra: Add OPE device on Tegra210 and laterSameer Pujar1-0/+23
Output Processing Engine (OPE) is a client of AHUB and is present on Tegra210 and later generations of Tegra SoC. Add this device on the relevant SoC DTSI files. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-04-29arm64: tegra: Add memory controller channelsAshish Mhetre1-3/+21
From tegra186 onwards, memory controller support multiple channels. During the error interrupts from memory controller, corresponding channels need to be accessed for logging error info and clearing the interrupt. So add address and size of these channels in device tree node of tegra186, tegra194 and tegra234 memory controller. Also add reg-names for each of these reg items which are used by driver for mapping. Signed-off-by: Ashish Mhetre <amhetre@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-04-26arm64: tegra: Add ASRC device on Tegra186 and laterSameer Pujar1-0/+8
Asynchronous Sample Rate Converter (ASRC) is a client of AHUB and is present on Tegra186 and later generations of Tegra SoC. Add this device on the relevant SoC DTSI files. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-04-25arm64: tegra: Add node for Tegra234 CCPLEX clusterSumit Gupta1-0/+7
Adding CCPLEX cluster node to represent Tegra234 cpufreq. Tegra234 uses some of the CRAB (Control Register Access Bus) registers for CPU frequency requests. These registers are memory mapped to the CCPLEX_MMCRAB_ARM region. In this node, mapping the range of MMCRAB registers is required only for CPU frequency info. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-04-06arm64: tegra: Add QSPI controllers on Tegra234Ashish Singhal1-0/+28
This adds the QSPI controllers on the Tegra234 SoC and populates the SPI NOR flash device for the Jetson AGX Orin platform. Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: Add HDA device tree node for Tegra234Mohan Kumar1-0/+17
Add HDA device tree node for Tegra234 chip and for Jetson AGX Orin platform. Signed-off-by: Mohan Kumar <mkumard@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2022-02-24arm64: tegra: APE sound card for Jetson AGX OrinSameer Pujar1-0/+14
Add audio-graph based sound card support on Jetson AGX Orin platform. The sound card binds following modules: * I/O interfaces such as I2S and DMIC (to be specific I2S1, I2S2, I2S4, I2S6 and DMIC3 instances). * HW accelerators such as MVC, SFC, AMX, ADX and Mixer (all the available instances). Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-20 01:57:50 +0300