summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
AgeCommit message (Collapse)AuthorFilesLines
2024-07-01arm64: dts: renesas: r9a07g044: Add missing hypervisor virtual timer IRQGeert Uytterhoeven1-1/+4
Add the missing fifth interrupt to the device node that represents the ARM architected timer. While at it, add an interrupt-names property for clarity, Fixes: 68a45525297b2e9a ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/21f556eb7e903d5b9f4c96188fd4b6ae0db71856.1718890849.git.geert+renesas@glider.be
2024-06-03arm64: dts: renesas: rzg2l: Update fallback string for SDHI nodesLad Prabhakar1-2/+2
Use 'renesas,rzg2l-sdhi' as a fallback string for SDHI nodes, where hs400_disabled and fixed_addr_mode quirks are applied. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240422213006.505576-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-03-27arm64: dts: renesas: r9a07g0{43,44,54}: Update RZ/G2L family compatibleBiju Das1-1/+1
The number of pipe buffers on RZ/G2L family SoCs is 10, whereas on RZ/A2M it is 16. Replace 'renesas,rza2m-usbhs->renesas,rzg2l-usbhs' as family SoC compatible to handle this difference and use the SoC specific compatible in driver to avoid the ABI breakage with older DTB. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240319105356.87287-7-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-02-23arm64: dts: renesas: rzg2l-smarc: Enable DU and link with DSIBiju Das1-0/+19
Enable DU and link with DSI on RZ/{G2L,G2LC,V2L} SMARC EVK. Move DSI port properties from board dtsi to SoC dtsi and then link with DU and after that enable DU on the board dtsi. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240222132117.137729-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-02-23arm64: dts: renesas: r9a07g044: Add DU nodeBiju Das1-0/+27
Add DU node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240222132117.137729-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-02-22arm64: dts: renesas: rzg2l: Add missing interrupts to IRQC nodesLad Prabhakar1-1/+21
The IRQC IP block supports Bus error and ECCRAM interrupts on RZ/G2L and alike SoC's (listed below). Update the IRQC nodes with the missing interrupts, and additionally, include the 'interrupt-names' properties in the IRQC nodes so that the driver can parse interrupts by name. - R9A07G043U - RZ/G2UL - R9A07G044L/R9A07G044LC - RZ/{G2L,G2LC} - R9A07G054 - RZ/V2L Fixes: 5edc51af5b30 ("arm64: dts: renesas: r9a07g044: Add IRQC node") Fixes: 48ab6eddd8bb ("arm64: dts: renesas: r9a07g043u: Add IRQC node") Fixes: 379478ab09e0 ("arm64: dts: renesas: r9a07g054: Add IRQC node") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240205144421.51195-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25arm64: dts: renesas: rzg2l: Update overfow/underflow IRQ names for MTU3 channelsBiju Das1-8/+8
As per R01UH0914EJ0130 Rev.1.30 HW manual the MTU3 overflow/underflow interrupt names start with 'tci' instead of 'tgi'. Replace the below overflow/underflow interrupt names: - tgiv0->tciv0 - tgiv1->tciv1 - tgiu1->tciu1 - tgiv2->tciv2 - tgiu2->tciu2 - tgiv3->tciv3 - tgiv4->tciv4 - tgiv6->tciv6 - tgiv7->tciv7 - tgiv8->tciv8 - tgiu8->tciu8 Fixes: 26336d66d021 ("arm64: dts: renesas: r9a07g044: Add MTU3a node") Fixes: dd123dd01def ("arm64: dts: renesas: r9a07g054: Add MTU3a node") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230724091927.123847-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08arm64: dts: renesas: r9a07g044: Add MTU3a nodeBiju Das1-0/+70
Add MTU3a node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230417090159.191346-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08arm64: dts: renesas: r9a07g044: Add DSI nodeBiju Das1-0/+28
Add DSI node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230411100346.299768-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08arm64: dts: renesas: r9a07g044: Add vspd nodeBiju Das1-0/+13
Add vspd node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230411100346.299768-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-05-08arm64: dts: renesas: r9a07g044: Add fcpvd nodeBiju Das1-0/+12
Add fcpvd node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230411100346.299768-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-30arm64: dts: renesas: r9a07g044: Add CSI and CRU nodesLad Prabhakar1-0/+79
Add CSI and CRU nodes r9a07g044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230322125648.24948-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-30arm64: dts: renesas: rzg2l: Add clock-names and reset-names to DMAC nodesBiju Das1-0/+2
Add clock-names and reset-names to RZ/G2{L,LC,UL}, RZ/V2L and RZ/Five DMAC nodes. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230315064726.22739-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-10arm64: dts: renesas: r9a07g044: Update IRQ numbers for SSI channelsLad Prabhakar1-12/+7
From R01UH0914EJ0120 Rev.1.20 HW manual the interrupt numbers for SSI channels have been updated, SPI 329 - SSIF0 is now marked as reserved SPI 333 - SSIF1 is now marked as reserved SPI 335 - SSIF2 is now marked as reserved SPI 336 - SSIF2 is now marked as reserved SPI 341 - SSIF3 is now marked as reserved This patch drops the above IRQs from SoC DTSI. Fixes: 92a341315afc9 ("arm64: dts: renesas: r9a07g044: Add SSI support") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230217185225.43310-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systemsLad Prabhakar1-4/+4
The GICv3 interrupts binding does not have a cpumask. The CPU mask only applies to pre-GICv3. So just drop using them from GICv3 systems. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230206002136.29401-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-03-06arm64: dts: renesas: r9a07g044: Add Cortex-A55 PMU nodeLad Prabhakar1-0/+5
Enable the performance monitor unit for the Cortex-A55 cores on the RZ/G2L (r9a07g044) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230206001300.28937-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-08arm64: dts: renesas: rzg2l: Drop #address-cells from pinctrl nodesLad Prabhakar1-1/+0
This fixes the below dtbs_check warning: arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dtb: pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must be fixed: [[2]] is not of type 'object' From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dtb: pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must be fixed: [[2]] is not of type 'object' From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dtb: pinctrl@11030000: #address-cells: 'anyOf' conditional failed, one must be fixed: [[2]] is not of type 'object' From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml Drop #address-cells properties from pinctrl nodes as they have no addressed child nodes. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20221107172953.63218-1-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/r/20221107172953.63218-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-11-08arm64: dts: renesas: rzg2l: Add missing cache-level propertiesPierre Gondois1-0/+1
The DeviceTree Specification v0.3 specifies that the cache node 'cache-level' property is 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes. Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Link: https://lore.kernel.org/r/20221107155825.1644604-19-pierre.gondois@arm.com [geert: Update description] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-10-17arm64: dts: renesas: rzg2l: Drop WDT2 nodesLad Prabhakar1-15/+0
On members of the RZ/G2L family, WDT CH2 is specifically meant to check the operation of the Cortex-M33 CPU. Using it from a Cortex-A55 CPU would result in unexpected behaviour. Hence drop all WDT2 nodes and their references from the affected SoC and SoM DTSI files. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20221009230044.10961-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-09-19arm64: dts: renesas: Adjust whitespace around '{'Lad Prabhakar1-1/+1
Drop extra space around the '{' sign. No functional changes (same DTB). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220916100251.20329-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-08-22arm64: dts: renesas: r9a07g044: Fix SCI{Rx,Tx} interrupt typesBiju Das1-4/+4
As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022), the interrupt type of SCI{Rx,Tx} is edge triggered. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Fixes: f9a2adcc9e908907 ("arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes") Link: https://lore.kernel.org/r/20220802101534.1401342-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-08-22arm64: dts: renesas: r9a07g044: Add DMA support to RSPIBiju Das1-0/+6
Add DMA properties to RSPI nodes to support DMA operation. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220728122312.189766-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-08-15arm64: dts: renesas: r9a07g044: Update pinctrl node to handle GPIO interruptsLad Prabhakar1-0/+4
Add required properties in pinctrl node to handle GPIO interrupts. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220718195651.7711-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-08-15arm64: dts: renesas: r9a07g044: Add IRQC nodeLad Prabhakar1-0/+55
Add IRQC node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220718195651.7711-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-05-06arm64: dts: renesas: r9a07g044: Fix external clk node namesBiju Das1-4/+4
Add suffix '-clk' for can and extal clk node names and replace the clk node names audio_clk{1,2} with audio{1,2}-clk as per the device tree specification. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220428133156.18080-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-17arm64: dts: renesas: Fix pin controller node namesGeert Uytterhoeven1-1/+1
Align all pin controller node names with the expectations of the DT bindings in Documentation/devicetree/bindings/pinctrl/pinctrl.yaml. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/09a09c8ac9cb1a11b859c1ab9d9eae84cfefb1bb.1639666967.git.geert+renesas@glider.be
2021-12-16arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU nodeBiju Das1-0/+65
Add Mali-G31 GPU node to SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211208104026.421-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-14arm64: dts: renesas: r9a07g044: Create thermal zone to support IPABiju Das1-0/+16
Setup a thermal zone driven by SoC temperature sensor. Create passive trip points and bind them to CPUFreq cooling device that supports power extension. Based on the work done by Dien Pham <dien.pham.ry@renesas.com> and others for r8a77990 SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211208142729.2456-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-12-14arm64: dts: renesas: r9a07g044: Add TSU nodeBiju Das1-0/+26
Add TSU node to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211208142729.2456-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26arm64: dts: renesas: r9a07g044: Add OPP tableBiju Das1-0/+31
Add OPP table for RZ/G2L SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211124154316.28365-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26arm64: dts: renesas: r9a07g044: Add WDT nodesBiju Das1-0/+45
Add WDT{0, 1, 2} nodes to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211123141420.23529-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26arm64: dts: renesas: r9a07g044: Rename SDHI clocksBiju Das1-4/+4
Rename the below SDHI clocks to match with the clocks used in driver. imclk->core clk_hs->clkh imclk2->cd Also re-arrange the clocks to match with the sorting order used in the binding document. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20211122103905.14439-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26arm64: dts: renesas: r9a07g044: Add OSTM nodesBiju Das1-0/+33
Add OSTM{0,1,2} nodes to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211118191826.2026-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-26arm64: dts: renesas: r9a07g044: Sort psci nodeBiju Das1-5/+5
Sort psci node alphabetically. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211112081003.15453-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-19arm64: dts: renesas: r9a07g044: Add RSPI{0,1,2} nodesLad Prabhakar1-0/+48
Add RSPI{0,1,2} nodes to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211117011247.27621-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-15arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodesLad Prabhakar1-0/+30
Add SCI[0-1] nodes to r9a07g044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211109123110.8543-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-11-15arm64: dts: renesas: r9a07g044: Add SCIF[1-4] nodesLad Prabhakar1-0/+72
Add SCIF[1-4] nodes to r9a07g044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211103195600.23964-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-10-14arm64: dts: renesas: r9a07g044: Add GbEthernet nodesBiju Das1-0/+40
Add Gigabit Ethernet{0,1} nodes to SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211013075647.32231-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-10-08arm64: dts: renesas: r9a07g044: Add SDHI nodesBiju Das1-0/+32
Add SDHI{0, 1} nodes to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20211007155451.10654-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-10-08arm64: dts: renesas: r9a07g044: Add SPI Multi I/O Bus controller nodeLad Prabhakar1-0/+17
Add SPI Multi I/O Bus controller node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210928155852.32569-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-24arm64: dts: renesas: r9a07g044: Add DMA support to SSIBiju Das1-0/+8
Add dmac phandles to SSI nodes to support DMA operation. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210921084605.16250-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-20arm64: dts: renesas: r9a07g044: Add SSI supportBiju Das1-0/+76
Add SSI{0,1,2,3} nodes to RZ/G2L SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210814135526.15561-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-20arm64: dts: renesas: r9a07g044: Add external audio clock nodesBiju Das1-0/+14
Add external audio clocks nodes to RZ/G2L (a.k.a R9A07G044) SoC DTSI. The external audio clocks are configured as 0 Hz fixed frequency clocks by default. Boards that provide audio clocks should override them. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210814135526.15561-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-20arm64: dts: renesas: r9a07g044: Add USB2.0 device supportBiju Das1-0/+19
Add USB2.0 device support to RZ/G2L SoC DT. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210812151808.7916-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-20arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host supportBiju Das1-0/+95
Add USB2.0 phy and host support to SoC DT. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210812151808.7916-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-09-20arm64: dts: renesas: r9a07g044: Add DMAC supportBiju Das1-0/+36
Add DMAC support to RZ/G2L SoC DT. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210719092535.4474-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-08-12arm64: dts: renesas: r9a07g044: Add I2C interrupt-namesGeert Uytterhoeven1-0/+8
Add "interrupt-names" properties to the I2C device nodes, to make it easier to review the interrupt mappings. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/d35ba11bd705e3c728f94ff0414ac6ae1156244f.1626267422.git.geert+renesas@glider.be
2021-08-10arm64: dts: renesas: r9a07g044: Add CANFD nodeLad Prabhakar1-0/+41
Add CANFD node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210727133022.634-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-08-10arm64: dts: renesas: r9a07g044: Add ADC nodeLad Prabhakar1-0/+42
Add ADC node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210804202118.25745-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-08-10arm64: dts: renesas: r9a07g044: Add pinctrl nodeLad Prabhakar1-0/+13
Add GPIO/pinctrl node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210727112328.18809-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-08 00:17:19 +0300