Age | Commit message (Collapse) | Author | Files | Lines | |
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2023-03-06 | arm64: dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 systems | Lad Prabhakar | 1 | -7/+0 | |
The GICv3 interrupts binding does not have a cpumask. The CPU mask only applies to pre-GICv3. So just drop using them from GICv3 systems. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230206002136.29401-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> | |||||
2021-06-10 | arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's | Lad Prabhakar | 1 | -0/+25 | |
Add initial DTSI for RZ/G2{L,LC} SoC's. File structure: r9a07g044.dtsi => RZ/G2L family SoC common parts r9a07g044l1.dtsi => RZ/G2L R9A07G044L1 SoC specific parts r9a07g044l2.dtsi => RZ/G2L R9A07G044L2 SoC specific parts Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210609153230.6967-11-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |