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2023-10-23arm64: dts: socionext: add missing cache propertiesKrzysztof Kozlowski3-0/+4
As all level 2 and level 3 caches are unified, add required cache-unified property to fix warnings like: uniphier-ld11-ref.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20231023021221.2884828-3-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-10-23arm64: dts: Update cache properties for socionextPierre Gondois3-0/+4
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20221107155825.1644604-21-pierre.gondois@arm.com Signed-off-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231020195022.4183862-2-robh@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-21ARM: dts: Move .dts files to vendor sub-directoriesRob Herring3-3/+3
The arm dts directory has grown to 1559 boards which makes it a bit unwieldy to maintain and use. Past attempts stalled out due to plans to move .dts files out of the kernel tree. Doing that is no longer planned (any time soon at least), so let's go ahead and group .dts files by vendors. This move aligns arm with arm64 .dts file structure. There's no change to dtbs_install as the flat structure is maintained on install. The naming of vendor directories is roughly in this order of preference: - Matching original and current SoC vendor prefix/name (e.g. ti, qcom) - Current vendor prefix/name if still actively sold (SoCs which have been aquired) (e.g. nxp/imx) - Existing platform name for older platforms not sold/maintained by any company (e.g. gemini, nspire) The whole move was scripted with the exception of MAINTAINERS and a few makefile fixups. Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Paul Barker <paul.barker@sancloud.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Nick Hawkins <nick.hawkins@hpe.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom Acked-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Patrice Chotard <patrice.chotard@foss.st.com> Acked-by: Romain Perier <romain.perier@gmail.com> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com> Signed-off-by: Rob Herring <robh@kernel.org>
2023-02-09arm64: dts: uniphier: Fix property name in PXs3 USB nodeKunihiko Hayashi2-2/+2
The property "snps,usb2_gadget_lpm_disable" is wrong. It should be fixed to "snps,usb2-gadget-lpm-disable". Cc: stable@vger.kernel.org Fixes: 19fee1a1096d ("arm64: dts: uniphier: Add USB-device support for PXs3 reference board") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207021429.28925-1-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-09arm64: dts: uniphier: Add syscon-uhs-mode to SD nodeKunihiko Hayashi2-2/+4
Add sociopnext,syscon-uhs-mode prpperty to the SD node to refer the handle of the control logic node. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-9-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-09arm64: dts: uniphier: Add syscon compatible string to soc-glue-debugKunihiko Hayashi3-3/+3
Add "syscon" compatible string to the nodes for soc-glue-debug according to the DT schema. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-8-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-09arm64: dts: uniphier: Add missing reg properties for glue layer nodesKunihiko Hayashi3-0/+8
The nodes for some glue layers don't include necessary reg properties. Add the properties according to the DT schema. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-7-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-09arm64: dts: uniphier: Align node names for SoC-dependent controller and PHYs ↵Kunihiko Hayashi3-56/+56
with bindings The node names for SoC-dependent controllers and PHYs should be generic ones according to the DT schemas. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-6-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Add L2 cache nodeKunihiko Hayashi3-0/+26
Add a L2 cache node referenced from CPU nodes as the missing cache hierarchy information because the following warning was issued. cacheinfo: Unable to detect cache hierarchy for CPU 0 Early cacheinfo failed, ret = -2 Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-11-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Remove compatible "snps,dw-pcie" from pcie nodeKunihiko Hayashi2-2/+2
The generic platform driver pcie-designware-plat.c doesn't work for UniPhier PCIe host controller, because the controller has some necessary initialization sequence for the controller-specific logic. Currently the controller doesn't use "snps,dw-pcie" compatible, so this is no longer needed. Remove the compatible string from the pcie node. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-10-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Fix opp-table node name for LD20Kunihiko Hayashi1-2/+2
To fix dtbs_check warning: uniphier-ld20-akebi96.dt.yaml: opp-table0: $nodename:0: 'opp-table0' does not match '^opp-table(-[a-z0-9]+)?$' From schema: Documentation/devicetree/bindings/opp/opp-v2.yaml Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-9-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Add USB-device support for PXs3 reference boardKunihiko Hayashi3-1/+84
PXs3 reference board can change each USB port 0 and 1 to device mode with jumpers. Prepare devicetree sources for USB port 0 and 1. This specifies dr_mode, pinctrl, and some quirks and removes nodes for unused phys and vbus-supply properties. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-8-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Add ahci controller nodes for PXs3Kunihiko Hayashi2-0/+88
Add ahci core controller and glue layer nodes including reset-controller and sata-phy. This supports for PXs3 and the boards. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-7-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Use GIC interrupt definitionsKunihiko Hayashi7-88/+93
Use human-readable definitions for GIC interrupt type and flag, instead of hard-coding the numbers. No functional change. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-6-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Rename gpio-hog nodesKunihiko Hayashi4-5/+5
According to gpio-hog schema, should add the suffix "-hog" to the node names including gpio-hog to fix the following warning. uniphier-ld11-ref.dtb: gpio@55000000: 'xirq0' does not match any of the regexes: '^.+-hog(-[0-9+)?$', 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml This applies to the devicetre for LD11, LD20 and PXs3 SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-5-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Rename usb-glue node for USB3 to usb-controllerKunihiko Hayashi2-3/+3
This "usb-glue" stands for an external controller associated with USB core, however, this is not common. So rename to "usb-controller". Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-4-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Rename usb-phy node for USB2 to usb-controllerKunihiko Hayashi1-1/+1
Actual phy nodes are each child node. The parent node should be usb-controller node as a representation of the phy integration. This applies to the devicetree for LD11 SoC. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-3-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-09-28arm64: dts: uniphier: Rename pvtctl node to thermal-sensorKunihiko Hayashi2-2/+2
The pvtctl node belongs to thermal-sensor, so the node name should be renamed to thermal-sensor. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20220913042321.4817-2-hayashi.kunihiko@socionext.com' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-08-02arm64: dts: uniphier: Fix USB interrupts for PXs3 SoCKunihiko Hayashi1-4/+4
An interrupt for USB device are shared with USB host. Set interrupt-names property to common "dwc_usb3" instead of "host" and "peripheral". Cc: stable@vger.kernel.org Fixes: d7b9beb830d7 ("arm64: dts: uniphier: Add USB3 controller nodes") Reported-by: Ryuta NAKANISHI <nakanishi.ryuta@socionext.com> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-23arm64: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins for ↵Kunihiko Hayashi2-3/+3
RTL8211E UniPhier LD20 and PXs3 boards have RTL8211E ethernet phy, and the phy have the RX/TX delays of RGMII interface using pull-ups on the RXDLY and TXDLY pins. After the commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx delay config"), the delays are working correctly, however, "rgmii" means no delay and the phy doesn't work. So need to set the phy-mode to "rgmii-id" to show that RX/TX delays are enabled. Fixes: c73730ee4c9a ("arm64: dts: uniphier: add AVE ethernet node") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-07-10arm64: dts: uniphier: Add missing clock-names and reset-names to pcie-phyKunihiko Hayashi2-0/+4
This adds missing clock-names and reset-names to pcie-phy node according to Documentation/devicetree/bindings/phy/socionext,uniphier-pcie.yaml. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-10arm64: dts: uniphier: Rename ethphy node to ethernet-phyKunihiko Hayashi6-7/+7
This renames the node name "ethphy" to "ethernet-phy" according to Documentation/devicetree/bindings/net/mdio.yaml. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-07arm64: dts: uniphier: give fixed port number to support card serialMasahiro Yamada3-3/+3
Add this to the aliases node to make it more convenient. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-07arm64: dts: uniphier: add interrupts to support card serialMasahiro Yamada3-0/+12
Since commit e69f5dc623f9 ("dt-bindings: serial: Convert 8250 to json-schema"), the schema for "ns16550a" is checked. Since then, 'make ARCH=arm64 dtbs_check' is so noisy because the required property 'interrupts' is missing. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-04arm64: dts: uniphier: Add support for Akebi96Masami Hiramatsu2-0/+190
Add the device tree for Akebi96. Akebi96 is a 96boards certified development board based on UniPhir LD20. ( https://www.96boards.org/product/akebi96/ ) This board has; - MAX3421 USB-SPI chip on SPI port3 (for USB gadget port) - Simple frame buffer with 1080p fixed resolution. - I2S port which is connected to aout1b instead of aout1. - 3 serial ports, only serial3 has CTS/RTS. - No NAND, only eMMC on the board. - OP-TEE installed firmware. Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-04arm64: dts: uniphier: add #address-cells and #size-cells to SPI nodesMasahiro Yamada3-0/+16
Documentation/devicetree/bindings/spi/spi-uniphier.txt requires #address-cells and #size-cells, but they are missing in actual DT files. Also, 'make ARCH=arm64 dtbs_check' is really noisy. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-04arm64: dts: uniphier: Stabilize Ethernet RGMII mode of PXs3 ref boardKunihiko Hayashi1-0/+16
The RGMII PHY implemented in PXs3 ref board needs to change drive-strength properties of the Ethernet Tx pins to stabilize the PHY. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-04arm64: dts: uniphier: Add ethernet aliasesKunihiko Hayashi5-0/+6
Add 'aliases' properties for ethernet device. U-Boot performs a fix-up of the MAC address and will overwrite the values from the Linux devicetree for aliased ethernet device. The MAC address can be inherited from U-Boot by adding aliases of ethernet devices. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-04arm64: dts: uniphier: Add XDMAC nodeKunihiko Hayashi3-0/+24
Add external DMA controller support implemented in UniPhier SoCs. This supports for LD11, LD20 and PXs3. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-03-16arm64: dts: uniphier: Set SCSSI clock and reset IDs for each channelKunihiko Hayashi3-10/+10
Currently common clock and reset IDs were used, however, each clock and reset ID should be used for each channel. Fixes: 925c5c32f31d ("arm64: dts: uniphier: add SPI node for LD20, LD11 and PXs3") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-03-16arm64: dts: uniphier: Add nodes of thermal monitor and thermal zone for PXs3Kunihiko Hayashi1-0/+43
Add nodes of thermal monitor and thermal zone for UniPhier PXs3 SoC. The thermal monitor node is included in sysctrl. This patch gives the default value for PXs3 in the same way as LD20. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-03-16arm64: dts: uniphier: Enable spi node for PXs3 reference boardKunihiko Hayashi1-0/+10
PXs3 reference board has 2 spi connectors. This enables spi0 and spi1, and adds aliases properties for each spi to determine device name assignments. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-29arm64: dts: uniphier: rename NAND node names to follow json-schemaMasahiro Yamada3-3/+3
Follow the standard nodename pattern "^nand-controller(@.*)?" defined in Documentation/devicetree/bindings/mtd/nand-controller.yaml Otherwise, after the dt-binding is converted to json-schema, 'make ARCH=arm64 dtbs_check' will show warnings like this: nand@68000000: $nodename:0: 'nand@68000000' does not match '^nand-controller(@.*)?' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-29arm64: dts: uniphier: rename aidet node names to follow json-schemaMasahiro Yamada3-3/+3
Follow the standard nodename pattern "^interrupt-controller(@[0-9a-f,]+)*$" defined in schemas/interrupt-controller.yaml of dt-schema. Otherwise, after the dt-binding is converted to json-schema, 'make ARCH=arm64 dtbs_check' will show warnings like this: aidet@5fc20000: $nodename:0: 'aidet@5fc20000' does not match '^interrupt-controller(@[0-9a-f,]+)*$' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-02-29arm64: dts: uniphier: change SD/eMMC node names to follow json-schemaMasahiro Yamada3-5/+5
Follow the standard nodename pattern "^mmc(@.*)?$" defined in Documentation/devicetree/bindings/mmc/mmc-controller.yaml Otherwise, after the dt-binding is converted to json-schema, 'make ARCH=arm64 dtbs_check' will show warnings like this: sdhc@5a000000: $nodename:0: 'sdhc@5a000000' does not match '^mmc(@.*)?$' Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-17arm64: dts: uniphier: add reset-names to NAND controller nodeMasahiro Yamada3-3/+6
The Denali NAND controller IP has separate reset control for the controller core and registers. Add the reset-names, and one more phandle accordingly. This is the approved DT-binding. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-25arm64: dts: uniphier: add reserved-memory for secure memoryMasahiro Yamada3-6/+33
The memory regions specified by /memreserve/ are passed to early_init_dt_reserve_memory_arch() with nomap=false, so it is not suitable for reserving memory for Trusted Firmware-A etc. Use the more robust /reserved-memory node with the no-map property to prevent the kernel from mapping it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-06-25arm64: dts: uniphier: update to new Denali NAND bindingMasahiro Yamada5-0/+14
With commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller and NAND chips"), the Denali NAND controller driver migrated to the new controller/chip representation. Update DT for it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-15Merge tag 'uniphier-dt64-v5.1' of ↵Arnd Bergmann4-5/+103
git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into arm/dt UniPhier ARM64 SoC DT updates for v5.1 - Add PCI Express controller nodes * tag 'uniphier-dt64-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: arm64: dts: uniphier: sort labels in the same order as in dtsi arm64: dts: uniphier: Add PCIe host controller and PHY nodes Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-02-15arm64: dts: uniphier: sort labels in the same order as in dtsiMasahiro Yamada2-6/+6
Sort the labels in the same order as in the corresponding dtsi file, in other words, the order of reg address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-15arm64: dts: uniphier: Add PCIe host controller and PHY nodesKunihiko Hayashi3-0/+98
Add PCIe host controller and PHY nodes. This supports for LD20, PXs3 and their boards. This node defines PCIe memory, I/O, and config spaces as follows. MEM: 20000000-2ffdffff (255MB) I/O: 2ffe0000-2ffeffff ( 64KB) CFG: 2fff0000-2fffffff ( 64KB) Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-01-30arm64: dts: Remove inconsistent use of 'arm,armv8' compatible stringRob Herring3-10/+10
The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: Michal Simek <michal.simek@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Chanho Min <chanho.min@lge.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Wei Xu <xuwei5@hisilicon.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2018-12-10arm64: dts: uniphier: Add all CPUs in cooling mapsViresh Kumar1-7/+4
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-04arm64: dts: uniphier: Add USB2 PHY nodesKunihiko Hayashi1-0/+27
Add nodes of USB2 physical layer for UniPhier SoC. This supports LD11. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-04arm64: dts: uniphier: Add USB3 controller nodesKunihiko Hayashi5-0/+450
Add USB3 controller nodes including usb-core, resets, regulator, ss-phy and hs-phy. This supports for LD20, PXs3 and the boards. This includes additional efuse nodes for obtaining PHY trimming values. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-10-03arm64: dts: uniphier: add SD controller nodesMasahiro Yamada3-0/+36
Add SD controller nodes for LD20 and PXs3. LD20 does not support the UHS mode, while PXs3 supports it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-28arm64: dts: uniphier: add SPI node for LD20, LD11 and PXs3Kunihiko Hayashi3-0/+88
Add nodes of SPI controller for UniPhier SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-08-28arm64: uniphier: dts: add more clocks to Denali NAND controller nodeMasahiro Yamada3-3/+6
Catch up with the new binding of the Denali IP where three clocks, "nand", "nand_x", "ecc" are required. For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they are both 200MHz. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-07-22Merge tag 'uniphier-dt64-v4.19' of ↵Olof Johansson3-0/+4
git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt UniPhier ARM64 SoC DT updates for v4.19 - Add missing #cooling-cells properties - Add hp-det-gpio property to detect headphone via GPIO * tag 'uniphier-dt64-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier: arm64: dts: uniphier: add headphone detect gpio for LD11 global board arm64: dts: uniphier: add headphone detect gpio for LD20 global board arm64: dts: uniphier: Add missing cooling device properties for CPUs Signed-off-by: Olof Johansson <olof@lixom.net>
2018-07-19arm64: dts: uniphier: add headphone detect gpio for LD11 global boardKatsuhiro Suzuki1-0/+1
This patch adds GPIO for headphone detection on LD11 global board. Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-25 13:55:33 +0300