summaryrefslogtreecommitdiff
path: root/arch/mips/include/asm/cpu-features.h
AgeCommit message (Expand)AuthorFilesLines
2013-05-08MIPS: Build uasm-generated code only once to avoid CPU Hotplug problemHuacai Chen1-0/+3
2013-02-21Merge branch 'mips-next-3.9' of git://git.linux-mips.org/pub/scm/john/linux-j...Ralf Baechle1-0/+7
2013-02-19MIPS: Probe for and report hardware virtualization support.David Daney1-0/+4
2013-02-17MIPS: Add support for the M14KEc core.Steven J. Hill1-0/+3
2013-02-16MIPS: Add printing of ISA version in cpuinfo.Steven J. Hill1-0/+13
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle1-9/+9
2012-10-11MIPS: Add detection of DSP ASE Revision 2.Steven J. Hill1-0/+4
2012-10-11MIPS: perf: Add cpu feature bit for PCI (performance counter interrupt)Al Cooper1-0/+4
2012-09-14MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.Steven J. Hill1-3/+0
2012-09-14MIPS: Add base architecture support for RI and XI.Steven J. Hill1-0/+3
2010-08-05MIPS: Update comment for cpu_has_clo_clzRalf Baechle1-1/+2
2010-02-27MIPS: Implement Read Inhibit/eXecute InhibitDavid Daney1-0/+3
2010-02-02MIPS: 64-bit: Detect virtual memory sizeGuenter Roeck1-0/+7
2009-09-17MIPS: Allow kernel use of LL/SC to be separate from the presence of LL/SC.David Daney1-0/+3
2009-06-17MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.David Daney1-0/+4
2009-06-17MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.David Daney1-0/+4
2009-05-14MIPS: Enable CLO / CLZ instructions via separate CPU propertyRalf Baechle1-0/+9
2009-01-11MIPS: Hook Cavium OCTEON cache init into cache.cDavid Daney1-0/+3
2008-10-30MIPS: New feature test macro cpu_has_mips_rRalf Baechle1-0/+2
2008-10-11MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle1-0/+219