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path: root/arch/mips/include/asm/mipsregs.h
AgeCommit message (Expand)AuthorFilesLines
2024-02-28MIPS: mipsregs: Parse fp and sp register by name in parse_rJiaxun Yang1-2/+5
2024-02-23MIPS: mipsregs: Set proper ISA level for virt extensionsJiaxun Yang1-5/+8
2024-02-23MIPS: Implement microMIPS MT ASE helpersJiaxun Yang1-0/+9
2024-02-20MIPS: Unify define of CP0 registers for uasm codeJiaxun Yang1-52/+197
2024-01-08MIPS: Fix typosBjorn Helgaas1-2/+2
2023-01-26MIPS: Always use -Wa,-msoft-float and eliminate GAS_HAS_SET_HARDFLOATNathan Chancellor1-16/+4
2022-07-14MIPS: Remove VR41xx supportThomas Bogendoerfer1-14/+0
2022-02-22MIPS: remove asm/war.hThomas Bogendoerfer1-1/+0
2021-09-23MIPS: Avoid macro redefinitionsPaul Cercueil1-77/+113
2021-06-29MIPS: set mips32r5 for virt extensionsNick Desaulniers1-4/+4
2021-02-11MIPS: Make check condition for SDBBP consistent with EJTAG specTiezhu Yang1-0/+4
2020-09-21MIPS: Loongson-3: Enable COP2 usage in kernelHuacai Chen1-0/+7
2020-09-07MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config optionThomas Bogendoerfer1-2/+2
2020-08-24MIPS: Remove PNX833x alias NXP_STB22xThomas Bogendoerfer1-12/+0
2020-07-31MIPS: handle Loongson-specific GSExc exceptionWANG Xuerui1-0/+3
2020-07-31MIPS: add definitions for Loongson-specific CP0.Diag1 registerWANG Xuerui1-0/+8
2020-07-08MIPS: Unify naming style of vendor CP0.Config6 bitsHuacai Chen1-14/+14
2020-06-04KVM: MIPS: Add CONFIG6 and DIAG registers emulationHuacai Chen1-0/+4
2020-05-24MIPS: Tidy up CP0.Config6 bits definitionHuacai Chen1-13/+24
2020-05-22mips: Add CONFIG/CONFIG6/Cause reg fields macroSerge Semin1-0/+19
2020-05-22mips: Add CP0 Write Merge config supportSerge Semin1-0/+3
2020-05-21mips: MAAR: Use more precise address maskSerge Semin1-1/+1
2020-05-19mips: MAAR: Add XPA mode supportSerge Semin1-0/+10
2020-05-17MIPS: define more Loongson CP0.Config6 and CP0.Diag feature bitsWANG Xuerui1-0/+6
2020-01-23MIPS: Add MAC2008 SupportJiaxun Yang1-0/+3
2019-11-23MIPS: Ingenic: Disable abandoned HPTLB function.Zhou Yanjie1-0/+6
2019-08-06MIPS: Ingenic: Disable broken BTB lookup optimization.Zhou Yanjie1-0/+4
2019-02-04MIPS: MemoryMapID (MMID) SupportPaul Burton1-0/+4
2019-02-04MIPS: Add GINVT instruction helpersPaul Burton1-0/+7
2018-11-09MIPS: Avoid using .set mips0 to restore ISAPaul Burton1-10/+20
2018-10-17MIPS: Cleanup DSP ASE detectionPaul Burton1-1/+19
2018-08-14Merge tag 'mips_4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/l...Linus Torvalds1-10/+19
2018-08-07MIPS: Use dins to simplify __write_64bit_c0_split()Paul Burton1-1/+10
2018-08-07MIPS: Use read-write output operand in __write_64bit_c0_split()Paul Burton1-9/+7
2018-07-27Revert "MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratum"Rafał Miłecki1-3/+0
2018-07-24MIPS: Loongson64: Define and use some CP0 registersHuacai Chen1-0/+2
2018-06-19MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratumTokunori Ikegami1-0/+3
2018-05-15MIPS: Probe for MIPS MT perf counters per TCMatt Redfearn1-0/+5
2018-02-19MIPS: Add crc instruction support flag to elf_hwcapMarcin Nowakowski1-0/+1
2018-01-22MIPS: XPA: Standardise readx/writex accessorsJames Hogan1-10/+10
2018-01-22MIPS: XPA: Allow use of $0 (zero) to MTHC0James Hogan1-2/+2
2018-01-22MIPS: XPA: Use XPA instructions in assemblyJames Hogan1-10/+16
2018-01-22MIPS: VZ: Pass GC0 register names in $n formatJames Hogan1-188/+188
2018-01-22MIPS: VZ: Update helpers to use new asm macrosJames Hogan1-127/+37
2018-01-22MIPS: Add helpers for assembler macro instructionsJames Hogan1-0/+83
2018-01-10MIPS: mipsregs.h: Make read_c0_prid use const accessorJames Hogan1-1/+1
2018-01-10MIPS: mipsregs.h: Add read const Cop0 macrosJames Hogan1-10/+27
2017-11-09MIPS: Use SLL by 0 for 32-bit truncation in `__read_64bit_c0_split'Maciej W. Rozycki1-8/+6
2017-09-21MIPS: Fix input modify in __write_64bit_c0_split()James Hogan1-6/+9
2017-08-30MIPS: Add accessor & bit definitions for GlobalNumberPaul Burton1-0/+13
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