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2023-08-22Merge tag 'riscv-dt-for-v6.6-pt2' of ↵Arnd Bergmann6-23/+84
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.6 Part 2 T-Head: Add a second minimal devicetree for the second board using the th1520 SoC, the BeagleV Ahead. As with the Lichee Pi 4a, this is sufficient only for booting to a console, with work on the mmc, clocks and ethernet sides of things under way. A relicense to a dual licence for the existing devicetree files is also done, for good measure. RISC-V Devicetrees for v6.6-pt2 StarFive: Fix the sort order of some nodes that I resolved incorrectly during a merge conflict. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.6-pt2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: change TH1520 files to dual license riscv: dts: thead: add BeagleV Ahead board device tree dt-bindings: riscv: Add BeagleV Ahead board compatibles riscv: dts: starfive: fix jh7110 qspi sort order Link: https://lore.kernel.org/r/20230819-unwieldy-railing-9bba2b176aa7@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-16riscv: dts: change TH1520 files to dual licenseDrew Fustini3-3/+3
Modify the SPDX-License-Identifier for dual license of GPL-2.0 OR MIT. Signed-off-by: Drew Fustini <dfustini@baylibre.com> Acked-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Guo Ren <guoren@kernel.org> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-16riscv: dts: thead: add BeagleV Ahead board device treeDrew Fustini2-1/+62
The BeagleV Ahead single board computer uses the T-Head TH1520 SoC. Add a minimal device tree to support basic uart/gpio/dmac drivers so that a user can boot to a basic shell. Link: https://beagleboard.org/beaglev-ahead Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Drew Fustini <dfustini@baylibre.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15riscv: dts: starfive: fix jh7110 qspi sort orderConor Dooley1-19/+19
Emil pointed out that "13010000 sorts after 12070000". Reshuffle the entries to be in-order. Reported-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15Merge tag 'sunxi-dt-for-6.6-2' of ↵Arnd Bergmann1-0/+34
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt - Add D1 CAN controller nodes * tag 'sunxi-dt-for-6.6-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: riscv: dts: allwinner: d1: Add CAN controller nodes Link: https://lore.kernel.org/r/ZNjRV0kJ7v7+DAH5@wens.tw Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-15Merge tag 'riscv-dt-for-v6.6' of ↵Arnd Bergmann6-2/+872
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.6 StarFive: There's only StarFive stuff this time around, starting with some bindings to get clock ID defines out of the binding headers. Getting these (and the syscon bindings) in unblocked a swathe of stuff sitting on the list. Added are: new clock controllers and sycons, ethernet support, thermal sensors, USB and PCIe PHYs, hwrng, mmc and a few more besides for the VisionFive v2. The original VisionFive and BeagleV Starlight got some the thermal sensor support too, as that is supported by the same driver. These changes make the board actually usable with something other than an initramfs. Overlay support by way of the -@ flag set during dtb building, is added also. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: (26 commits) riscv: dts: starfive: jh7110: Fix GMAC configuration riscv: dts: starfive - Add hwrng node for JH7110 SoC riscv: dts: starfive - Add crypto and DMA node for JH7110 riscv: dts: starfive: Add mmc nodes on VisionFive 2 board riscv: dts: starfive: enable DCDC1&ALDO4 node in axp15060 riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC riscv: dts: starfive: jh7110: add the node and pins configuration for tdm riscv: dts: starfive: jh7110: add dma controller node riscv: dts: starfive: Add spi node and pins configuration riscv: dts: starfive: Add USB dts node for JH7110 riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110 riscv: dts: starfive: jh7110: Add temperature sensor node and thermal-zones riscv: dts: starfive: jh7100: Add temperature sensor node and thermal-zones riscv: dts: starfive: visionfive 2: Add configuration of gmac and phy riscv: dts: starfive: jh7110: Add ethernet device nodes riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node riscv: dts: starfive: jh7110: Add syscon nodes riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator ... Link: https://lore.kernel.org/r/20230813-naturist-fragment-ac7d10c453ba@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-13riscv: dts: starfive: jh7110: Fix GMAC configurationSamin Guo1-4/+4
Fixed configuration to improve the speed of TCP RX. Before: # iperf3 -s ----------------------------------------------------------- Server listening on 5201 (test #1) ----------------------------------------------------------- Accepted connection from 192.168.1.4, port 47604 [ 5] local 192.168.1.3 port 5201 connected to 192.168.1.4 port 47612 [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 36.3 MBytes 305 Mbits/sec [ 5] 1.00-2.00 sec 35.6 MBytes 299 Mbits/sec [ 5] 2.00-3.00 sec 36.5 MBytes 306 Mbits/sec [ 5] 3.00-4.00 sec 36.5 MBytes 306 Mbits/sec [ 5] 4.00-5.00 sec 35.7 MBytes 300 Mbits/sec [ 5] 5.00-6.00 sec 35.4 MBytes 297 Mbits/sec [ 5] 6.00-7.00 sec 37.1 MBytes 311 Mbits/sec [ 5] 7.00-8.00 sec 35.6 MBytes 298 Mbits/sec [ 5] 8.00-9.00 sec 36.4 MBytes 305 Mbits/sec [ 5] 9.00-10.00 sec 36.3 MBytes 304 Mbits/sec - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate [ 5] 0.00-10.00 sec 361 MBytes 303 Mbits/sec receiver After: # iperf3 -s ----------------------------------------------------------- Server listening on 5201 (test #1) ----------------------------------------------------------- Accepted connection from 192.168.1.4, port 47710 [ 5] local 192.168.1.3 port 5201 connected to 192.168.1.4 port 47720 [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 111 MBytes 932 Mbits/sec [ 5] 1.00-2.00 sec 111 MBytes 934 Mbits/sec [ 5] 2.00-3.00 sec 111 MBytes 934 Mbits/sec [ 5] 3.00-4.00 sec 111 MBytes 934 Mbits/sec [ 5] 4.00-5.00 sec 111 MBytes 934 Mbits/sec [ 5] 5.00-6.00 sec 111 MBytes 935 Mbits/sec [ 5] 6.00-7.00 sec 111 MBytes 934 Mbits/sec [ 5] 7.00-8.00 sec 111 MBytes 935 Mbits/sec [ 5] 8.00-9.00 sec 111 MBytes 934 Mbits/sec [ 5] 9.00-10.00 sec 111 MBytes 934 Mbits/sec [ 5] 10.00-10.00 sec 167 KBytes 933 Mbits/sec - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate [ 5] 0.00-10.00 sec 1.09 GBytes 934 Mbits/sec receiver Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Fixes: 1ff166c97972 ("riscv: dts: starfive: jh7110: Add ethernet device nodes") Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> [conor: converted to decimal per emil's request] Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-13riscv: dts: allwinner: d1: Add CAN controller nodesJohn Watts1-0/+34
The Allwinner D1, T113 provide two CAN controllers that are variants of the R40 controller. I have tested support for these controllers on two boards: - A Lichee Panel RV 86 Panel running a D1 chip - A Mango Pi MQ Dual running a T113-s3 chip Both of these fully support both CAN controllers. Signed-off-by: John Watts <contact@jookia.org> Link: https://lore.kernel.org/r/20230807191952.2019208-1-contact@jookia.org Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2023-08-12Merge tag 'sunxi-dt-for-6.6-1' of ↵Arnd Bergmann1-0/+10
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt - Add D1 GPADC node - Introduce support for OrangePi Zero 3 SBC - Enable DT overlay support for Allwinner H3 boards * tag 'sunxi-dt-for-6.6-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm: dts: Enable device-tree overlay support for sun8i-h3 pi devices arm64: dts: allwinner: h616: Add OrangePi Zero 3 board support dt-bindings: arm: sunxi: document Orange Pi Zero 3 board name arm64: dts: allwinner: h616: Split Orange Pi Zero 2 DT riscv: dts: allwinner: d1: Add GPADC node Link: https://lore.kernel.org/r/20230806180546.GA127039@jernej-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-09riscv: dts: starfive - Add hwrng node for JH7110 SoCJia Jie Ho1-0/+10
Add hardware rng controller node for StarFive JH7110 SoC. Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-09riscv: dts: starfive - Add crypto and DMA node for JH7110Jia Jie Ho1-0/+27
Add hardware crypto module and dedicated dma controller node to StarFive JH7110 SoC. Co-developed-by: Huan Feng <huan.feng@starfivetech.com> Signed-off-by: Huan Feng <huan.feng@starfivetech.com> Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-09riscv: dts: starfive: Add mmc nodes on VisionFive 2 boardWilliam Qiu2-0/+128
Add the mmc nodes for the StarFive JH7110 SoC. Set mmc0 node to emmc and set mmc1 node to sd. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-09riscv: dts: starfive: enable DCDC1&ALDO4 node in axp15060William Qiu1-0/+16
Enable DCDC1 node for vmmc-supply and enable ALDO4 node for vqmmc-supply. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-05riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoCWilliam Qiu2-0/+55
Add the quad spi controller node for the StarFive JH7110 SoC. Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com> Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-31riscv: dts: allwinner: d1: Add GPADC nodeMaksim Kiselev1-0/+10
This patch adds declaration of the general purpose ADC for D1 and T113s SoCs. Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20230619154252.3951913-5-bigunclemax@gmail.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-26riscv: dts: starfive: jh7110: add the node and pins configuration for tdmWalker Chen2-1/+61
Add the tdm controller node and pins configuration of tdm for the StarFive JH7110 SoC. Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-26riscv: dts: starfive: jh7110: add dma controller nodeWalker Chen1-0/+18
Add the dma controller node for the Starfive JH7110 SoC. Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-26riscv: dts: starfive: Add spi node and pins configurationWilliam Qiu2-0/+155
Add StarFive JH7110 SPI controller node and pins configuration on VisionFive 2 board. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-26riscv: dts: starfive: Add USB dts node for JH7110Minda Chen2-0/+37
Add USB wrapper layer and Cadence USB3 controller dts configuration for StarFive JH7110 SoC and VisionFive2 Board. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-26riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110Minda Chen1-0/+21
Add USB and PCIe PHY dts nodes for the StarFive JH7110 SoC. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-25riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy nodeConor Dooley1-0/+2
dtbs_check w/ W=1 complains: Warning (unit_address_vs_reg): /soc/ethernet@11c20000/ethernet-phy@7: node has a unit name, but no reg or ranges property Warning (avoid_unnecessary_addr_size): /soc/ethernet@11c20000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property The ethernet@11c20000 node is guarded by an `#if (!SW_ET0_EN_N)` in rzg2ul-smarc-som.dtsi, where the phy child node is added. In rzfive-smarc-som.dtsi, the ethernet node is marked disabled & the interrupt properties are deleted from the phy child node. As a result, the produced dts looks like: ethernet@11c20000 { compatible = "renesas,r9a07g043-gbeth", "renesas,rzg2l-gbeth"; /* snip */ #address-cells = <1>; #size-cells = <0>; status = "disabled"; ethernet-phy@7 { }; }; Adding a corresponding `#if (!SW_ET0_EN_N)` around the node in rzfive-smarc-som.dtsi avoids the complaint, as the empty child node is not added: ethernet@11c20000 { compatible = "renesas,r9a07g043-gbeth", "renesas,rzg2l-gbeth"; /* snip */ #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230712-squealer-walmart-9587342ddec1@wendy Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-07-25riscv: dts: starfive: jh7110: Add temperature sensor node and thermal-zonesHal Feng1-1/+53
Add temperature sensor and thermal-zones support for the StarFive JH7110 SoC. CPUFreq cooling is supported in thermal-zones. Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-25riscv: dts: starfive: jh7100: Add temperature sensor node and thermal-zonesHal Feng1-0/+37
Add temperature sensor and thermal-zones support for the StarFive JH7100 SoC. Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-25riscv: dts: starfive: visionfive 2: Add configuration of gmac and phySamin Guo3-0/+78
v1.3B: v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and inverse configurations. The tx_clk of v1.3B uses an external clock and needs to be switched to an external clock source. v1.2A: v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs delay configurations. v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to switch rx and rx to external clock sources. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Signed-off-by: Samin Guo <samin.guo@starfivetech.com> [conor: squashed a fix from Samin to use the actual properties] Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-20riscv: dts: starfive: jh7110: Add ethernet device nodesSamin Guo1-0/+69
Add JH7110 ethernet device node to support gmac driver for the JH7110 RISC-V SoC. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-20riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG nodeXingyu Wu1-2/+6
Add PLL clocks input from PLL clocks driver in SYSCRG node. Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-20riscv: dts: starfive: jh7110: Add syscon nodesWilliam Qiu1-0/+22
Add stg_syscon/sys_syscon/aon_syscon/PLL nodes for JH7110 SoC. Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-20riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodesXingyu Wu1-0/+55
Add STGCRG/ISPCRG/VOUTCRG new node to support JH7110 System-Top-Group, Image-Signal-Process and Video-Output clock and reset drivers for the JH7110 RISC-V SoC. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-20riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocksXingyu Wu2-0/+20
Add DVP and HDMI TX pixel external fixed clocks and the rates are 74.25MHz and 297MHz. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-12riscv: dts: Enable device-tree overlay support for starfive devicesFelix Moessbauer1-0/+6
Add the '-@' DTC option for the starfive devices. This option populates the '__symbols__' node that contains all the necessary symbols for supporting device-tree overlays (for instance from the firmware or the bootloader) on these devices. The starfive devices allow various modules to be connected and this enables users to create out-of-tree device-tree overlays for these modules. Please note that this change does increase the size of the resulting DTB by ~20%. For example, with v6.4 increase in size is as follows: jh7100-beaglev-starlight.dtb 6192 -> 7339 jh7100-starfive-visionfive-v1.dtb 6281 -> 7428 jh7110-starfive-visionfive-2-v1.2a.dtb 11101 -> 13447 jh7110-starfive-visionfive-2-v1.3b.dtb 11101 -> 13447 Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-06-21Merge tag 'riscv-dt-for-v6.5-pt2' of ↵Arnd Bergmann5-2/+497
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.5 Part 2 T-Head: Add a basic dtsi, Kconfig bits & trivial binding additions for the T-Head 1520 SoC (codename "light"). This SoC can be found on the Lichee Pi 4a, for which a minimal dts is added. Misc: Re-sort the dts Makefile to be in alphanumerical order by directory. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.5-pt2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: sort makefile entries by directory riscv: defconfig: enable T-HEAD SoC MAINTAINERS: add entry for T-HEAD RISC-V SoC riscv: dts: thead: add sipeed Lichee Pi 4A board device tree riscv: dts: add initial T-HEAD TH1520 SoC device tree riscv: Add the T-HEAD SoC family Kconfig option dt-bindings: riscv: Add T-HEAD TH1520 board compatibles dt-bindings: timer: Add T-HEAD TH1520 clint dt-bindings: interrupt-controller: Add T-HEAD's TH1520 PLIC Link: https://lore.kernel.org/r/20230620-fidelity-variety-60b47c889e31@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-20Merge tag 'riscv-dt-for-v6.5' of ↵Arnd Bergmann3-0/+93
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.5 StarFive: Watchdog nodes for both the JH7110 & its forerunner, the JH7100. PMU, P being power, support for the JH7110. PMIC and frequency scaling support for the JH7110 equipped VisionFive 2. Most of the DT bits for the JH7110, and the SBCs using it, are pending support for one of the clock controllers, so it's a smaller set of changes than I would have hoped for. Misc: Pick up some dt-binding cleanup that Palmer assigned to me & had no uptake from the respective maintainers. My powers of estimation failed me again, with part of my motivation for picking them up being the addition of new platforms that ended up not making it. Hopefully next window for those, as they were relatively close. Exclude the Allwinner and Renesas subdirectories from the Misc. MAINTAINERS entry, since I do not take care of those. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: Add cpu scaling for JH7110 SoC riscv: dts: starfive: Enable axp15060 pmic for cpufreq dt-bindings: interrupt-controller: sifive,plic: Sort compatible values dt-bindings: timer: sifive,clint: Clean up compatible value section riscv: dts: starfive: jh7110: Add watchdog node riscv: dts: starfive: jh7100: Add watchdog node riscv: dts: starfive: Add PMU controller node MAINTAINERS: exclude maintained subdirs in RISC-V misc DT entry Link: https://lore.kernel.org/r/20230612-fasting-floss-0bc05a08bc7a@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-06-19riscv: dts: sort makefile entries by directoryConor Dooley1-3/+3
New additions to the list have tried to respect alphanumeric ordering, but the thing was out of order to start with. Sort it. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-06-17Merge patch series "Add Sipeed Lichee Pi 4A RISC-V board support"Conor Dooley5-0/+495
Jisheng Zhang <jszhang@kernel.org> says: Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's TH1520 SoC. Add minimal device tree files for the core module and the development board. Support basic uart/gpio/dmac drivers, so supports booting to a basic shell. This also pulls in -rc2, because of some maintainers re-jigging that went on in the interim in commit 80e62bc8487b ("MAINTAINERS: re-sort all entries and fields"). Link: https://lore.kernel.org/r/20230617161529.2092-1-jszhang@kernel.org Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-06-17riscv: dts: thead: add sipeed Lichee Pi 4A board device treeJisheng Zhang4-0/+73
Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core module which is powered by T-HEAD's TH1520 SoC. Add minimal device tree files for the core module and the development board. Support basic uart/gpio/dmac drivers, so supports booting to a basic shell. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-06-17riscv: dts: add initial T-HEAD TH1520 SoC device treeJisheng Zhang1-0/+422
Add initial device tree for the TH1520 RISC-V SoC by T-HEAD. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-06-06riscv: dts: starfive: Add cpu scaling for JH7110 SoCMason Huo2-0/+49
Add the operating-points-v2 to support cpu scaling on StarFive JH7110 SoC. It supports up to 4 cpu frequency loads. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-06-06riscv: dts: starfive: Enable axp15060 pmic for cpufreqMason Huo1-0/+17
The VisionFive 2 board has an embedded pmic axp15060, which supports the cpu DVFS through the dcdc2 regulator. This patch enables axp15060 pmic and configs the dcdc2. Signed-off-by: Mason Huo <mason.huo@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-05-19riscv: dts: allwinner: d1: Add SPI controllers nodeMaksim Kiselev1-0/+37
Some boards form the MangoPi family (MQ\MQ-Dual\MQ-R) may have an optional SPI flash that connects to the SPI0 controller. This controller is the same for R329/D1/R528/T113s SoCs and should be supported by the sun50i-r329-spi driver. So let's add its DT nodes. Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20230510081121.3463710-6-bigunclemax@gmail.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-05-15riscv: dts: starfive: jh7110: Add watchdog nodeXingyu Wu1-0/+10
Add the watchdog node for the Starfive JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-05-15riscv: dts: starfive: jh7100: Add watchdog nodeXingyu Wu1-0/+10
Add watchdog node for the StarFive JH7100 RISC-V SoC. Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-05-08riscv: dts: starfive: Add PMU controller nodeWalker Chen1-0/+7
Add the pmu controller node for the StarFive JH7110 SoC. The PMU needs to be used by other modules, e.g. VPU,ISP,etc. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-29Merge tag 'riscv-for-linus-6.4-mw1' of ↵Linus Torvalds1-0/+7
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for runtime detection of the Svnapot extension - Support for Zicboz when clearing pages - We've moved to GENERIC_ENTRY - Support for !MMU on rv32 systems - The linear region is now mapped via huge pages - Support for building relocatable kernels - Support for the hwprobe interface - Various fixes and cleanups throughout the tree * tag 'riscv-for-linus-6.4-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (57 commits) RISC-V: hwprobe: Explicity check for -1 in vdso init RISC-V: hwprobe: There can only be one first riscv: Allow to downgrade paging mode from the command line dt-bindings: riscv: add sv57 mmu-type RISC-V: hwprobe: Remove __init on probe_vendor_features() riscv: Use --emit-relocs in order to move .rela.dyn in init riscv: Check relocations at compile time powerpc: Move script to check relocations at compile time in scripts/ riscv: Introduce CONFIG_RELOCATABLE riscv: Move .rela.dyn outside of init to avoid empty relocations riscv: Prepare EFI header for relocatable kernels riscv: Unconditionnally select KASAN_VMALLOC if KASAN riscv: Fix ptdump when KASAN is enabled riscv: Fix EFI stub usage of KASAN instrumented strcmp function riscv: Move DTB_EARLY_BASE_VA to the kernel address space riscv: Rework kasan population functions riscv: Split early and final KASAN population functions riscv: Use PUD/P4D/PGD pages for the linear mapping riscv: Move the linear mapping creation in its own function riscv: Get rid of riscv_pfn_base variable ...
2023-04-25Merge tag 'soc-dt-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds9-10/+1151
Pull ARM SoC devicetree updates from Arnd Bergmann: "The devicetree changes overall are again dominated by the Qualcomm Snapdragon platform that weighs in at over 300 changesets, but there are many updates across other platforms as well, notably Mediatek, NXP, Rockchips, Renesas, TI, Samsung and ST Microelectronics. These all add new features for existing machines, as well as new machines and SoCs. The newly added SoCs are: - Allwinner T113-s, an Cortex-A7 based variant of the RISC-V based D1 chip. - StarFive JH7110, a RISC-V SoC based on the Sifive U74 core like its JH7100 predecessor, but with additional CPU cores and a GPU. - Apple M2 as used in current Macbook Air/Pro and Mac Mini gets added, with comparable support as its M1 predecessor. - Unisoc UMS512 (Tiger T610) is a midrange smartphone SoC - Qualcomm IPQ5332 and IPQ9574 are Wi-Fi 7 networking SoCs, based on the Cortex-A53 and Cortex-A73 cores, respectively. - Qualcomm sa8775p is an automotive SoC derived from the Snapdragon family. Including the initial board support for the added SoC platforms, there are 52 new machines. The largest group are 19 boards industrial embedded boards based on the NXP i.MX6 (32-bit) and i.MX8 (64-bit) families. Others include: - Two boards based on the Allwinner f1c200s ultra-low-cost chip - Three 'Banana Pi' variants based on the Amlogic g12b (A311D, S922X) SoC. - The Gl.Inet mv1000 router based on Marvell Armada 3720 - A Wifi/LTE Dongle based on Qualcomm msm8916 - Two robotics boards based on Qualcomm QRB chips - Three Snapdragon based phones made by Xiaomi - Five developments boards based on various Rockchip SoCs, including the rk3588s-khadas-edge2 and a few NanoPi models - The AM625 Beagleplay industrial SBC Another 14 machines get removed: both boards for the obsolete 'oxnas' platform, three boards for the Renesas r8a77950 SoC that were only for pre-production chips, and various chromebook models based on the Qualcomm Sc7180 'trogdor' design that were never part of products" * tag 'soc-dt-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (836 commits) arm64: dts: rockchip: Add support for volume keys to rk3399-pinephone-pro arm64: dts: rockchip: Add vdd_cpu_big regulators to rk3588-rock-5b arm64: dts: rockchip: Use generic name for es8316 on Pinebook Pro and Rock 5B arm64: dts: rockchip: Drop RTC clock-frequency on rk3588-rock-5b arm64: dts: apple: t8112: Add PWM controller arm64: dts: apple: t600x: Add PWM controller arm64: dts: apple: t8103: Add PWM controller arm64: dts: rockchip: Add pinctrl gpio-ranges for rk356x ARM: dts: nomadik: Replace deprecated spi-gpio properties ARM: dts: aspeed-g6: Add UDMA node ARM: dts: aspeed: greatlakes: add mctp device ARM: dts: aspeed: greatlakes: Add gpio names ARM: dts: aspeed: p10bmc: Change power supply info arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMM050 Magnetometer arm64: dts: mediatek: mt6795-xperia-m5: Add Bosch BMA255 Accelerometer arm64: dts: mediatek: mt6795: Add tertiary PWM node arm64: dts: rockchip: add panel to Anbernic RG353 series dt-bindings: arm: Add Data Modul i.MX8M Plus eDM SBC dt-bindings: arm: fsl: Add chargebyte Tarragon dt-bindings: vendor-prefixes: add chargebyte ...
2023-04-19riscv: Use --emit-relocs in order to move .rela.dyn in initAlexandre Ghiti1-0/+7
To circumvent an issue where placing the relocations inside the init sections produces empty relocations, use --emit-relocs. But to avoid carrying those relocations in vmlinux, use an intermediate vmlinux.relocs file which is a copy of vmlinux *before* stripping its relocations. Suggested-by: Björn Töpel <bjorn@kernel.org> Suggested-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20230329045329.64565-7-alexghiti@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-04-14Merge tag 'sunxi-dt-for-6.4-1' of ↵Arnd Bergmann2-6/+90
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt - added D1 crypto node - enabled DVFS on OrangePi PC2 board - added GPIO line names on Nezha D1 board - added suniv USB nodes and enabled on licheepi-nano - new suniv boards: PopStick v1.1 and Lctech Pi - added Allwinner T113-s DTSI - added MangoPi MQ-R T113-s board variant - swapped DMA names for A23, A31, A33, D1, H3, H5, V3s * tag 'sunxi-dt-for-6.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: riscv: dts: allwinner: d1: Switch dma-names order for snps,dw-apb-uart nodes ARM: dts: sunxi: h3/h5: Switch dma-names order for snps,dw-apb-uart nodes ARM: dts: sun8i: v3s: Switch dma-names order for snps,dw-apb-uart nodes ARM: dts: sun8i: a23/a33: Switch dma-names order for snps,dw-apb-uart nodes ARM: dts: sun6i: a31: Switch dma-names order for snps,dw-apb-uart nodes ARM: dts: sunxi: add MangoPi MQ-R-T113 board dt-bindings: arm: sunxi: document MangoPi MQ-R board names ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi dts: add riscv include prefix link ARM: dts: suniv: Add Lctech Pi F1C200s devicetree ARM: dts: suniv: add device tree for PopStick v1.1 dt-binding: arm: sunxi: add two board compatible strings dt-bindings: vendor-prefixes: add Source Parts and Lctech names ARM: dts: suniv: licheepi-nano: enable USB ARM: dts: suniv: add USB-related device nodes riscv: dts: nezha-d1: add gpio-line-names arm64: dts: allwinner: h5: OrangePi PC2: add OPP table to enable DVFS riscv: dts: allwinner: d1: Add crypto engine node Link: https://lore.kernel.org/r/20230408125156.GA17050@jernej-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-04-08riscv: dts: allwinner: d1: Switch dma-names order for snps,dw-apb-uart nodesCristian Ciocaltea1-6/+6
Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties") documented dma-names property to handle Allwinner D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the reverse of what a bunch of different boards expect. The initial proposed solution was to allow a flexible dma-names order in the binding, due to potential ABI breakage concerns after fixing the DTS files. But luckily the Allwinner boards are not affected, since they are using a shared DMA channel for rx and tx. Hence, the first step in fixing the inconsistency was to change dma-names order in the binding to tx->rx. Do the same for the snps,dw-apb-uart nodes in the DTS file. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230321215624.78383-7-cristian.ciocaltea@collabora.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-04-06Merge branch 'riscv-jh7110_initial_dts' into riscv-dt-for-nextConor Dooley6-1/+1054
Merge Hal's series adding support for the new StarFive JH7110 SoC. There's a few bindings here for core components that were not picked up by the various maintainers for the subsystems (previously Palmer would pick these up via the RISC-V tree) & the first two commits in the branch are shared with the clk tree, since the dts depends on defines in the dt-binding headers. This is based on -rc2, as the board does not actually boot on -rc1 due to the bug Linus introduced. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device treeEmil Renner Berthing4-1/+246
Add a minimal device tree for StarFive JH7110 VisionFive 2 board which has version A and version B. Support booting and basic clock/reset/pinctrl/uart drivers. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-04-05riscv: dts: starfive: Add StarFive JH7110 pin function definitionsJianlong Huang1-0/+308
Add pin function definitions for StarFive JH7110 SoC. Tested-by: Tommaso Merciai <tomm.merciai@gmail.com> Co-developed-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-08 20:58:05 +0300