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path: root/arch/riscv/include/asm/cacheflush.h
AgeCommit message (Expand)AuthorFilesLines
2022-10-21RISC-V: Fix compilation without RISCV_ISA_ZICBOMAndrew Jones1-8/+0
2022-10-13Merge patch series "Some style cleanups for recent extension additions"Palmer Dabbelt1-0/+2
2022-10-13riscv: drop some idefs from CMO initializationHeiko Stuebner1-0/+2
2022-09-17RISC-V: Avoid coupling the T-Head CMOs and ZicbomPalmer Dabbelt1-1/+5
2022-09-13RISC-V: Clean up the Zicbom block size probingPalmer Dabbelt1-0/+1
2022-07-29riscv: Add support for non-coherent devices using zicbom extensionHeiko Stuebner1-0/+10
2020-06-08mm: rename flush_icache_user_range to flush_icache_user_pageChristoph Hellwig1-1/+2
2020-06-08riscv: use asm-generic/cacheflush.hChristoph Hellwig1-59/+3
2020-03-03riscv: Use flush_icache_mm for flush_icache_user_rangeGuo Ren1-1/+1
2019-07-18riscv: fix build break after macro-to-function conversion in generic cacheflu...Paul Walmsley1-4/+59
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner1-9/+1
2019-05-17riscv: move flush_icache_{all,mm} to cacheflush.cGary Guo1-1/+1
2018-06-07riscv: use NULL instead of a plain 0Luc Van Oostenryck1-1/+1
2017-11-30RISC-V: Allow userspace to flush the instruction cacheAndrew Waterman1-0/+6
2017-11-30RISC-V: Flush I$ when making a dirty page executableAndrew Waterman1-4/+20
2017-09-27RISC-V: Atomic and Locking CodePalmer Dabbelt1-0/+39