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path: root/arch/riscv/include/asm/hwcap.h
AgeCommit message (Expand)AuthorFilesLines
2022-10-02RISC-V: Probe Svinval extension form ISA stringMayuresh Chitale1-0/+4
2022-08-12RISC-V: Add Sstc extension supportPalmer Dabbelt1-0/+1
2022-08-12RISC-V: Enable sstc extension parsing from DTAtish Patra1-0/+1
2022-08-11arch/riscv: add Zihintpause supportDao Lu1-0/+5
2022-07-29riscv: Add support for non-coherent devices using zicbom extensionHeiko Stuebner1-0/+1
2022-06-16riscv: introduce unified static key mechanism for ISA extensionsJisheng Zhang1-0/+25
2022-05-12riscv: add RISC-V Svpbmt extension supportHeiko Stuebner1-0/+1
2022-03-22RISC-V: Add sscofpmf extension supportAtish Patra1-0/+1
2022-03-17RISC-V: Improve /proc/cpuinfo output for ISA extensionsAtish Patra1-0/+7
2022-03-17RISC-V: Implement multi-letter ISA extension probing frameworkAtish Patra1-0/+18
2020-05-05RISC-V: Add bitmap reprensenting ISA features common across CPUsAnup Patel1-0/+22
2019-11-12riscv: clean up the macro format in each header fileZong Li1-3/+4
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234Thomas Gleixner1-12/+1
2017-09-27RISC-V: ELF and module implementationPalmer Dabbelt1-0/+37