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path: root/arch/riscv/include/asm/smp.h
AgeCommit message (Expand)AuthorFilesLines
2023-05-15riscv: Switch to hotplug core state synchronizationThomas Gleixner1-1/+1
2023-04-08RISC-V: Allow marking IPIs as suitable for remote FENCEsAnup Patel1-2/+16
2023-04-08RISC-V: Treat IPIs as normal Linux IRQsAnup Patel1-14/+21
2022-11-30riscv: kexec: Fixup crash_smp_send_stop without multi coresGuo Ren1-0/+3
2022-07-20riscv: smp: Add 64bit hartid support on RV64Sunil V L1-2/+2
2022-01-20RISC-V: Do not use cpumask data structure for hartid bitmapAtish Patra1-2/+0
2022-01-09RISC-V: Use common riscv_cpuid_to_hartid_mask() for both SMP=y and SMP=nSean Christopherson1-8/+2
2022-01-09riscv: remove cpu_stop()Jisheng Zhang1-2/+0
2021-04-26riscv: Constify sbi_ipi_opsJisheng Zhang1-2/+2
2020-08-20RISC-V: Add mechanism to provide custom IPI operationsAnup Patel1-0/+19
2020-08-05RISC-V: Fix build warning for smpboot.cAtish Patra1-0/+3
2020-06-10RISC-V: self-contained IPI handling routineAnup Patel1-0/+3
2020-03-31RISC-V: Support cpu hotplugAtish Patra1-0/+17
2020-03-31RISC-V: Implement new SBI v0.2 extensionsAtish Patra1-0/+7
2019-09-05riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig1-6/+0
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner1-9/+1
2019-03-04RISC-V: Move cpuid to hartid mapping to SMP.Atish Patra1-5/+13
2018-10-23RISC-V: Show IPI statsAnup Patel1-0/+9
2018-10-23RISC-V: Add logical CPU indexing for RISC-VAtish Patra1-1/+23
2018-10-23RISC-V: Provide a cleaner raw_smp_processor_id()Palmer Dabbelt1-10/+4
2018-08-13clocksource: new RISC-V SBI timer driverPalmer Dabbelt1-3/+0
2018-08-13RISC-V: simplify software interrupt / IPI codeChristoph Hellwig1-3/+0
2017-09-27RISC-V: Init and Halt CodePalmer Dabbelt1-0/+52