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2024-01-11Merge patch series "RISC-V SBI debug console extension support"Palmer Dabbelt1-0/+10
2024-01-11riscv: sbi: Introduce system suspend supportAndrew Jones1-0/+9
2024-01-11Merge patch series "riscv: enable EFFICIENT_UNALIGNED_ACCESS and DCACHE_WORD_...Palmer Dabbelt2-0/+42
2024-01-10RISC-V: Add SBI debug console helper routinesAnup Patel1-0/+5
2024-01-10RISC-V: Add stubs for sbi_console_putchar/getchar()Anup Patel1-0/+5
2024-01-10riscv: select DCACHE_WORD_ACCESS for efficient unaligned access HWJisheng Zhang2-0/+42
2024-01-10Merge patch series "riscv: hwprobe: add Zicond, Zacas and Ztso support"Palmer Dabbelt2-0/+5
2024-01-10riscv: hwprobe: export Zicond extensionClément Léger1-0/+1
2024-01-10riscv: hwprobe: export Zacas ISA extensionClément Léger1-0/+1
2024-01-10riscv: add ISA extension parsing for ZacasClément Léger1-0/+1
2024-01-10riscv: hwprobe: export Ztso ISA extensionClément Léger1-0/+1
2024-01-10riscv: add ISA extension parsing for ZtsoClément Léger1-0/+1
2024-01-10Merge patch series "Fix XIP boot and make XIP testable in QEMU"Palmer Dabbelt1-1/+1
2024-01-10riscv: Remove SHADOW_OVERFLOW_STACK_SIZE macroSong Shuai1-1/+0
2024-01-10Merge remote-tracking branch 'palmer/fixes' into for-nextPalmer Dabbelt1-0/+1
2024-01-10Merge patch series "riscv: CPU operations cleanup"Palmer Dabbelt1-12/+2
2024-01-10Merge patch series "RISC-V: hwprobe: Introduce which-cpus"Palmer Dabbelt2-0/+27
2024-01-10riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macroFrederik Haxel1-1/+1
2024-01-09riscv: Check if the code to patch lies in the exit sectionAlexandre Ghiti1-0/+1
2024-01-05riscv: Use the same CPU operations for all CPUsSamuel Holland1-2/+2
2024-01-05riscv: Remove unused members from struct cpu_operationsSamuel Holland1-10/+0
2024-01-03RISC-V: hwprobe: Introduce which-cpus flagAndrew Jones2-0/+27
2024-01-03RISC-V: Remove the removed single-letter extensionsPalmer Dabbelt1-6/+0
2023-12-20Merge patch series "riscv: Use READ_ONCE()/WRITE_ONCE() for pte accesses"Palmer Dabbelt3-44/+15
2023-12-20riscv: Use accessors to page table entries instead of direct dereferenceAlexandre Ghiti3-39/+10
2023-12-20riscv: Use WRITE_ONCE() when setting page table entriesAlexandre Ghiti2-5/+5
2023-12-13riscv: hwprobe: export Zfa ISA extensionClément Léger1-0/+1
2023-12-13riscv: add ISA extension parsing for ZfaClément Léger1-0/+1
2023-12-13riscv: hwprobe: export Zvfh[min] ISA extensionsClément Léger1-0/+2
2023-12-13riscv: add ISA extension parsing for Zvfh[min]Clément Léger1-0/+2
2023-12-13riscv: hwprobe: export Zhintntl ISA extensionClément Léger1-0/+1
2023-12-13riscv: add ISA extension parsing for ZihintntlClément Léger1-0/+1
2023-12-13riscv: hwprobe: export Zfh[min] ISA extensionsClément Léger1-0/+2
2023-12-13riscv: add ISA extension parsing for Zfh/Zfh[min]Clément Léger1-0/+2
2023-12-13riscv: hwprobe: export vector crypto ISA extensionsClément Léger1-0/+10
2023-12-13riscv: add ISA extension parsing for vector cryptoClément Léger1-1/+11
2023-12-13riscv: hwprobe: add support for scalar crypto ISA extensionsClément Léger1-0/+9
2023-12-13riscv: add ISA extension parsing for scalar cryptoEvan Green2-1/+14
2023-12-13riscv: hwprobe: export missing Zbc ISA extensionClément Léger1-0/+1
2023-12-13riscv: add ISA extension parsing for ZbcClément Léger1-0/+1
2023-11-10Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds17-121/+419
2023-11-09riscv: Optimize bitops with Zbb extensionXiao Wang1-3/+251
2023-11-09riscv: Rearrange hwcap.h and cpufeature.hXiao Wang6-94/+87
2023-11-09Merge patch "drivers: perf: Do not broadcast to other cpus when starting a co...Palmer Dabbelt3-2/+43
2023-11-08Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds15-17/+156
2023-11-08RISC-V: Probe misaligned access speed in parallelEvan Green1-1/+0
2023-11-08Merge patch series "riscv: Add remaining module relocations and tests"Palmer Dabbelt1-1/+4
2023-11-08riscv: Add remaining module relocationsCharlie Jenkins1-1/+4
2023-11-06Merge patch series "riscv: tlb flush improvements"Palmer Dabbelt3-8/+18
2023-11-06riscv: Improve flush_tlb_kernel_range()Alexandre Ghiti1-5/+6