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2023-11-06Merge patch series "riscv: tlb flush improvements"Palmer Dabbelt3-8/+18
2023-11-06riscv: Improve flush_tlb_kernel_range()Alexandre Ghiti1-5/+6
2023-11-06riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlbAlexandre Ghiti2-3/+3
2023-11-06riscv: Improve tlb_flush()Alexandre Ghiti2-1/+10
2023-11-06riscv: mm: update T-Head memory type definitionsJisheng Zhang1-5/+9
2023-11-05Merge patch series "Improve PTDUMP and introduce new fields"Palmer Dabbelt1-2/+2
2023-11-05riscv: Improve PTDUMP to show RSW with non-zero valueYu Chien Peter Lin1-2/+2
2023-11-05RISC-V: capitalise CMO op macrosConor Dooley2-7/+7
2023-11-05Merge patch series "Add support to handle misaligned accesses in S-mode"Palmer Dabbelt3-0/+41
2023-11-03RISC-V: hwprobe: Fix vDSO SIGSEGVAndrew Jones1-0/+5
2023-11-03Merge patch series "riscv: SCS support"Palmer Dabbelt5-4/+111
2023-11-03Merge patch "riscv: errata: improve T-Head CMO"Palmer Dabbelt1-9/+9
2023-11-03riscv: errata: prefix T-Head mnemonics with th.Icenowy Zheng1-7/+7
2023-11-01riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGNClément Léger1-0/+9
2023-11-01riscv: report misaligned accesses emulation to hwprobeClément Léger1-0/+18
2023-11-01riscv: add support for misaligned trap handling in S-modeClément Léger1-0/+14
2023-11-01Merge patch series "RISC-V: ACPI improvements"Palmer Dabbelt1-0/+6
2023-11-01riscv: mm: Update the comment of CONFIG_PAGE_OFFSETSong Shuai1-2/+2
2023-11-01riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpauseMinda Chen1-1/+1
2023-11-01riscv/mm: Fix the comment for swap pte formatXiao Wang1-1/+1
2023-11-01RISC-V: Provide pgtable_l5_enabled on rv32Palmer Dabbelt2-1/+3
2023-10-28riscv: Use separate IRQ shadow call stacksSami Tolvanen1-0/+7
2023-10-28riscv: Implement Shadow Call StackSami Tolvanen3-0/+66
2023-10-28riscv: Move global pointer loading to a macroSami Tolvanen1-0/+8
2023-10-28riscv: Deduplicate IRQ stack switchingSami Tolvanen2-0/+8
2023-10-28riscv: VMAP_STACK overflow detection thread-safeDeepak Gupta3-4/+22
2023-10-26RISC-V: ACPI: RHCT: Add function to get CBO block sizesSunil V L1-0/+6
2023-09-21RISC-V: hwprobe: Expose Zicboz extension and its block sizeAndrew Jones2-1/+3
2023-09-21RISC-V: Enable cbo.zero in usermodeAndrew Jones3-0/+18
2023-09-12riscv: errata: fix T-Head dcache.cva encodingIcenowy Zheng1-2/+2
2023-09-10Merge tag 'riscv-for-linus-6.6-mw2-2' of git://git.kernel.org/pub/scm/linux/k...Linus Torvalds9-9/+54
2023-09-08Merge patch series "bpf, riscv: use BPF prog pack allocator in BPF JIT"Palmer Dabbelt1-0/+1
2023-09-08Merge patch series "riscv: Introduce KASLR"Palmer Dabbelt2-0/+5
2023-09-08Merge patch "RISC-V: Add ptrace support for vectors"Palmer Dabbelt1-4/+9
2023-09-08Merge patch series "Add non-coherent DMA support for AX45MP"Palmer Dabbelt4-0/+37
2023-09-08Merge patch series "RISC-V: Probe for misaligned access speed"Palmer Dabbelt2-5/+2
2023-09-07Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds4-4/+29
2023-09-06riscv: implement a memset like function for textPuranjay Mohan1-0/+1
2023-09-06riscv: libstub: Implement KASLR by using generic functionsAlexandre Ghiti1-0/+2
2023-09-06riscv: Introduce virtual kernel mapping KASLRAlexandre Ghiti1-0/+3
2023-09-01RISC-V: Add ptrace support for vectorsAndy Chiu1-4/+9
2023-09-01riscv: mm: dma-noncoherent: nonstandard cache operations supportLad Prabhakar1-0/+28
2023-09-01riscv: errata: Add Andes alternative portsLad Prabhakar2-0/+8
2023-09-01riscv: asm: vendorid_list: Add Andes Technology to the vendors listLad Prabhakar1-0/+1
2023-09-01RISC-V: alternative: Remove feature_probe_funcEvan Green1-5/+0
2023-09-01RISC-V: Probe for unaligned access speedEvan Green1-0/+2
2023-09-01Merge tag 'riscv-for-linus-6.6-mw1' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds14-23/+245
2023-08-31Merge tag 'x86_shstk_for_6.6-rc1' of git://git.kernel.org/pub/scm/linux/kerne...Linus Torvalds1-3/+3
2023-08-31Merge tag 'kvm-riscv-6.6-1' of https://github.com/kvm-riscv/linux into HEADPaolo Bonzini4-4/+29
2023-08-31Merge patch series "RISC-V: mm: Make SV48 the default address space"Palmer Dabbelt3-12/+75