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path: root/arch/riscv/mm/tlbflush.c
AgeCommit message (Expand)AuthorFilesLines
2023-03-30riscv: mm: Fix incorrect ASID argument when flushing TLBDylan Jhong1-1/+1
2023-03-22Revert "riscv: mm: notify remote harts about mmu cache updates"Sergey Matyukevich1-11/+17
2023-01-07riscv: mm: notify remote harts about mmu cache updatesSergey Matyukevich1-17/+11
2022-01-20RISC-V: Do not use cpumask data structure for hartid bitmapAtish Patra1-7/+2
2021-07-01riscv: add ASID-based tlbflushing methodsGuo Ren1-7/+40
2021-07-01riscv: pass the mm_struct to __sbi_tlb_flush_rangeChristoph Hellwig1-9/+6
2021-05-22riscv: mm: add THP support on 64-bitNanyong Sun1-0/+7
2021-05-22riscv: mm: add param stride for __sbi_tlb_flush_rangeNanyong Sun1-5/+5
2019-10-29RISC-V: Issue a tlb page flush if possibleAtish Patra1-1/+4
2019-10-29RISC-V: Issue a local tlbflush if possible.Atish Patra1-2/+17
2019-10-29RISC-V: Do not invoke SBI call if cpumask is emptyAtish Patra1-0/+3
2019-09-05riscv: move the TLB flush logic out of lineChristoph Hellwig1-0/+35