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2021-09-08riscv: dts: microchip: Add ethernet0 to the aliases nodeBin Meng1-0/+4
2021-09-08riscv: dts: microchip: Use 'local-mac-address' for emac1Bin Meng1-1/+1
2021-09-03riscv: Ensure the value of FP registers in the core dump file is up to dateVincent Chen1-0/+4
2021-08-26riscv: Fix a number of free'd resources in init_resources()Petr Pavlu1-2/+2
2021-08-18riscv: kexec: do not add '-mno-relax' flag if compiler doesn't support itChangbin Du1-1/+1
2021-08-12riscv: dts: fix memory size for the SiFive HiFive UnmatchedQiu Wenbo1-1/+1
2021-08-12riscv: Disable STACKPROTECTOR_PER_TASK if GCC_PLUGIN_RANDSTRUCT is enabledGuenter Roeck1-0/+1
2021-08-12riscv: stacktrace: Fix NULL pointer dereferenceJisheng Zhang1-1/+1
2021-08-04bpf: Introduce BPF nospec instruction for mitigating Spectre v4Daniel Borkmann2-0/+8
2021-07-28RISC-V: load initrd wherever it fits into memoryHeinrich Schuchardt1-2/+2
2021-07-28riscv: Fix 32-bit RISC-V boot failureBin Meng1-1/+3
2021-07-14sched/core: Initialize the idle task with preemption disabledValentin Schneider1-1/+0
2021-06-19riscv: dts: fu740: fix cache-controller interruptsDavid Abdurachmanov1-1/+1
2021-06-19riscv: Ensure BPF_JIT_REGION_START aligned with PMD sizeJisheng Zhang2-4/+3
2021-06-19riscv: kasan: Fix MODULES_VADDR evaluation due to local variables' nameJisheng Zhang1-4/+4
2021-06-13riscv: sifive: fix Kconfig errata warningRandy Dunlap1-0/+1
2021-06-13riscv32: Use medany C model for modulesKhem Raj1-1/+1
2021-06-12riscv: Fix BUILTIN_DTB for sifive and microchip socAlexandre Ghiti2-0/+2
2021-06-11riscv: alternative: fix typo in macro nameVitaly Wool1-2/+2
2021-06-11riscv: code patching only works on !XIP_KERNELJisheng Zhang1-9/+9
2021-06-11riscv: xip: support runtime trap patchingVitaly Wool2-5/+23
2021-06-02Merge remote-tracking branch 'riscv/riscv-wx-mappings' into fixesPalmer Dabbelt1-2/+6
2021-06-02RISC-V: Fix memblock_free() usages in init_resources()Wende Tan1-2/+2
2021-06-02riscv: skip errata_cip_453.o if CONFIG_ERRATA_SIFIVE_CIP_453 is disabledVincent1-1/+1
2021-06-02riscv: mm: Fix W+X mappings at bootJisheng Zhang1-2/+6
2021-05-29riscv: Use -mno-relax when using lld linkerKhem Raj1-0/+9
2021-05-23riscv: kexec: Fix W=1 build warningsJisheng Zhang2-7/+8
2021-05-23riscv: kprobes: Fix build error when MMU=nJisheng Zhang1-0/+2
2021-05-23riscv: Select ARCH_USE_MEMTESTKefeng Wang1-0/+1
2021-05-23riscv: stacktrace: fix the riscv stacktrace when CONFIG_FRAME_POINTER enabledChen Huang1-7/+7
2021-05-06riscv: remove unused handle_exception symbolRouven Czerwinski1-2/+0
2021-05-06riscv: Consistify protect_kernel_linear_mapping_text_rodata() useGeert Uytterhoeven3-4/+7
2021-05-06riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=yVincent Chen1-2/+2
2021-05-06riscv: Only extend kernel reservation if mapped read-onlyGeert Uytterhoeven1-2/+7
2021-05-06Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds63-214/+2525
2021-05-05Merge branch 'akpm' (patches from Andrew)Linus Torvalds1-4/+1
2021-05-05Merge tag 'pci-v5.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/gi...Linus Torvalds1-0/+33
2021-05-05mm: generalize SYS_SUPPORTS_HUGETLBFS (rename as ARCH_SUPPORTS_HUGETLBFS)Anshuman Khandual1-4/+1
2021-05-04Merge tag 'm68knommu-for-v5.13' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds1-0/+1
2021-05-04riscv: dts: Add PCIe support for the SiFive FU740-C000 SoCGreentime Hu1-0/+33
2021-05-02Merge branch 'work.misc' of git://git.kernel.org/pub/scm/linux/kernel/git/vir...Linus Torvalds1-1/+0
2021-05-01RISC-V: Always define XIP_FIXUPPalmer Dabbelt1-10/+13
2021-05-01riscv: Remove 32b kernel mapping from page table dumpAlexandre Ghiti1-3/+3
2021-05-01riscv: Fix 32b kernel build with CONFIG_DEBUG_VIRTUAL=yAlexandre Ghiti1-1/+1
2021-05-01RISC-V: Fix error code returned by riscv_hartid_to_cpuid()Anup Patel1-1/+1
2021-04-30mm: move mem_init_print_info() into mm_init()Kefeng Wang1-1/+0
2021-04-26RISC-V: Enable Microchip PolarFire ICICLE SoCAtish Patra1-0/+4
2021-04-26RISC-V: Initial DTS for Microchip ICICLE boardAtish Patra4-0/+404
2021-04-26RISC-V: Add Microchip PolarFire SoC kconfig optionAtish Patra1-0/+7
2021-04-26RISC-V: enable XIPVitaly Wool11-19/+424