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path: root/drivers/clk/bcm
AgeCommit message (Expand)AuthorFilesLines
2017-06-21clk: iproc: Remove __init marking on iproc_pll_clk_setup()Stephen Boyd1-6/+6
2017-06-20clk: bcm: Add clocks for Stingray SOCSandeep Tripathy3-0/+336
2017-06-03clk: bcm2835: Minimise clock jitter for PCM clockPhil Elwell1-5/+29
2017-06-03clk: bcm2835: Limit PCM clock to OSC and PLLD_PERPhil Elwell1-1/+26
2017-06-03clk: bcm2835: Correct the prediv logicPhil Elwell1-1/+3
2017-04-19clk: ns2: Correct SDIO bitsBharat Kumar Reddy Gooty1-1/+1
2017-04-12clk: iproc: Remove redundant checkRay Jui1-1/+1
2017-01-21clk: bcm2835: Add leaf clock measurement support, disabled by defaultEric Anholt1-25/+119
2017-01-21clk: bcm2835: Register the DSI0/DSI1 pixel clocks.Eric Anholt1-12/+109
2017-01-21clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.Eric Anholt1-14/+28
2016-12-12clk: bcm: Fix 'maybe-uninitialized' warning in bcm2835_clock_choose_div_and_p...Boris Brezillon1-1/+1
2016-12-09clk: bcm: Make COMMON_CLK_IPROC into a libraryStephen Boyd1-11/+5
2016-12-09clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clockBoris Brezillon1-1/+6
2016-12-09clk: bcm: Support rate change propagation on bcm2835 clocksBoris Brezillon1-4/+63
2016-12-09clk: bcm2835: Avoid overwriting the div info when disabling a pll_div clkBoris Brezillon1-1/+3
2016-11-24Merge branch 'clk-fixes' into clk-nextStephen Boyd1-1/+1
2016-11-24clk: bcm: Fix unmet Kconfig dependencies for CLK_BCM_63XXFlorian Fainelli1-1/+1
2016-11-23clk: bcm2835: Fix ->fixed_divider of pllh_auxBoris Brezillon1-1/+1
2016-10-18clk: bcm2835: Clamp the PLL's requested rate to the hardware limits.Eric Anholt1-7/+4
2016-09-17clk: bcm: Add driver for BCM53573 ILP clockRafał Miłecki2-0/+149
2016-09-15clk: bcm2835: Migrate to clk_hw based registration and OF APIsStephen Boyd2-55/+58
2016-09-15clk: iproc: Make clocks visible optionsJon Mason2-5/+32
2016-09-14clk-kona-setup: Use kmalloc_array() in parent_process()Markus Elfring1-2/+2
2016-09-07clk: bcm2835: Skip PLLC clocks when deciding on a new clock parentEric Anholt1-0/+23
2016-09-07clk: bcm2835: Mark the CM SDRAM clock's parent as criticalEric Anholt1-0/+25
2016-09-07clk: bcm2835: Mark GPIO clocks enabled at boot as criticalEric Anholt1-1/+9
2016-09-07clk: bcm2835: Mark the VPU clock as criticalEric Anholt1-1/+4
2016-08-25clk: bcm: kona: Migrate to clk_hw based registration and OF APIsStephen Boyd3-51/+41
2016-06-30clk: bcm: iproc: Migrate to clk_hw based registration and OF APIsStephen Boyd3-35/+33
2016-06-21clk: iproc: fix missing include of clk-iproc.hBen Dooks1-0/+2
2016-05-06clk: bcm/kona: Do not use sizeof on pointer typeVaishali Thakkar1-1/+2
2016-04-20clk: bcm2835: Fix PLL poweronEric Anholt1-0/+4
2016-04-20clk: bcm2835: Fix compiler warnings on 64-bit buildsEric Anholt1-4/+4
2016-03-17clk: bcm2835: add missing osc and per clocksMartin Sperl1-0/+90
2016-03-17clk: bcm2835: add missing PLL clock dividersMartin Sperl1-0/+32
2016-03-17clk: bcm2835: enable management of PCM clockMartin Sperl1-0/+7
2016-03-17clk: bcm2835: reorganize bcm2835_clock_array assignmentMartin Sperl1-459/+393
2016-03-17clk: bcm2835: remove use of BCM2835_CLOCK_COUNT in driverMartin Sperl1-73/+94
2016-03-17clk: bcm2835: expose raw clock-registers via debugfsMartin Sperl1-0/+101
2016-03-17clk: bcm2835: clean up coding style issuesMartin Sperl1-6/+2
2016-03-17clk: bcm2835: correctly enable fractional clock supportMartin Sperl1-6/+39
2016-03-17clk: bcm2835: divider value has to be 1 or moreMartin Sperl1-2/+3
2016-03-17clk: bcm2835: add locking to pll*_on/off methodsMartin Sperl1-0/+4
2016-03-17clk: bcm2835: pll_off should only update CM_PLL_ANARSTMartin Sperl1-2/+8
2016-03-16clk: bcm2835: fix check of error code returned by devm_ioremap_resource()Vladimir Zapolskiy1-2/+2
2016-03-03clk: bcm: Remove CLK_IS_ROOTStephen Boyd1-6/+3
2016-02-26clk: bcm2835: added missing clock register definitionsMartin Sperl1-0/+13
2016-02-16Merge branch 'clk-bcm2835' into clk-nextMichael Turquette1-16/+9
2016-02-16clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate()Eric Anholt1-11/+2
2016-02-16clk: bcm2835: Fix setting of PLL divider clock ratesEric Anholt1-5/+7