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path: root/drivers/clk/ingenic/cgu.c
AgeCommit message (Expand)AuthorFilesLines
2021-06-28clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil1-13/+27
2021-06-28clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil1-2/+2
2021-06-28clk: ingenic: Read bypass register only when there is onePaul Cercueil1-8/+11
2021-06-28clk: Support bypassing dividersPaul Cercueil1-11/+22
2020-12-20clk: ingenic: Fix divider calculation with div tablesPaul Cercueil1-4/+10
2020-10-14clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_ratePaul Cercueil1-0/+2
2020-10-14clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENTPaul Cercueil1-7/+7
2020-10-14clk: ingenic: Don't use CLK_SET_RATE_GATE for PLLPaul Cercueil1-2/+7
2020-10-14clk: ingenic: Use readl_poll_timeout instead of custom loopPaul Cercueil1-26/+29
2020-10-14clk: ingenic: Use to_clk_info() macro for all clocksPaul Cercueil1-39/+15
2020-05-29clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)1-3/+13
2020-05-29clk: Ingenic: Remove unnecessary spinlock when reading registers.周琰杰 (Zhou Yanjie)1-11/+1
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-6/+35
2019-06-07clk: ingenic: Add support for divider tablesPaul Cercueil1-6/+35
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner1-10/+1
2019-05-15clk: Remove io.h from clk-provider.hStephen Boyd1-0/+1
2019-02-26clk: ingenic: Remove set but not used variable 'enable'YueHaibing1-2/+1
2019-02-22clk: ingenic: Fix round_rate misbehaving with non-integer dividersPaul Cercueil1-5/+5
2018-06-02clk: ingenic: Support specifying "wait for clock stable" delayPaul Cercueil1-0/+3
2018-06-02clk: ingenic: Add support for clocks whose gate bit is invertedPaul Cercueil1-2/+3
2018-01-19clk: ingenic: Add code to enable/disable PLLsPaul Cercueil1-15/+74
2018-01-19clk: ingenic: support PLLs with no bypass bitPaul Cercueil1-1/+2
2018-01-19clk: ingenic: Fix recalc_rate for clocks with fixed dividerPaul Cercueil1-0/+2
2017-11-03Update MIPS email addressesPaul Burton1-1/+1
2016-05-13clk: ingenic: Allow divider value to be dividedHarvey Hunt1-1/+10
2015-07-20clk: ingenic: Include clk.hStephen Boyd1-0/+1
2015-06-21clk: ingenic: add driver for Ingenic SoC CGU clocksPaul Burton1-0/+711