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path: root/drivers/clk/mediatek/clk-mt8173.c
AgeCommit message (Expand)AuthorFilesLines
2023-01-31clk: mediatek: mt8173: Break down clock drivers and allow module buildAngeloGioacchino Del Regno1-1187/+0
2023-01-31clk: mediatek: mt8173: Remove mtk_clk_enable_critical()AngeloGioacchino Del Regno1-25/+16
2023-01-31clk: mediatek: mt8173: Migrate to platform driver and common probeAngeloGioacchino Del Regno1-207/+276
2023-01-31clk: mediatek: clk-mtk: Propagate struct device for compositesAngeloGioacchino Del Regno1-4/+6
2023-01-31clk: mediatek: cpumux: Propagate struct device where possibleAngeloGioacchino Del Regno1-2/+2
2023-01-31clk: mediatek: clk-gate: Propagate struct device with mtk_clk_register_gates()AngeloGioacchino Del Regno1-12/+12
2022-11-29clk: mediatek: mt8173: Drop flags for main/sys/univpll fixed factorsAngeloGioacchino Del Regno1-38/+38
2022-06-16clk: mediatek: reset: Support nonsequence base offsets of reset registersRex-BC Chen1-4/+7
2022-06-16clk: mediatek: reset: Revise structure to control reset registerRex-BC Chen1-2/+17
2022-06-16clk: mediatek: reset: Merge and revise reset register functionRex-BC Chen1-2/+2
2022-05-20clk: mediatek: mt8173: Switch to clk_hw provider APIsChen-Yu Tsai1-5/+4
2022-05-20clk: mediatek: Switch to clk_hw provider APIsChen-Yu Tsai1-7/+5
2022-05-20clk: mediatek: Replace 'struct clk' with 'struct clk_hw'Chen-Yu Tsai1-26/+26
2022-05-19clk: mediatek: use en_mask as a pure div_en_maskChun-Jie Chen1-14/+14
2022-02-17clk: mediatek: pll: Split definitions into separate header fileChen-Yu Tsai1-2/+3
2020-04-13clk / soc: mediatek: Move mt8173 MMSYS to platform driverMatthias Brugger1-104/+0
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner1-9/+1
2019-02-26clk: mediatek: correct cpu clock name for MT8173 SoCSeiya Wang1-2/+2
2017-06-20clk: mediatek: export cpu multiplexer clock for MT8173 SoCsSean Wang1-0/+23
2016-09-21clk: mediatek: clk-mt8173: Unmap region obtained by of_iomapArvind Yadav1-1/+3
2016-05-06clk: mediatek: remove hdmitx_dig_cts from TOP clocksPhilipp Zabel1-1/+0
2016-05-06clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock outputPhilipp Zabel1-0/+5
2016-05-06clk: mediatek: make dpi0_sel propagate rate changesPhilipp Zabel1-1/+5
2015-10-01clk: mediatek: Add USB clock support in MT8173 APMIXEDSYSJames Liao1-0/+47
2015-10-01clk: mediatek: Add subsystem clocks of MT8173James Liao1-0/+267
2015-10-01clk: mediatek: Fix rate and dependency of MT8173 clocksJames Liao1-6/+13
2015-10-01clk: mediatek: Add __initdata and __init for data and functionsJames Liao1-3/+3
2015-10-01clk: mediatek: Remove unused code from MT8173.James Liao1-2/+0
2015-10-01clk: mediatek: Removed unused dpi_ck clock from MT8173James Liao1-1/+0
2015-10-01clk: mediatek: add 13mhz clock for MT8173Joe.C1-0/+5
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd1-0/+1
2015-07-28clk: mediatek: Add MT8173 MMPLL change rate supportJames Liao1-3/+21
2015-07-20clk: mediatek: Properly include clk.hStephen Boyd1-0/+1
2015-07-07clk: mediatek: mt8173: Fix enabling of critical clocksSascha Hauer1-5/+21
2015-06-05clk: mediatek: Fix apmixedsys clock registrationJames Liao1-1/+1
2015-05-06clk: mediatek: Add basic clocks for Mediatek MT8173.James Liao1-0/+830